CN116347890A

CN116347890A - Semiconductor structure and manufacturing method thereof

Info

Publication number: CN116347890A
Application number: CN202310422893.8A
Authority: CN
Inventors: 吴俊�; 张民慧; 王金春; 江长
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-04-14
Filing date: 2023-04-14
Publication date: 2023-06-27

Abstract

The embodiment of the disclosure relates to the field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof, wherein the method comprises the following steps: providing a first substrate; forming a conductive layer on a first substrate; forming a filling layer on the conductive layer; forming a capacitor hole penetrating through the filling layer in the filling layer, wherein the capacitor hole exposes part of the surface of the conductive layer; forming a second electrode layer, a dielectric layer and a first electrode layer which are sequentially stacked in the capacitor hole, wherein the first electrode layer, the dielectric layer and the second electrode layer form a capacitor structure; providing a second substrate, wherein the surface of the second substrate is provided with a contact structure, and the position of the contact structure corresponds to the position of the first electrode layer; the first substrate is opposite to the second substrate, so that the first electrode layer is opposite to and contacted with the contact structure, and the first substrate and the second substrate are bonded; the first substrate is removed. The semiconductor structure and the manufacturing method thereof provided by the embodiment of the disclosure are at least beneficial to improving the performance of the semiconductor structure.

Description

Semiconductor structure and manufacturing method thereof

Technical Field

Embodiments of the present disclosure relate to the field of semiconductors, and more particularly, to a semiconductor structure and a method for fabricating the same.

Background

The memory is a memory means for storing programs and various data information. Random Access Memory (Random Access Memory, RAM) used in a typical computer system can be divided into dynamic Random Access Memory (Dynamic Random Access Memory, DRAM) and Static Random Access Memory (SRAM), which are semiconductor Memory devices commonly used in computers and are composed of a plurality of repeated Memory cells.

The memory cell generally includes a capacitor and a transistor, a drain of the transistor is connected to a bit line structure, a source of the transistor is connected to the capacitor, the capacitor includes a capacitance contact structure and a capacitance, and a word line structure of the memory cell can control the opening or closing of a channel region of the transistor, thereby reading data information stored in the capacitor through the bit line structure or writing data information into the capacitor through the bit line structure for storage.

Disclosure of Invention

Embodiments of the present disclosure provide a semiconductor structure and a method of manufacturing the same, which are at least advantageous for improving performance of the semiconductor structure.

According to some embodiments of the present disclosure, an aspect of an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including: providing a first substrate; forming a conductive layer on a first substrate; forming a filling layer on the conductive layer; forming a capacitor hole penetrating through the filling layer in the filling layer, wherein the capacitor hole exposes part of the surface of the conductive layer; forming a second electrode layer, a dielectric layer and a first electrode layer which are sequentially stacked in the capacitor hole, wherein the second electrode layer covers the inner wall of the capacitor hole and the surface of the filling layer; the dielectric layer covers the surface of the second electrode layer; the first electrode layer covers the surface of the dielectric layer and is filled with the capacitor holes, and the first electrode layer, the dielectric layer and the second electrode layer form a capacitor structure; providing a second substrate, wherein the surface of the second substrate is provided with a contact structure, and the position of the contact structure corresponds to the position of the first electrode layer; the first substrate is opposite to the second substrate, so that the first electrode layer is opposite to and contacted with the contact structure, and the first substrate and the second substrate are bonded; the first substrate is removed.

In some embodiments, providing the first substrate comprises: providing a first substrate; forming a buffer layer on a first substrate; and forming a conductive layer on the first substrate includes: a conductive layer is formed on the buffer layer.

In some embodiments, forming a capacitive hole in the fill layer through the fill layer includes: the filling layer is patterned to form a capacitor hole, wherein the conductive layer serves as an etching stop layer when the capacitor hole is formed.

In some embodiments, the material of the fill layer comprises at least one of doped polysilicon, silicon germanium, tungsten, platinum nickel, titanium, tantalum, cobalt, tantalum nitride, titanium nitride, and ruthenium; and/or the material of the conductive layer comprises a metallic material capable of bonding with the material of the second electrode layer.

In some embodiments, the material of the filler layer is the same as the material of the second electrode layer, such that the filler layer is used as the second electrode layer; forming the capacitor structure includes: forming a dielectric layer and a first electrode layer which are sequentially stacked in the capacitor hole, wherein the dielectric layer covers the inner wall of the capacitor hole and the surface of the filling layer; the first electrode layer covers the surface of the dielectric layer and is filled with the capacitor hole, and the first electrode layer, the dielectric layer and the filling layer form a capacitor structure.

In some embodiments, after forming the capacitive structure, before bonding the first substrate and the second substrate, further comprising: a surface of the first electrode layer, which is far away from the first substrate, is subjected to planarization treatment so that a top surface of the first electrode layer is flush with a top surface of the dielectric layer.

In some embodiments, the bonding of the first substrate and the second substrate is followed by an annealing treatment, the process conditions of which include: the annealing time is 3-8 minutes, and the annealing temperature is 250-350 ℃.

In some embodiments, the second base includes a second substrate on which the transistor, the word line, and the bit line are disposed, the gate of the transistor is electrically connected to the word line, one of the source or the drain of the transistor is electrically connected to the bit line, and the other of the source or the drain of the transistor is electrically connected to the contact structure.

According to some embodiments of the present disclosure, another aspect of embodiments of the present disclosure further provides a semiconductor structure, including: the surface of the second substrate is provided with a contact structure; the capacitor structure is arranged on the second substrate and comprises a first electrode layer, a dielectric layer and a second electrode layer which are sequentially stacked, wherein the first electrode layer extends along the thickness direction of the second substrate, and the bottom surface of the first electrode layer is contacted with the top surface of the contact structure; the dielectric layer covers the surface of the first electrode layer and the surface of the second substrate between the first electrode layers; the second electrode layer covers the surface of the dielectric layer; the filling layer fills gaps between adjacent capacitor structures; and the conductive layer covers the top surface of the filling layer and the top surface of the second electrode layer.

The technical scheme provided by the embodiment of the disclosure has at least the following advantages:

according to the semiconductor structure and the manufacturing method thereof, the conductive layer and the filling layer are formed on the first substrate, the capacitor holes are formed in the filling layer, and then the capacitor holes are filled to form the capacitor structure, so that the filling layer can be fully filled between the capacitor structures, and the capacitor holes in the filling layer can have a higher depth-to-width ratio as a whole, and further the capacitor structure formed after the capacitor holes are filled subsequently can also have a larger depth-to-width ratio, so that the capacitor structure can have a higher charge storage capacity. In addition, by forming the capacitor structure on the first substrate, and then bonding the first substrate (for example, the process of performing the capacitor structure on the first substrate) with the second substrate (for example, the process of performing the front-end process on the second substrate, including the process of transistor formation, word line formation, bit line formation, capacitor contact structure formation, landing pad formation, etc.), the structures on the first substrate and the second substrate can be fabricated simultaneously, and then a complete memory cell is formed by bonding, so that the process can be simplified obviously, and the manufacturing efficiency of the semiconductor structure can be improved.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.

Fig. 1 to 11 are schematic structural diagrams corresponding to respective steps of a method for manufacturing a semiconductor structure according to an embodiment of the disclosure.

Detailed Description

Analysis has found that as semiconductor structures continue to decrease in size, the capacitor structures require greater aspect ratios to accommodate higher charge storage amounts, typically in the shape of vertical high aspect ratio cylinders to facilitate increased surface area. The capacitor structure comprises a lower electrode layer, a dielectric layer and an upper electrode layer which are sequentially laminated, and in order to improve the stability of the capacitor structure, a supporting layer is required to be formed between the capacitor structures so as to avoid the problem that the capacitor structure collapses due to overhigh height.

In addition, the filling layer is needed to be filled between the capacitor structures and used as a connecting layer between the capacitor structures and the metal wiring layer formed in the back-end process, and the filling layer can stabilize the capacitor structures. Since the dielectric layer in the capacitor structure is greatly affected by thermal budget, if the filling layer is made by using a high temperature process, the dielectric layer is too crystallized to increase its conductivity, which results in leakage current.

In order to reduce the resistance of the filling layer and improve the service performance of the semiconductor structure, doped polysilicon is generally used as the filling layer. However, in order to reduce the resistance of the filling layer to a desired value, the concentration of the dopant ions needs to be increased, and the deposition speed of the filling layer is too fast, so that the filling layer is sealed early, and air gaps are formed inside the filling layer between the capacitor structures, thereby affecting the performance of the semiconductor structure.

According to some embodiments of the present disclosure, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, which is at least beneficial to improving performance of the semiconductor structure.

Embodiments of the present disclosure will be described in detail below with reference to the attached drawings. However, those of ordinary skill in the art will understand that in the various embodiments of the present disclosure, numerous technical details have been set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments.

Fig. 1 to 11 are schematic structural views corresponding to respective steps of a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure, wherein fig. 5 is a schematic sectional structure along the AA1 direction of fig. 4, and the method for manufacturing a semiconductor structure according to the embodiment of the present disclosure will be described in detail with reference to the accompanying drawings, specifically as follows:

referring to fig. 1 to 11, a method of manufacturing a semiconductor structure includes:

referring to fig. 1, a first substrate 100 is provided.

In some embodiments, the first base 100 may include a substrate, wherein the substrate may include: a base semiconductor, a compound semiconductor, or an alloy semiconductor. For example, the base semiconductor includes silicon, germanium (Ge); the compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, and/or a group III-V semiconductor material, etc.; the alloy semiconductor includes silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenide phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and/or aluminum gallium arsenide, etc. In some embodiments, the first substrate 100 may also be a silicon-on-insulator structure, a silicon-germanium-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

Referring to fig. 2, a conductive layer 101 is formed on a first substrate 100.

In some embodiments, the material of conductive layer 101 comprises tungsten.

In some embodiments, referring to fig. 3, providing the first substrate 100 includes: providing a first substrate 110; forming a buffer layer 120 on the first substrate 110; and forming the conductive layer 101 on the first substrate 100 includes: the conductive layer 101 is formed on the buffer layer 120. In this way, the buffer layer 120 can be used to transition between the conductive layer 101 and the first substrate 110, so as to avoid diffusion between the elements in the conductive layer 101 and the first substrate 110, and improve the stability of the semiconductor structure.

In some embodiments, the material of the first substrate 110 may be a semiconductor material, such as, but not limited to, silicon. In some embodiments, the first substrate 110 may comprise a silicon substrate (e.g., a wafer). In some embodiments, the first substrate 110 may include: a base semiconductor, a compound semiconductor, or an alloy semiconductor. For example, the base semiconductor includes germanium (Ge); the compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, and/or a group III-V semiconductor material, etc.; the alloy semiconductor includes silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenide phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and/or aluminum gallium arsenide, etc.

In some embodiments, the material of the buffer layer 120 includes silicon oxide, silicon nitride, silicon oxynitride, or the like.

Referring to fig. 4, a filling layer 102 is formed on a conductive layer 101; a capacitor hole 103 penetrating the filler layer 102 is formed in the filler layer 102, and the capacitor hole 103 exposes a part of the surface of the conductive layer 101.

In fig. 4, a direction perpendicular to the surface of the first substrate 100, in which the direction of the capacitor hole 103 penetrating the filling layer 102 is taken as an example, that is, an angle between the extending direction of the capacitor hole 103 and the surface of the first substrate 100 is 90 °, and the extending direction of the capacitor hole 103 is not limited. In some embodiments, the extending direction of the capacitor hole may form an angle of 30 °, 60 °, 45 ° or the like with the surface of the first substrate.

In some embodiments, referring to fig. 5, the number of the capacitor holes 103 formed in the filling layer 102 is plural, and the plural capacitor holes 103 may be arranged in the filling layer 102 in an array along a first direction X and a second direction Y, where the first direction X and the second direction Y are parallel to the surface of the first substrate 100, so as to improve the arrangement density of the capacitor holes 103, thereby being beneficial to forming plural closely arranged capacitor structures subsequently and improving the space utilization of the semiconductor structure.

In fig. 5, an included angle between the first direction X and the second direction Y is 90 ° for example, so that the subsequently formed capacitor structures may be in a square compact arrangement. In some embodiments, the first direction and the second direction may be 60 ° so that the subsequently formed capacitor structures are closely arranged in a hexagonal shape. The capacitor structure closely arranged in the square or hexagonal mode can be beneficial to improving the space utilization of the capacitor structure, and further is beneficial to improving the integration density of the semiconductor structure.

In fig. 5, the cross section of the capacitor hole 103 is described as a circle, and the capacitor structure formed by this is a cylinder, and the shape of the capacitor hole 103 is not limited. In some embodiments, the cross-section of the capacitive aperture 103 may also be rectangular, square, triangular, or the like. It will be appreciated that the cylindrical capacitor structure may have a smooth surface to avoid the phenomenon of tip discharge, and when the capacitor hole is rectangular, square or triangular, the tip may be chamfered to smooth the surface of the subsequently formed capacitor structure.

In some embodiments, the thickness of the filling layer 102 is 1 μm or more in a direction perpendicular to the surface of the first substrate 100, for example, the thickness of the filling layer 102 may be 1 μm, 1.5 μm, 2 μm, 3 μm, or the like. It can be understood that the thickness of the filling layer 102 determines the depth of the capacitor hole 103, that is, the length of the capacitor structure along the direction perpendicular to the surface of the first substrate 100 corresponds to the longer the thickness of the filling layer 102, which is more beneficial to forming the capacitor structure with a larger aspect ratio and improving the charge storage capability of the capacitor structure.

In some embodiments, the material of the fill layer 102 includes at least one of doped polysilicon, silicon germanium, tungsten, platinum nickel, titanium, tantalum, cobalt, tantalum nitride, titanium nitride, and ruthenium. In this way, the filling layer 102 has better conductivity, so as to be beneficial to reducing the resistance of the capacitor structure formed later and improving the electrical transmission performance of the capacitor structure and other devices.

In some embodiments, forming the capacitor hole 103 in the fill layer 102 through the fill layer 102 includes: the fill layer is patterned to form a capacitor hole 103, wherein the conductive layer 101 acts as an etch stop layer when forming the capacitor hole 103. In this way, the surface of the conductive layer 101 contacted by the poor topography of the capacitor hole 103 or excessive etching caused by long-term exposure of the filling layer 102 to the etching environment can be prevented from being damaged.

In some embodiments, referring to fig. 6, the material of conductive layer 101 may be the same as the material of filler layer 102. Thus, the formation of the conductive layer 101 on the first substrate 100 and the formation of the filling layer 102 on the conductive layer 101 may be formed in the same process step to improve the manufacturing efficiency of the semiconductor structure.

Referring to fig. 7, a second electrode layer 133, a dielectric layer 123, and a first electrode layer 113 are formed in the capacitor hole 103, which are sequentially stacked, the second electrode layer 133 covering the bottom surface and the side wall of the capacitor hole 103 and the surface of the filling layer 102; the dielectric layer 123 covers the surface of the second electrode layer 133; the first electrode layer 113 covers the surface of the dielectric layer 123 and fills the capacitor hole 103, and the first electrode layer 113, the dielectric layer 123 and the second electrode layer 133 constitute a capacitor structure 203.

In some embodiments, the resistance value of the material of the filling layer 102 is less than or equal to the resistance value of the material of the second electrode layer 133. The second electrode layers 133 of the plurality of capacitor structures 203 can be electrically connected to each other through the filling layer 102, and meanwhile, the resistance of the plurality of capacitor structures 203 is reduced, so that the electrical transmission efficiency of the capacitor structures 203 and other devices is improved.

In some embodiments, referring to fig. 8, the material of the filler layer 102 is the same as the material of the second electrode layer 133, such that the filler layer 102 is used as the second electrode layer 133; forming the capacitor structure 203 includes: forming a dielectric layer 123 and a first electrode layer 113 stacked in this order in the capacitor hole 103, the dielectric layer 123 covering the inner wall (including the bottom surface and the side wall) of the capacitor hole 103 and the surface of the filler layer 102; the first electrode layer 113 covers the surface of the dielectric layer 123 and fills the capacitor hole 103, and the first electrode layer 113, the dielectric layer 123 and the filling layer 102 constitute a capacitor structure. In this way, the filling layer 102 and the second electrode layer 133 may be formed in the same process step or the manufacturing process steps of the second electrode layer 133 may be reduced, so as to improve the manufacturing efficiency of the semiconductor structure.

In some embodiments, the material of the conductive layer 101 includes a metal material capable of bonding with the material of the second electrode layer 133. In this way, good ohmic contact can be provided between the conductive layer 101 and the second electrode layer 133, so that the contact resistance between the conductive layer 101 and the second electrode layer 133 is prevented from being too large, and the usability of the semiconductor structure is improved.

In some embodiments, the materials of the first electrode layer 113 and the second electrode layer 133 each include at least one of platinum nickel, titanium, tantalum, cobalt, polysilicon, copper, tungsten, tantalum nitride, titanium nitride, or ruthenium.

In some embodiments, the material of the dielectric layer 123 includes a high dielectric constant material such as silicon oxide, tantalum oxide, hafnium oxide, zirconium oxide, niobium oxide, titanium oxide, barium oxide, strontium oxide, yttrium oxide, lanthanum oxide, praseodymium oxide, or barium strontium titanate. A high dielectric constant material is advantageous for improving the charge storage capability of the capacitor structure.

In some embodiments, the material of the filling layer 102 is silicon germanium, the material of the conductive layer 101 is tungsten, and the material of the first electrode layer 113 and the second electrode layer 133 is titanium nitride.

Referring to fig. 9, a second substrate 200 is provided, and a surface of the second substrate 200 has a contact structure 201, and a position of the contact structure 201 corresponds to a position of the first electrode layer 113. Referring to fig. 10, the first substrate 100 is aligned with the second substrate 200 such that the first electrode layer 113 is aligned with and contacts the contact structure 201, and the first substrate 100 and the second substrate 200 are bonded. Referring to fig. 11, the first substrate 100 is removed. In this way, in the capacitor structure 203 remaining on the second substrate 200, the first electrode layer 113 in contact with the contact structure 201 serves as a lower electrode layer of the capacitor structure 203, the dielectric layer 123 serves as a capacitor dielectric layer of the capacitor structure 203, and the second electrode layer 133 serves as an upper electrode layer of the capacitor structure 203.

In some embodiments, the second substrate 200 may include: a base semiconductor, a compound semiconductor, or an alloy semiconductor. For example, the base semiconductor includes silicon, germanium (Ge); the compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, and/or a group III-V semiconductor material, etc.; the alloy semiconductor includes silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenide phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and/or aluminum gallium arsenide, etc. In some embodiments, the second substrate 200 may also be a silicon-on-insulator structure, a silicon-germanium-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

In some embodiments, the material of the contact structure 201 includes copper, silver, gold, tungsten, tin, lead, or the like.

In some embodiments, the second base includes a second substrate on which the transistor, the word line, and the bit line are disposed, the gate of the transistor is electrically connected to the word line, one of the source or the drain of the transistor is electrically connected to the bit line, and the other of the source or the drain of the transistor is electrically connected to the contact structure. Thus, the transistor can be electrically connected with the corresponding capacitor structure through the contact structure, the transistor and the corresponding capacitor structure form a memory cell, and the corresponding word line and bit line can realize the storage or reading of the memory cell.

In some embodiments, the material of the second substrate may be a semiconductor material, such as, but not limited to, silicon. In some embodiments, the second substrate may comprise a crystalline silicon substrate (e.g., a wafer). In some embodiments, the second substrate may include: a base semiconductor, a compound semiconductor, or an alloy semiconductor. For example, the base semiconductor includes germanium (Ge); the compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, indium antimonide, and/or a group III-V semiconductor material, etc.; the alloy semiconductor includes silicon germanium (SiGe), silicon germanium carbide, germanium tin, silicon germanium tin, gallium arsenide phosphide, gallium indium arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and/or aluminum gallium arsenide, etc. In some embodiments, the second substrate may also be a silicon-on-insulator structure, a silicon-germanium-on-insulator structure, a germanium-on-insulator structure, or a combination thereof.

In some embodiments, the material of the word line includes at least one of polysilicon, titanium nitride, titanium aluminide, tantalum nitride, nickel silicide, cobalt silicide, tantalum, aluminum, lanthanum, titanium, or tungsten.

In some embodiments, the material of the bit line includes at least one of metal silicide, titanium nitride, or tungsten. In some embodiments, the material forming the bit lines may be a single metal, a metal compound, or an alloy. Wherein the single metal can be aluminum, tungsten, gold or silver; the metal compound may be tungsten nitride, tantalum nitride or titanium nitride; the alloy may be an alloy material composed of at least 2 of aluminum, tungsten, gold, or silver.

In some embodiments, after forming the capacitive structure, before bonding the first substrate 100 and the second substrate 200, further comprising: a surface of the first electrode layer 113, which is far from the first substrate 100, is planarized such that a top surface of the first electrode layer 113 is flush with a top surface of the dielectric layer 123. By planarizing the top surface of the first electrode layer 113 to be flush with the top surface of the dielectric layer 123, the subsequent bonding of the first substrate 100 to the second substrate 200 may be facilitated, and poor contact between the contact structure 201 and the first electrode layer 113 may be avoided. And by performing planarization treatment on the surface of the first electrode layer 113 away from the first substrate 100, the top surface of the dielectric layer 123 is exposed, so that after the subsequent bonding with the second substrate, the dielectric layer 123 contacts with the surface of the second substrate 200 between the adjacent contact structures 201, and the different capacitor structures 203 can be insulated from each other, so as to avoid electric leakage between the adjacent capacitor structures 203.

In some embodiments, the process conditions for bonding the first substrate 100 and the second substrate 200 include: the bonding temperature is 20-25 ℃, and the bonding time is more than or equal to 5 seconds. For example, the bonding temperature may be 20 ℃, 22 ℃, 24.5 ℃, 25 ℃, or the like; the bonding time may be 5 seconds, 8 seconds, 10 seconds, or the like.

In some embodiments, the first substrate 100 and the second substrate 200 are bonded further including an annealing process, the process conditions of which include: the annealing time is 3 to 8 minutes, the annealing temperature is 250 to 350 ℃, and better ohmic contact between the first electrode layer 113 and the contact structure 201 can be achieved through the annealing process.

In some embodiments, the annealing time may be 3 minutes, 4 minutes, 5 minutes, 6.5 minutes, 8 minutes, or the like; the annealing temperature may be 250 ℃, 275 ℃, 290 ℃, 314 ℃, 328 ℃, or 350 ℃.

According to the manufacturing method of the semiconductor structure provided by the embodiment of the disclosure, the conductive layer 101 and the filling layer 102 are formed on the first substrate 100, the capacitor hole 103 is formed in the filling layer 102, and then the capacitor hole 103 is filled to form the capacitor structure 203, so that the filling layer 102 can be fully filled between the capacitor structures 203, and the capacitor hole 103 in the filling layer 102 can have a higher depth-to-width ratio as a whole, and then the capacitor structure 203 formed after the capacitor hole 103 is filled subsequently can also have a larger depth-to-width ratio, so that the capacitor structure 203 can have a higher charge storage capacity. In addition, by forming the capacitor structure 203 on the first substrate 100, and then bonding the first substrate 100 (e.g., the process of forming the capacitor structure on the first substrate) with the second substrate 200 (e.g., the process of forming the front-end on the second substrate, including the process of forming the transistor, forming the word line, forming the bit line, forming the capacitor contact structure, forming the landing pad, etc.), the structures on the first substrate 100 and the second substrate 200 can be fabricated simultaneously, and then a complete memory cell can be formed by bonding, so that the process can be simplified significantly and the manufacturing efficiency of the semiconductor structure can be improved.

Compared with the mode of firstly forming a plurality of independent capacitor structures and then filling gaps between the capacitor structures with a filling layer, the mode of firstly forming the capacitor structures on the first substrate and then bonding the capacitor structures with the second substrate provided by the embodiment of the disclosure can avoid the problem that gaps are generated between the capacitor structures due to too high formation rate of the filling layer, so that the performance of the semiconductor structure is improved. In addition, compared with the method of forming a plurality of independent capacitor structures, in the embodiment of the disclosure, the capacitor holes are formed in the filling layer, and the filling layer is taken as a whole, so that the capacitor structure has higher supporting strength, and the problem of collapse caused by overlarge depth-to-width ratio of the capacitor structure can be effectively avoided.

According to some embodiments of the present disclosure, another embodiment of the present disclosure provides a semiconductor structure that may be formed using the method for manufacturing a semiconductor structure described above to improve the performance of the semiconductor structure. It should be noted that, in the same or corresponding parts as those of the above embodiments, reference may be made to the corresponding descriptions of the above embodiments, and detailed descriptions thereof will be omitted.

The following will describe the semiconductor structure provided in this embodiment in detail with reference to the accompanying drawings, and specifically includes:

referring to fig. 11, a semiconductor structure includes: a second substrate 200, the surface of the second substrate 200 having a contact structure 201; the capacitor structure 203 disposed on the second substrate, where the capacitor structure 203 includes a first electrode layer 113, a dielectric layer 123, and a second electrode layer 133 that are sequentially stacked, the first electrode layer 113 extends along a thickness direction of the second substrate 200, and a bottom surface of the first electrode layer 113 contacts a top surface of the contact structure 201; the dielectric layer 123 covers the surface of the first electrode layer 113 and the surface of the second substrate 200 between the first electrode layers 113; the second electrode layer 133 covers the surface of the dielectric layer 123; a filling layer 102, the filling layer 102 filling gaps between adjacent capacitance structures 203; and a conductive layer 101, the conductive layer 101 covering the top surface of the filling layer 102 and the top surface of the second electrode layer 133.

The semiconductor structure provided in the embodiments of the present disclosure is formed by using the manufacturing method of the semiconductor structure, the filling layer 102 may be fully filled between the capacitor structures 203, and the filling layer 102 may be used as a supporting structure between the capacitor structures 203, so that the capacitor structures 203 have a larger aspect ratio and have sufficient strength, and collapse of the capacitor structures 203 is avoided.

In some embodiments, the resistance value of the material of conductive layer 101 is less than the resistance value of the material of filler layer 102. It can be understood that, the filling layer 102 is configured to communicate the second electrode layers 133 of the plurality of capacitor structures 203 with each other, even though the upper electrode layers of the plurality of capacitor structures 203 share the same control terminal, the conductive layer 101 may electrically connect the plurality of capacitor structures 203 with the metal wiring layer in the subsequent process, so that the capacitor structures 203 can perform signal transmission with other devices, and a resistance value of the material of the conductive layer 101 is smaller than that of the material of the filling layer 102, which is beneficial to reduce a contact resistance between the capacitor structures 203 and other devices and improve a signal transmission efficiency.

It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples of implementing the disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure.

Claims

1. A method of fabricating a semiconductor structure, comprising:

providing a first substrate;

forming a conductive layer on the first substrate;

forming a filling layer on the conductive layer;

forming a capacitor hole penetrating through the filling layer in the filling layer, wherein part of the surface of the conductive layer is exposed by the capacitor hole;

forming a second electrode layer, a dielectric layer and a first electrode layer which are sequentially stacked in the capacitor hole, wherein the second electrode layer covers the inner wall of the capacitor hole and the surface of the filling layer; the dielectric layer covers the surface of the second electrode layer; the first electrode layer covers the surface of the dielectric layer and fills the capacitor hole, and the first electrode layer, the dielectric layer and the second electrode layer form a capacitor structure;

providing a second substrate, wherein the surface of the second substrate is provided with a contact structure, and the position of the contact structure corresponds to the position of the first electrode layer;

the first substrate is opposite to the second substrate, so that the first electrode layer is opposite to and contacted with the contact structure, and the first substrate and the second substrate are bonded;

and removing the first substrate.

2. The method of manufacturing a semiconductor structure of claim 1, wherein providing a first substrate comprises: providing a first substrate;

forming a buffer layer on the first substrate; and

forming a conductive layer on the first substrate includes: the conductive layer is formed on the buffer layer.

3. The method of manufacturing a semiconductor structure of claim 2, wherein forming a capacitor hole in the fill layer through the fill layer comprises:

patterning the filling layer to form the capacitor hole, wherein the conductive layer is used as an etching stop layer when the capacitor hole is formed.

4. The method of claim 1, wherein the material of the filling layer comprises at least one of doped polysilicon, silicon germanium, tungsten, platinum nickel, titanium, tantalum, cobalt, tantalum nitride, titanium nitride, and ruthenium; and/or

The material of the conductive layer includes a metal material capable of bonding with the material of the second electrode layer.

5. The method for manufacturing a semiconductor structure according to claim 1, wherein a material of the filling layer is the same as a material of the second electrode layer, so that the filling layer is used as the second electrode layer;

forming the capacitor structure includes:

forming the dielectric layer and the first electrode layer which are sequentially stacked in the capacitor hole, wherein the dielectric layer covers the inner wall of the capacitor hole and the surface of the filling layer; the first electrode layer covers the surface of the dielectric layer and fills the capacitor hole, and the first electrode layer, the dielectric layer and the filling layer form a capacitor structure.

6. The method of manufacturing a semiconductor structure according to any one of claims 1 to 5, further comprising, after forming the capacitor structure, before bonding the first substrate and the second substrate: and carrying out planarization treatment on the surface of one side of the first electrode layer away from the first substrate so that the top surface of the first electrode layer is flush with the top surface of the dielectric layer.

7. The method of manufacturing a semiconductor structure according to any one of claims 1 to 5, wherein after bonding the first substrate and the second substrate, further comprising an annealing treatment, the process conditions of the annealing treatment comprising: the annealing time is 3-8 minutes, and the annealing temperature is 250-350 ℃.

8. The method of manufacturing a semiconductor structure according to any one of claims 1 to 5, wherein the second base includes a second substrate on which a transistor, a word line, and a bit line are provided, a gate of the transistor is electrically connected to the word line, one of a source or a drain of the transistor is electrically connected to the bit line, and the other of the source or the drain of the transistor is electrically connected to the contact structure.

9. A semiconductor structure, comprising:

a second substrate, the surface of which is provided with a contact structure;

the capacitor structure is arranged on the second substrate and comprises a first electrode layer, a dielectric layer and a second electrode layer which are sequentially stacked, wherein the first electrode layer extends along the thickness direction of the second substrate, and the bottom surface of the first electrode layer is in contact with the top surface of the contact structure; the dielectric layer covers the surface of the first electrode layer and the surface of the second substrate between the first electrode layers; the second electrode layer covers the surface of the dielectric layer;

a filling layer filling a gap between adjacent capacitor structures;

and the conductive layer covers the top surface of the filling layer and the top surface of the second electrode layer.

10. The semiconductor structure of claim 9, wherein the material of the fill layer comprises at least one of doped polysilicon, silicon germanium, tungsten, platinum nickel, titanium, tantalum, cobalt, tantalum nitride, titanium nitride, and ruthenium; and/or