CN116344508B - Semiconductor structure, forming method thereof and chip - Google Patents
Semiconductor structure, forming method thereof and chip Download PDFInfo
- Publication number
- CN116344508B CN116344508B CN202310588580.XA CN202310588580A CN116344508B CN 116344508 B CN116344508 B CN 116344508B CN 202310588580 A CN202310588580 A CN 202310588580A CN 116344508 B CN116344508 B CN 116344508B
- Authority
- CN
- China
- Prior art keywords
- layer
- metal
- metal layer
- interconnect
- interconnection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The embodiment of the disclosure discloses a semiconductor structure, a forming method thereof and a chip. The semiconductor structure comprises: a first interconnect layer comprising a first metal interconnect structure; a second interconnect layer stacked on the first interconnect layer, comprising: at least one first contact structure and one second metal interconnection structure which are arranged along a first direction, wherein the first direction is vertical to the stacking direction of the first interconnection layer and the second interconnection layer; a third interconnect layer stacked on the second interconnect layer, including at least one bond pad; the bonding pad is connected with the first contact structure and is not connected with the second metal interconnection structure; the first metal interconnect structures are of the same material as the first contact structures and each comprise a first conductive material, and the second metal interconnect structures are of a material comprising a second conductive material having a resistivity greater than the resistivity of the first conductive material.
Description
Technical Field
Embodiments of the present disclosure relate to the field of memory devices, and, but not limited to, a semiconductor structure, a method of forming the same, and a chip.
Background
With the development of integrated circuit technology, the chip integration level of very large scale integrated circuits has been as high as several hundred million to several billion devices. In order to achieve complete system functionality, integrated circuit design and fabrication requires metal interconnection of many semiconductor devices in an integrated circuit in a back-end process.
How to optimize the metal interconnection structure and improve the electrical performance of the metal interconnection structure becomes a problem to be solved.
Disclosure of Invention
In view of the above, embodiments of the present disclosure provide a semiconductor structure, a method for forming the same, and a chip.
In a first aspect, embodiments of the present disclosure provide a semiconductor structure, comprising:
a first interconnect layer comprising a first metal interconnect structure;
a second interconnect layer stacked on the first interconnect layer, comprising: at least one first contact structure and a second metal interconnection structure arranged along a first direction, wherein the first direction is perpendicular to the stacking direction of the first interconnection layer and the second interconnection layer;
a third interconnect layer stacked on the second interconnect layer, including at least one bond pad;
the first metal interconnection structure is connected with the first contact structure and the second metal interconnection structure, and the bonding pad is connected with the first contact structure and not connected with the second metal interconnection structure; the first metal interconnection structure is made of the same material as the first contact structure and comprises a first conductive material, and the second metal interconnection structure is made of a second conductive material with resistivity greater than that of the first conductive material.
In some embodiments, the first metal interconnect structure comprises a first metal layer and the second metal interconnect structure comprises a second metal layer, a second contact structure; the second contact structure is located between the first metal layer and the second metal layer and is connected with both the first metal layer and the second metal layer.
In some embodiments, the first metal layer includes a first portion, a second portion, and a first portion arranged along the first direction; the first portion and the second portion both extend in a second direction; the second direction is perpendicular to the first direction and the stacking direction of the first interconnect layer and the second interconnect layer;
the first contact structure is connected with the first part, and the second contact structure is connected with the second part;
the first metal interconnection structure further comprises a third metal layer and a plurality of third contact structures positioned on the third metal layer; the third metal layer extends along the first direction, and the first portion and the second portion are connected with the third metal layer through the third contact structure.
In some embodiments, the first metal layer extends along the first direction, and the first contact structure and the second contact structure are both connected to the first metal layer.
In some embodiments, the first metal interconnect structure further comprises a third metal layer, a plurality of third contact structures located on the third metal layer; the third metal layer comprises a third part, a fourth part and a third part which are arranged along the first direction, wherein the third part and the fourth part extend along the second direction, and the third part and the fourth part are connected with the first metal layer through the third contact structure; the second direction is perpendicular to both the first direction and a stacking direction of the first interconnect layer and the second interconnect layer.
In some embodiments, the first metal interconnect structure further comprises a third metal layer, a plurality of third contact structures located on the third metal layer; the third metal layer extends along the first direction, the second metal layer is connected with the third metal layer through the third contact structure, and the first contact structure extends into the first interconnection layer to be connected with the third metal layer.
In some embodiments, the third interconnect layer further comprises a virtual bond pad; the dummy bond pad is not connected to both the first contact structure and the second metal interconnect structure.
In some embodiments, the first conductive material comprises copper and the second conductive material comprises aluminum.
In a second aspect, embodiments of the present disclosure further include a chip including a plurality of the semiconductor structures according to any of the embodiments above, wherein a plurality of the semiconductor structures are bonded through the bond pads.
In a third aspect, embodiments of the present disclosure further include a method of forming a semiconductor structure, the method including:
forming a first interconnection layer, wherein the first interconnection layer comprises a first metal interconnection structure;
forming a second interconnection layer on the first interconnection layer, wherein the second interconnection layer comprises at least one first contact structure and a second metal interconnection structure which are arranged along a first direction, the first metal interconnection structure is connected with the first contact structure and the second metal interconnection structure, and the first direction is perpendicular to the stacking direction of the first interconnection layer and the second interconnection layer; the material of the first metal interconnection structure is the same as the material of the first contact structure and comprises a first conductive material, and the material of the second metal interconnection structure comprises a second conductive material, wherein the resistivity of the second conductive material is larger than that of the first conductive material;
Forming a third interconnect layer on the second interconnect layer, the third interconnect layer including at least one bond pad; the bond pad is connected with the first contact structure and disconnected with the second metal interconnect structure.
In some embodiments, the forming the first interconnect layer includes: forming a first metal layer;
the forming a second interconnect layer includes:
forming a second contact structure on the first metal layer;
forming a second metal layer on the second contact structure; the second contact structure is connected with both the first metal layer and the second metal layer.
In some embodiments, the forming a first metal layer includes:
forming a first portion, a second portion, and a first portion arranged along the first direction; the first portion and the second portion both extend in a second direction; the second direction is perpendicular to the first direction and the stacking direction of the first interconnect layer and the second interconnect layer; the first contact structure is connected with the first portion, and the second contact structure is connected with the second portion.
In some embodiments, the forming the first interconnect layer further comprises: forming a third metal layer before forming the first metal layer; forming a plurality of third contact structures on the third metal layer; the third metal layer extends along the first direction, and the first portion and the second portion are connected with the third metal layer through the third contact structure.
In some embodiments, the forming a first metal layer includes:
a first metal layer extending along the first direction is formed, and the first contact structure and the second contact structure are connected with the first metal layer.
In some embodiments, the forming the first interconnect layer further comprises:
forming a third metal layer before forming the first metal layer; the third metal layer comprises a third part, a fourth part and a third part which are arranged along the first direction, wherein the third part and the fourth part extend along a second direction, and the second direction is perpendicular to the first direction and the stacking direction of the first interconnection layer and the second interconnection layer.
Forming a plurality of third contact structures on the third metal layer; the third portion and the fourth portion are both connected to the first metal layer through the third contact structure.
In some embodiments, the forming the first interconnect layer further comprises:
forming a third metal layer before forming the first metal layer, the third metal layer extending along the first direction;
and forming a plurality of third contact structures on the third metal layer, wherein the second metal layer is connected with the third metal layer through the third contact structures, and the first contact structures extend into the first interconnection layer to be connected with the third metal layer.
In some embodiments, the forming the third interconnect layer includes: forming a virtual bonding pad; the dummy pad is not connected to both the first contact structure and the second metal interconnect structure.
In the embodiment of the disclosure, the material of the first contact structure and the material of the first metal interconnection structure are both first conductive materials, the material of the second metal interconnection structure is second conductive material, and the resistivity of the second conductive material is larger than that of the first conductive material, the first contact structure is connected with the first metal interconnection structure and is not connected with the second metal interconnection structure, so that after the two semiconductor structures are bonded through the bonding pad, data transmission between the two semiconductor structures can not pass through the second metal interconnection structure, and the second metal interconnection structure is specially used for wafer test (CP) test, on one hand, the data transmission speed between the two semiconductor structures is not affected due to the selection of the material of the second metal interconnection structure, so that the material of the second metal interconnection structure suitable for performing CP test can be selected according to the requirement of CP test, and the CP test has higher accuracy; on the other hand, since the data transmission speed between the two semiconductor structures is related to the first metal interconnection structure and the first contact structure, and since the materials of the first metal interconnection structure and the first contact structure are the same and the resistivity of the materials of the first metal interconnection structure and the first contact structure is smaller than that of the materials of the second metal interconnection structure, the overall resistance of the first contact structure and the first metal interconnection structure is smaller and the contact resistance between the first contact structure and the first metal interconnection structure is smaller, thereby enabling to increase the data transmission speed; in still another aspect, since the first metal interconnection structure is connected with the first contact structure, and the first metal interconnection structure is made of the same material as the first contact structure, the problem of ion migration caused by the difference of materials of contact interfaces can be improved, and thus the reliability and the service life of a product can be improved.
Drawings
FIG. 1 is a schematic diagram of a semiconductor structure in some embodiments;
FIG. 2 is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a second semiconductor structure provided in an embodiment of the disclosure;
FIG. 4 is a schematic diagram III of a semiconductor structure provided in an embodiment of the present disclosure;
FIG. 5A is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;
FIG. 5B is a schematic top view of the first metal layer and the third metal layer according to the embodiments of the present disclosure;
fig. 6 is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;
fig. 7 is a schematic diagram of a semiconductor structure provided in an embodiment of the present disclosure;
fig. 8 is a schematic diagram seven of a semiconductor structure provided in an embodiment of the present disclosure;
FIG. 9 is a schematic top view of bond pads and virtual bond pads provided in an embodiment of the present disclosure;
fig. 10 is a schematic view eight of a semiconductor structure provided in an embodiment of the present disclosure;
FIG. 11 is a flow chart of a method for forming a semiconductor structure according to an embodiment of the disclosure;
fig. 12a is a schematic diagram of a process for forming a semiconductor structure provided in an embodiment of the disclosure;
fig. 12b is a schematic diagram of a second process for forming a semiconductor structure provided in an embodiment of the disclosure;
Fig. 12c is a schematic diagram three of a process for forming a semiconductor structure provided in an embodiment of the present disclosure;
fig. 12d is a schematic diagram of a process for forming a semiconductor structure provided in an embodiment of the present disclosure;
fig. 12e is a schematic diagram of a process for forming a semiconductor structure provided in an embodiment of the present disclosure;
fig. 12f is a schematic diagram of a process for forming a semiconductor structure provided in an embodiment of the disclosure.
Reference numerals illustrate:
10-lower interconnect level; 20-an intermediate interconnect layer; 30-an upper interconnect level; 21-a metal layer; 22-lower contact structure; 23-upper contact structure; 32-a first bond pad; 100-a first interconnect layer; 200-a second interconnect layer; 201-a first contact structure; 210-a second metal interconnect structure; 300-a third interconnect layer; 301-bonding pads; 110-a first metal interconnect structure; 210-a second metal interconnect structure; 202-a second metal layer; 203-a second contact structure; 101-a first metal layer; 403-a first adhesion layer; 404-a second adhesion layer; 303-air gap; 304-a barrier layer; 101 a-a first part; 101 b-a second part; 102-a third metal layer; 103-a third contact structure; 102 a-a third portion; 102 b-fourth part; 131-a first dielectric layer; 132-a second dielectric layer; 133-a third dielectric layer; 134-a fourth dielectric layer; 135-a fifth dielectric layer; 136-a sixth dielectric layer; 310-etching the barrier layer; 310 a-a first blocking portion; 310 b-a second blocking portion; 401-a first photoresist layer; 402-a first opening; 405-a first trench; 330 a diffusion barrier; 137-seventh dielectric layer; 340-a second photoresist layer; 408-a second trench; 1000-semiconductor structure.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In the semiconductor field, wafer testing is an essential link, CP testing is between Wafer fabrication and packaging throughout the chip fabrication process, and the test object is for each Die (Die) in Wafer, in order to ensure that each Die in Wafer can substantially meet the device characteristics or design specifications, typically including verification of voltage, current, timing and function. The specific operation of the CP test is to connect the Die pins exposed to the outside with a test machine through probes after the wafer is fabricated.
The embodiment of the present disclosure provides a semiconductor structure, as shown in fig. 1, including a lower interconnect layer 10, a middle interconnect layer 20 stacked on the lower interconnect layer 10, and an upper interconnect layer 30 stacked on the middle interconnect layer 20. The intermediate interconnect layer 20 includes a metal layer 21 extending in the X-direction, a plurality of lower contact structures 22 arranged in the X-direction below the metal layer 21, and a plurality of upper contact structures 23 arranged in the X-direction above the metal layer 21. The lower contact structure 22 connects the metal layer 21 and the lower interconnect layer 10. The upper contact structure 23 connects the metal layer 21 and the first bond pad 32 in the upper interconnect layer 30.
In the process of semiconductor structure, in order to make data have relatively high transmission speed, a material with relatively low resistivity, such as copper Cu, is generally selected as an interconnection line in the interconnection structure, but copper is easy to deform, and if copper is used as a metal layer for CP test, poor contact or inaccurate test during CP test is easy to cause. The semiconductor structure shown in fig. 1 is mainly used for the metal layer 21 to be in contact with a probe in the CP test, and in order to avoid the problems of poor contact or inaccurate test caused in the CP test, the lower contact structure 22 and the metal layer 21 in the semiconductor structure shown in fig. 1 are generally made of aluminum Al (or at least the metal layer 21 is made of Al) which is not easily deformed. After the CP test is completed, an upper contact structure 23 connected to the metal layer 21 is formed on the metal layer 21, and a first bonding pad 32 connected to the upper contact structure 23 is formed on the upper contact structure 23, and then the two Wafer sheets may be bonded by using the first bonding pad 32, so as to realize a function of increasing the memory capacity. The upper contact structure 23 and the first bond pad 32 are typically made of a material having a relatively low resistivity, such as copper.
However, on the one hand, since the resistivity of aluminum is relatively high, the total resistance of the metal layer 21 and the lower contact structure 22 is relatively high, and the two wafers are interconnected, the signal needs to pass through the metal layer 21 and the lower contact structure 22, and the relatively high resistance causes the problem of relatively low data transmission speed when data is performed between the two wafers interconnected; on the other hand, as the materials of the metal layer 21 and the upper contact structure 23 are different, the interface materials of the upper contact structure 23 and the metal layer 21 are different after being electrified, so that ion migration can be caused, and the reliability and the service life of the chip are reduced; on the other hand, the interface material between the upper contact structure 23 and the metal layer 21 is cu—al, so that the contact resistance is high, which also results in a low data transmission speed.
To solve the above-mentioned problem, an embodiment of the present disclosure provides a semiconductor structure 1000, as shown in fig. 2, including:
in the embodiment of the present disclosure, the first direction is taken as the X direction, the second direction is taken as the Y direction, and the stacking direction of the first interconnect layer 100 and the second interconnect layer 200 is taken as the Z direction as an example.
A first interconnect layer 100 including a first metal interconnect structure 110;
a second interconnect layer 200 stacked on the first interconnect layer 100, comprising: at least one first contact structure 201, a second metal interconnection structure 210 arranged along a first direction, the first direction being perpendicular to a stacking direction of the first interconnection layer 100 and the second interconnection layer 200;
A third interconnect layer 300 stacked on the second interconnect layer 200, including at least one bond pad 301;
wherein the first metal interconnection structure 110 is connected to the first contact structure 201 and the second metal interconnection structure 210, and the bond pad 301 is connected to the first contact structure 201 and not connected to the second metal interconnection structure 210; the material of the first metal interconnect structure 110 is the same as the material of the first contact structure 201 and each includes a first conductive material, and the material of the second metal interconnect structure 210 includes a second conductive material having a resistivity greater than the resistivity of the first conductive material.
In the embodiment of the disclosure, the material of the first contact structure 201 and the material of the first metal interconnection structure 110 are both the first conductive material, the material of the second metal interconnection structure 210 is the second conductive material, and the resistivity of the second conductive material is greater than that of the first conductive material, the first contact structure 201 is connected with the first metal interconnection structure 110 and is not connected with the second metal interconnection structure 210, so that after the two semiconductor structures 1000 are bonded through the bonding pad 301, data transmission between the two semiconductor structures 1000 may not pass through the second metal interconnection structure 210, so that the second metal interconnection structure 210 is dedicated to CP testing, on one hand, since the selection of the material of the second metal interconnection structure 210 does not affect the data transmission speed between the two semiconductor structures 1000, so that the material of the second metal interconnection structure 210 suitable for CP testing can be selected according to the requirements of CP testing, so that the CP testing has higher accuracy; on the other hand, since the data transmission speed between the two semiconductor structures 1000 is related to the first metal interconnection structure 110 and the first contact structure 201, and since the materials of the first metal interconnection structure 110 and the first contact structure 201 are the same and the resistivity of the materials of the first metal interconnection structure 110 and the first contact structure 201 is smaller than the resistivity of the materials of the second metal interconnection structure 210, the overall resistance of the first contact structure 201 and the first metal interconnection structure 110 is smaller and the contact resistance between the first contact structure 201 and the first metal interconnection structure 110 is smaller, thereby enabling to increase the data transmission speed; in still another aspect, since the first metal interconnection structure 110 is connected with the first contact structure 201, and the first metal interconnection structure 110 is made of the same material as the first contact structure 201, it is possible to improve the problem of ion migration due to the difference in material of the contact interface, and thus it is possible to improve the reliability and the service life of the product.
In some embodiments, under the first interconnect layer 100, the semiconductor structure 1000 may further include at least one interconnect layer and/or at least one memory cell for storage and/or MOS transistors required for peripheral circuits.
In some embodiments, the first conductive material may include copper and the second conductive material may include aluminum.
It should be noted that the first conductive material and the second conductive material given in the above embodiments are only exemplary, and are not intended to limit the first conductive material and the second conductive material in the embodiments of the present disclosure.
In some embodiments, the first conductive material may further include a copper alloy and a silver alloy. In some embodiments, the bond pad may use a third conductive material. The third conductive material may be the same as or different from the first conductive material, and in some embodiments, both the third conductive material and the first conductive material may be copper.
The present disclosure provides a plurality of embodiments for a specific structure of a first metal interconnection structure and a specific connection relationship between the first metal interconnection structure and a first contact structure, which will be specifically described below with reference to the accompanying drawings.
The first metal interconnect structure 110 in the semiconductor structure 1000 of the embodiments of the present disclosure may include only one metal layer, and may also include multiple metal layers. The semiconductor structure in the case where the first metal interconnection structure 110 includes only one metal layer will be described in detail.
In some embodiments, as shown in fig. 3, the first metal interconnect structure 110 includes a first metal layer 101, and the second metal interconnect structure 210 includes a second metal layer 202, a second contact structure 203; the second contact structure 203 is located between the first metal layer 101 and the second metal layer 202 and is connected to both the first metal layer 101 and the second metal layer 202.
It should be noted that, connection in the embodiments of the present disclosure refers to direct contact connection, and indirect connection is not realized through other components.
Here, the second metal layer 202 is connected to the first metal layer 101 by means of a second contact structure 203.
In some embodiments, as shown in fig. 3, the first metal layer 101 extends along a first direction, and both the first contact structure 201 and the second contact structure 203 are connected to the first metal layer 101.
Here, the size of the first metal layer 101 in the first direction is larger than the size of the second metal layer 202 in the first direction, so that the first metal layer 101 has a portion protruding with respect to the second metal layer 202 in the first direction, so that the first contact structure 201 can be directly connected with the first metal layer 101 without being connected with the second metal layer 202.
As shown in fig. 3, the first metal layer 101 may include one complete whole extending in the first direction. A plurality of first contact structures 201 and a plurality of second contact structures 203 are respectively led out at different regions on the first metal layer 101. The first contact structure 201 may be directly connected to the bonding pad 301 for data transmission channels between different wafers. The second contact structure 203 is connected to the second metal layer 202 and is commonly used for performing CP testing.
In some embodiments, as shown in fig. 3, an adhesion layer is further provided between the second metal layer 202 and the dielectric layer in contact therewith, the adhesion layer being used to increase the adhesion between the second metal layer 202 and the dielectric layer material. The adhesion layer includes a second adhesion layer 404 covering at least a portion of the upper surface of the second metal layer 202 and a first adhesion layer 403 covering at least a portion of the lower surface of the second metal layer 202.
In some embodiments, an Air Gap 303 (Air Gap) is also present in the dielectric layer, which may be used to reduce parasitic capacitance in the semiconductor structure 1000.
In some embodiments, as shown in fig. 3, a barrier layer 304 is further included between each metal layer, each contact structure, and the corresponding dielectric layer, where the barrier layer 304 is configured to block diffusion of metal into the dielectric layer.
In some embodiments, as shown in fig. 4, the first metal layer 101 includes a first portion 101a, a second portion 101b, and a first portion 101a arranged along a first direction; the first portion 101a and the second portion 101b each extend in a second direction; the second direction and the first direction are both perpendicular to the stacking direction of the first interconnect layer 100 and the second interconnect layer 200;
the first contact structure 201 is connected to the first portion 101a and the second contact structure 203 is connected to the second portion 101 b.
In the disclosed embodiment, the first metal layer 101 may include a plurality of portions. For example, a plurality of first portions 101a and second portions 101b are included, and the plurality of first portions 101a may be disposed on both sides of the second portions 101a in the X direction. The first portion 101a has a portion protruding from the second metal layer 202 in the first direction, so that the first contact structure 201 can be directly connected to the first portion 101a of the first metal layer without being connected to the second metal layer 202.
In some embodiments, the number of first contact structures 201 connected on each first portion 101a is not limited to one as shown in fig. 4, the number of first contact structures 201 connected on each first portion 101a may also be plural, and each first contact structure 201 may be connected with one corresponding bonding pad 301.
The semiconductor structure 1000 in the case where the first metal interconnect structure 110 includes two metal layers will be described in further detail below.
In some embodiments, as shown in fig. 5A, the first metal interconnect structure 100 further includes a third metal layer 102, a plurality of third contact structures 103 located on the third metal layer 102; the third metal layer 102 extends in the first direction, and the first portion 101a and the second portion 101b are each connected to the third metal layer 102 by a third contact structure 103.
Since the first metal layer 101 may include a plurality of portions arranged in the X direction, at least one third contact structure 103 may be disposed under each portion, and a third metal layer 102 extending in the X direction may be disposed under the plurality of third contact structures 103, the third metal layer 102 may be a complete whole. Whereby both the first portion 101a and the second portion 101b are indirectly connected to the third metal layer 102.
Fig. 5B is a top view of the first metal layer 101 and the third metal layer 102. The first metal layer 101 is perpendicular to the extension direction of the third metal layer 102. Portions of the first metal layer 101 (e.g., the first portion 101a and the second portion 101 b) may each extend in the Y direction, and the third metal layer 102 may extend in the X direction.
In some embodiments, as shown in fig. 6, the first metal layer 101 extends along a first direction, and both the first contact structure 201 and the second contact structure 203 are connected to the first metal layer 101.
The first metal interconnect structure 110 further includes a third metal layer 102, a plurality of third contact structures 103 located on the third metal layer 102; the third metal layer 102 includes a third portion 102a, a fourth portion 102b, and a third portion 102a arranged along the first direction, wherein the third portion 102a and the fourth portion 102b each extend along the second direction, and the third portion 102a and the fourth portion 102b are connected to the first metal layer 101 through a third contact structure 103; the second direction and the first direction are perpendicular to the stacking direction of the first interconnection layer and the second interconnection layer.
In the embodiment of the present disclosure, the first contact structure 201 and the second contact structure 203 may be connected to the first metal layer 101, and then a plurality of third contact structures 103 are disposed under the first metal layer 101. The third contact structure 103 may connect the third portion 102a and the fourth portion 102b, and then may continue to connect with the underlying interconnect structure or device through the third portion 102a and the fourth portion 102 b.
In some embodiments, as shown in fig. 7, the first metal interconnect structure 110 further includes a third metal layer 102, a plurality of third contact structures 103 located on the third metal layer 102; the third metal layer 102 extends in the first direction, the first metal layer 101 is connected to the third metal layer 102 by a third contact structure 103, and the first contact structure 201 extends into the first interconnect layer 100 to be connected to the third metal layer 102.
In the disclosed embodiment, the first contact structure 201 may be directly connected to the third metal layer 102, i.e. the first contact structure 201 may extend into the first interconnect layer 100. The second metal interconnection structure 210 for CP testing is also connected with the third metal layer 102 through the first metal layer 101 and the plurality of third contact structures 103, so that the second metal interconnection structure 210 can be used for CP testing, and a channel for performing data transmission with an external device does not pass through the second metal interconnection structure 210, thereby not only meeting the requirements of CP testing, but also ensuring that data has a higher transmission speed.
In some embodiments, as shown in fig. 8, the third interconnect layer 300 further includes a virtual bond Pad (Dummy Pad) 302; the dummy bond pads are not connected to both the first contact structure 201 and the second metal interconnect structure 210.
In the embodiment of the present disclosure, the dummy bond pad 302 may also be disposed in the third interconnect layer 300, and the dummy bond pad 302 may be disposed in a region of the third interconnect layer of the semiconductor structure 1000 where the bond pad 301 is not formed, so that on one hand, the bonding area of the semiconductor structure may be increased, and thus the bonding strength may be increased; on the other hand, the dummy bonding pads 302 may be disposed around the bonding pads 301 as shown in fig. 9, so that the bonding pads 301 may be protected, and the bonding pads 301 may be electromagnetically protected.
It should be noted that fig. 9 is a schematic top view of the virtual bonding pad 302 and the bonding pad 301. It should be understood that the arrangement of the dummy bond pads 302 and the bond pads 301 is not limited thereto.
In the embodiment of the disclosure, the plurality of first contact structures 201 are connected to the first metal interconnection structure 110, and each first contact structure 201 is connected to one bonding pad 301, so that a plurality of bonding pads 301 indirectly connected to the first contact structure 110 are disposed on the first metal interconnection structure 110, so that a dislocation problem caused by insufficient precision of the bonding pads 301 when bonding with other wafer can be prevented, and a protection effect on the second metal interconnection structure 210 can be also played.
Embodiments of the present disclosure also include a chip comprising a plurality of semiconductor structures 1000 as in any of the embodiments above, the plurality of semiconductor structures 1000 being bonded by bond pads.
In some embodiments, one semiconductor structure 1000 as shown in fig. 2 may be disposed on another semiconductor structure 1000 as shown in fig. 2, forming a structure as shown in fig. 10 for increasing storage capacity.
The two semiconductor structures can be processed separately, so that the processing time can be saved, and the mutual influence when simultaneously formed on one substrate can be reduced.
In some embodiments, the upper layer semiconductor structure 1000 in fig. 10 may include a MOS transistor for setting a peripheral circuit, and the lower layer semiconductor structure 1000 may include a memory cell for storage, without being limited thereto.
In some embodiments, the chip may include a plurality of 3D stacked semiconductor structures 1000 as depicted in fig. 10.
Based on the above semiconductor structure, the embodiment of the disclosure further provides a method for manufacturing a semiconductor structure, and fig. 11 is a schematic flow chart of the method for manufacturing a semiconductor structure according to the embodiment of the disclosure. As shown in fig. 11, a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure includes the following steps:
Step S101, forming a first interconnection layer, wherein the first interconnection layer comprises a first metal interconnection structure;
step S201, forming a second interconnection layer on the first interconnection layer, wherein the second interconnection layer comprises at least one first contact structure and a second metal interconnection structure which are arranged along a first direction, the first metal interconnection structure is connected with the first contact structure and the second metal interconnection structure, and the first direction is perpendicular to the stacking direction of the first interconnection layer and the second interconnection layer; the material of the first metal interconnection structure is the same as the material of the first contact structure and comprises a first conductive material, and the material of the second metal interconnection structure comprises a second conductive material, wherein the resistivity of the second conductive material is larger than that of the first conductive material;
step S301, forming a third interconnection layer on the second interconnection layer, wherein the third interconnection layer comprises at least one bonding pad; the bonding pad is connected with the first contact structure and is not connected with the second metal interconnection structure.
In the embodiment of the disclosure, the material of the first contact structure and the material of the first metal interconnection structure are both the first conductive material, the material of the second metal interconnection structure is the second conductive material, and the resistivity of the second conductive material is greater than that of the first conductive material, the first contact structure is connected with the first metal interconnection structure and is not connected with the second metal interconnection structure, so that after the two semiconductor structures are bonded through the bonding pad, data transmission between the two semiconductor structures can not pass through the second metal interconnection structure, and the second metal interconnection structure is special for CP test. On the other hand, since the data transmission speed between the two semiconductor structures is related to the first metal interconnection structure and the first contact structure, and since the materials of the first metal interconnection structure and the first contact structure are the same and the resistivity of the materials of the first metal interconnection structure and the first contact structure is smaller than that of the materials of the second metal interconnection structure, the overall resistance of the first contact structure and the first metal interconnection structure is smaller and the contact resistance between the first contact structure and the first metal interconnection structure is smaller, thereby enabling to increase the data transmission speed; in still another aspect, since the first metal interconnection structure is connected with the first contact structure, and the first metal interconnection structure is made of the same material as the first contact structure, the problem of ion migration caused by the difference of materials of contact interfaces can be improved, and thus the reliability and the service life of a product can be improved.
It should be understood that the steps shown in fig. 11 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations. The steps shown in fig. 11 can be sequentially adjusted according to actual needs.
In some embodiments, forming the first interconnect layer includes: forming a first metal layer;
forming a second interconnect layer comprising:
forming a second contact structure on the first metal layer;
forming a second metal layer on the second contact structure; the second contact structure is connected with both the first metal layer and the second metal layer.
In some embodiments, forming the first metal layer includes:
forming a first portion, a second portion, and a first portion arranged along a first direction; the first part and the second part extend along the second direction; the second direction is perpendicular to the first direction and the stacking direction of the first interconnection layer and the second interconnection layer; the first contact structure is connected with the first portion, and the second contact structure is connected with the second portion.
In some embodiments, forming the first interconnect layer further comprises: forming a third metal layer before forming the first metal layer; forming a plurality of third contact structures on the third metal layer; the third metal layer extends along the first direction, and the first part and the second part are connected with the third metal layer through a third contact structure.
In some embodiments, forming the first metal layer includes:
a first metal layer extending along a first direction is formed, and both the first contact structure and the second contact structure are connected with the first metal layer.
In some embodiments, forming the first interconnect layer further comprises:
forming a third metal layer before forming the first metal layer; the third metal layer comprises a third part, a fourth part and a third part which are arranged along the first direction, wherein the third part and the fourth part extend along the second direction, and the second direction is perpendicular to the first direction and the stacking direction of the first interconnection layer and the second interconnection layer.
Forming a plurality of third contact structures on the third metal layer; the third portion and the fourth portion are both connected to the first metal layer by a third contact structure.
In some embodiments, forming the first interconnect layer further comprises:
forming a third metal layer before forming the first metal layer, the third metal layer extending along the first direction;
a plurality of third contact structures are formed on the third metal layer, the second metal layer is connected with the third metal layer through the third contact structures, and the first contact structures extend into the first interconnection layer to be connected with the third metal layer.
In some embodiments, forming the third interconnect layer includes: forming a virtual bonding pad; the dummy pad is not connected to both the first contact structure and the second metal interconnect structure.
An exemplary description will be given below with reference to fig. 12a to 12 f.
As shown in fig. 12a, a first dielectric layer 131 may be deposited, and a third metal layer 102 is formed in the first dielectric layer 131, the third metal layer 102 extending in the X direction. Then, a second dielectric layer 132 is deposited, a plurality of third contact structures 103 connected with the third metal layer 102 are formed in the second dielectric layer 132, the third dielectric layer 133 is continuously deposited, a first metal layer 101 is formed in the third dielectric layer 133, the first metal layer 101 comprises a first portion 101a, a second portion 101b and a first portion 101a which are arranged along the X direction, and the first portion 101a and the second portion 101b extend along the Y direction. Continuing to deposit the fourth dielectric layer 134, a second contact structure 203 is formed in the fourth dielectric layer 134, the second contact structure 203 being connected to the second portion 101 b. Continuing to deposit the fifth dielectric layer 135, a second metal layer 202 is formed in the fifth dielectric layer 135.
In some specific examples, the methods of forming the first metal layer 101, the second metal layer 202, the third metal layer 103, the second contact structure 203, and the third contact structure 103 include, but are not limited to, a deposition process.
A sixth dielectric layer 136 is deposited over the second metal layer 202, an etch stop layer 310 is formed in the sixth dielectric layer 136, and an upper surface of the etch stop layer 310 is flush with an upper surface of the sixth dielectric layer 136. The etch stop layer 310 includes a first stop portion 310a and a second stop portion 310b. In some embodiments, the projections of the first blocking portion 310a and the second blocking portion 310b in the top view cover the partial projections of the second metal layer 202 in the top view. The etch stop layer 310 may be used as a stop layer in a subsequent etching process.
A layer of photoresist is deposited over the etch stop layer 310, the portions to be removed are aligned using a patterned reticle, and then exposed. The photoresist may be a negative photoresist, and then the photoresist corresponding to the mask pattern is removed to form a first photoresist layer 401 and a plurality of first openings 402 as shown in fig. 12 a.
Before and after forming the second metal layer 202, a first adhesion layer 403 and a second adhesion layer 404 may be formed on the upper and lower surfaces of the second metal layer 202, respectively.
In some embodiments, other layers such as semiconductor substrates, device layers, etc. may also be included under the first dielectric layer 131.
The semiconductor substrate may include an elemental semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.
The device layer may include MOS transistors required for at least one memory cell and/or peripheral circuitry for storage.
The portion of the semiconductor structure shown in fig. 12a not covered by the first photoresist layer 401 is etched down, i.e. along the plurality of first openings 402. And etching the etch stop layer 310 and the sixth dielectric layer 136, the fifth dielectric layer 135 and the fourth dielectric layer 134 in sequence to form a plurality of first trenches 405 penetrating the etch stop layer 310 and the sixth dielectric layer 136, the fifth dielectric layer 135 and the fourth dielectric layer 134 as shown in fig. 12b, the first trenches 405 exposing the upper surface of the first portion 101a of the first metal layer 101.
Next, a conductive material, e.g., copper and its alloys, silver and its alloys, etc., is deposited or sputtered in the first trench 405 shown in fig. 12b using a deposition process or a sputtering process. The conductive material above the upper surface of the etch stop layer 310 is then planarized to form a first contact structure 201 as shown in fig. 12 c. The first contact structure 201 is connected to the first portion 101 a.
Next, a seventh dielectric layer 137, a diffusion barrier layer 330 and a photoresist layer are sequentially formed on the upper surfaces of the etching barrier layer 310 and the first contact structure 201. The patterned mask is used to align the portions to be removed and then exposure is performed. The photoresist may be a negative photoresist and then the photoresist corresponding to the mask pattern is removed to form a second photoresist layer 340 and a plurality of second openings 407 as shown in fig. 12 d.
Next, the portion of the semiconductor structure not covered by the second photoresist layer 340, i.e. along the plurality of second openings 407, is etched as shown in fig. 12 d. And the diffusion barrier layer 330 and the seventh dielectric layer 137 are sequentially etched to form a plurality of second trenches 408 extending through the diffusion barrier layer 330 and the seventh dielectric layer 137 as shown in fig. 12 e. The second trench 408 exposes an upper surface of the first contact structure 201.
Next, a conductive material, such as copper and its alloys, silver and its alloys, etc., is deposited or sputtered in the second trench 408 shown in fig. 12e using a deposition process or sputtering process. The conductive material above the upper surface of the diffusion barrier 330 is then planarized to form bond pads 301 and dummy bond pads 302 as shown in fig. 12 f. Wherein the bonding pad 301 is connected to the first contact structure 201. The dummy bond pad 302 is not connected to the first contact structure 201.
After the two semiconductor structures are bonded by the bond pad 301, the diffusion barrier layer may be used to improve metal diffusion problems that occur due to misalignment of the two bond pads.
In the embodiment of the present disclosure, the material of the first metal layer 101 may be the same as the material of the first contact structure 201, and each include a first conductive material, which may be copper.
The material of the second metal layer 202 and the material of the second contact structure 203 may be a second conductive material, the resistivity of which is greater than the resistivity of the first conductive material, and the second conductive material may be aluminum.
The materials used for the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, the fifth dielectric layer, the sixth dielectric layer and the seventh dielectric layer in the embodiments of the present disclosure may be the same or different. Illustratively, the materials of the first dielectric layer, the second dielectric layer, the third dielectric layer, the fourth dielectric layer, the fifth dielectric layer, the sixth dielectric layer, and the seventh dielectric layer may be silicon oxide or silicon oxynitride.
The material of the etch stop layer and the material of the diffusion stop layer may be the same or different. By way of example, the material of the etch stop layer and the material of the diffusion barrier layer may both be silicon nitride.
In the above embodiments, the methods of forming the dielectric layers, the barrier layers, the contact structures, and the metal layers include, but are not limited to, physical vapor deposition (PVD, physical Vapor Deposition) processes, chemical vapor deposition (CVD, chemical Vapor Deposition) processes, atomic layer deposition (ALD, atomic Layer Deposition), and the like.
In the above embodiments, the planarization process includes, but is not limited to, chemical mechanical polishing (CMP, chemical Mechanical Polish).
It should be appreciated that reference throughout this specification to "some embodiments," "one embodiment," or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. It should be understood that, in various embodiments of the present disclosure, the sequence numbers of the foregoing processes do not mean the order of execution, and the order of execution of the processes should be determined by their functions and internal logic, and should not constitute any limitation on the implementation of the embodiments of the present disclosure. The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is merely an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think about the changes or substitutions within the technical scope of the present disclosure, and should be covered by the protection scope of the present disclosure.
Claims (10)
1. A semiconductor structure, comprising:
a first interconnect layer comprising a first metal interconnect structure;
a second interconnect layer stacked on the first interconnect layer, comprising: at least one first contact structure and a second metal interconnection structure arranged along a first direction, wherein the first direction is perpendicular to the stacking direction of the first interconnection layer and the second interconnection layer;
A third interconnect layer stacked on the second interconnect layer, including at least one bond pad;
the first metal interconnection structure is connected with the first contact structure and the second metal interconnection structure, and the bonding pad is connected with the first contact structure and not connected with the second metal interconnection structure; the first metal interconnection structure is made of the same material as the first contact structure and comprises a first conductive material, and the second metal interconnection structure is made of a second conductive material with resistivity greater than that of the first conductive material.
2. The semiconductor structure of claim 1, wherein the first metal interconnect structure comprises a first metal layer and the second metal interconnect structure comprises a second metal layer, a second contact structure; the second contact structure is located between the first metal layer and the second metal layer and is connected with both the first metal layer and the second metal layer.
3. The semiconductor structure of claim 2, wherein the first metal layer comprises a first portion, a second portion, and a first portion arranged along the first direction; the first portion and the second portion both extend in a second direction; the second direction is perpendicular to the first direction and the stacking direction of the first interconnect layer and the second interconnect layer;
The first contact structure is connected with the first portion, and the second contact structure is connected with the second portion.
4. The semiconductor structure of claim 3, wherein the first metal interconnect structure further comprises a third metal layer, a plurality of third contact structures located on the third metal layer; the third metal layer extends along the first direction, and the first portion and the second portion are connected with the third metal layer through the third contact structure.
5. The semiconductor structure of claim 2, wherein the first metal layer extends along the first direction, the first contact structure and the second contact structure each being connected to the first metal layer;
the first metal interconnection structure further comprises a third metal layer and a plurality of third contact structures positioned on the third metal layer; the third metal layer comprises a third part, a fourth part and a third part which are arranged along the first direction, wherein the third part and the fourth part extend along the second direction, and the third part and the fourth part are connected with the first metal layer through the third contact structure; the second direction is perpendicular to both the first direction and a stacking direction of the first interconnect layer and the second interconnect layer.
6. The semiconductor structure of claim 2, wherein the first metal interconnect structure further comprises a third metal layer, a plurality of third contact structures located on the third metal layer; the third metal layer extends along the first direction, the second metal layer is connected with the third metal layer through the third contact structure, and the first contact structure extends into the first interconnection layer to be connected with the third metal layer.
7. The semiconductor structure of claim 1, wherein the third interconnect layer further comprises a dummy bond pad; the dummy bond pad is not connected to both the first contact structure and the second metal interconnect structure.
8. The semiconductor structure of claim 1, wherein the first conductive material comprises copper and the second conductive material comprises aluminum.
9. A chip comprising a plurality of semiconductor structures according to any one of claims 1 to 8, wherein a plurality of the semiconductor structures are bonded by the bond pads.
10. A method of forming a semiconductor structure, the method comprising:
forming a first interconnection layer, wherein the first interconnection layer comprises a first metal interconnection structure;
Forming a second interconnection layer on the first interconnection layer, wherein the second interconnection layer comprises at least one first contact structure and a second metal interconnection structure which are arranged along a first direction, the first metal interconnection structure is connected with the first contact structure and the second metal interconnection structure, and the first direction is perpendicular to the stacking direction of the first interconnection layer and the second interconnection layer; the material of the first metal interconnection structure is the same as the material of the first contact structure and comprises a first conductive material, and the material of the second metal interconnection structure comprises a second conductive material, wherein the resistivity of the second conductive material is larger than that of the first conductive material;
forming a third interconnect layer on the second interconnect layer, the third interconnect layer including at least one bond pad; the bond pad is connected with the first contact structure and disconnected with the second metal interconnect structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310588580.XA CN116344508B (en) | 2023-05-24 | 2023-05-24 | Semiconductor structure, forming method thereof and chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310588580.XA CN116344508B (en) | 2023-05-24 | 2023-05-24 | Semiconductor structure, forming method thereof and chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN116344508A CN116344508A (en) | 2023-06-27 |
| CN116344508B true CN116344508B (en) | 2023-07-25 |
Family
ID=86879027
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202310588580.XA Active CN116344508B (en) | 2023-05-24 | 2023-05-24 | Semiconductor structure, forming method thereof and chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN116344508B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108987386A (en) * | 2017-05-30 | 2018-12-11 | 富士电机株式会社 | Semiconductor device |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6486499B1 (en) * | 1999-12-22 | 2002-11-26 | Lumileds Lighting U.S., Llc | III-nitride light-emitting device with increased light generating capability |
| US8343809B2 (en) * | 2010-03-15 | 2013-01-01 | Stats Chippac, Ltd. | Semiconductor device and method of forming repassivation layer with reduced opening to contact pad of semiconductor die |
| US20230029867A1 (en) * | 2021-07-30 | 2023-02-02 | Taiwan Semiconductor Manufacturing Company Limited | Conductive structures with bottom-less barriers and liners |
-
2023
- 2023-05-24 CN CN202310588580.XA patent/CN116344508B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108987386A (en) * | 2017-05-30 | 2018-12-11 | 富士电机株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN116344508A (en) | 2023-06-27 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Das et al. | Technology, performance, and computer-aided design of three-dimensional integrated circuits | |
| CN109148415B (en) | Multi-wafer stack structure and method for forming the same | |
| US8933540B2 (en) | Thermal via for 3D integrated circuits structures | |
| US7897431B2 (en) | Stacked semiconductor device and method | |
| JP4979320B2 (en) | Semiconductor wafer, manufacturing method thereof, and manufacturing method of semiconductor device | |
| US8470705B2 (en) | Chip pad resistant to antenna effect and method | |
| US20010045670A1 (en) | Semiconductor device | |
| CN109390305B (en) | Bonding wafer and preparation method thereof | |
| US10784163B2 (en) | Multi-wafer stacking structure and fabrication method thereof | |
| KR20150076098A (en) | Semiconductor deivices and methods of manufacture thereof | |
| US10224276B2 (en) | Integrated circuit including wire structure, related method and design structure | |
| CN111244057B (en) | Bonding structure and manufacturing method thereof | |
| US7943482B2 (en) | Method for semiconductor device having radiation hardened insulators and design structure thereof | |
| CN116344508B (en) | Semiconductor structure, forming method thereof and chip | |
| KR20220100480A (en) | Backside or frontside through substrate via (tsv) landing on metal | |
| CN109166820B (en) | Semiconductor device manufacturing method and semiconductor device | |
| US20090189299A1 (en) | Method of forming a probe pad layout/design, and related device | |
| EP3180802B1 (en) | Semiconductor structure with multiple active layers in an soi wafer | |
| CN108054137B (en) | Metal interconnection structure and manufacturing method thereof | |
| CN112201573B (en) | Multi-layer wafer bonding method | |
| CN112968011B (en) | Semiconductor device and method for manufacturing the same | |
| JPH0845935A (en) | Forming method of multilayer interconnection | |
| US9059111B2 (en) | Reliable back-side-metal structure | |
| US20230223380A1 (en) | Bonded wafer device structure and methods for making the same | |
| US20220344278A1 (en) | Scribe structure for memory device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |