CN116343860A

CN116343860A - Memory device detecting weakness of operation mode and operation method thereof

Info

Publication number: CN116343860A
Application number: CN202211519323.2A
Authority: CN
Inventors: 柳廷旻
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2021-12-02
Filing date: 2022-11-30
Publication date: 2023-06-27
Also published as: US20230178136A1

Abstract

A memory device for detecting a vulnerability of an operation mode and an operation method thereof are provided. The method comprises the following steps: storing address information and activation count information about N word lines among the plurality of word lines in a register including N entries; storing address information and activation count information about a first word line in an entry from which information is evicted among N entries based on activation of the first word line different from the N word lines; and generating first vulnerability information based on a number of times an eviction is performed on the register in the first cycle.

Description

Memory device detecting weakness of operation mode and operation method thereof

Cross Reference to Related Applications

The present application claims priority from korean patent application No.10-2021-0171202 filed on 12 months 2 in 2021 and korean patent application No.10-2022-0052229 filed on 27 months 4 in 2022, the disclosures of which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates to a memory device and an operating method thereof, and more particularly, to a memory device detecting a weakness of an operation mode and an operating method thereof.

Background

The integration and speed of memory devices used in high performance electronic systems are both increasing. In a memory device such as a Dynamic Random Access Memory (DRAM), when an access frequency of a specific memory cell increases, memory cells adjacent to the specific memory cell may be stressed. As a result, the data retention characteristics of the adjacent memory cells are affected, and thus the data reliability is deteriorated. For example, when a specific word line is densely activated, data retention characteristics of memory cells connected to one or more word lines adjacent to the specific word line may be deteriorated, and thus, a target refresh may be performed on one or more word lines adjacent to the specific word line to ensure data reliability. The memory device may include means for counting the number of activations with respect to the plurality of word lines to control a target refresh execution.

However, when a nursing operation such as nursing refresh is performed only by counting the number of activation times of the word line, the nursing operation is actually performed without determining the possibility of data loss in detail, and thus the resource utilization efficiency of the memory device may be deteriorated. For example, the case where the number of activation times of a specific word line is increased may occur not only in a normal memory operation but also by a malicious attack from the outside. In this regard, care operations that do not determine the mode of operation of the memory device in detail may waste resources of the memory device.

Disclosure of Invention

One or more embodiments provide a memory device capable of detecting a vulnerability of the memory device based on a detailed operation mode of the memory device and an operation method thereof.

According to an aspect of an embodiment, there is provided a method of operating a memory device including a plurality of word lines and a register including N entries (N is an integer equal to or greater than 2). The method comprises the following steps: storing address information and activation count information about N word lines among the plurality of word lines in a register; based on activation of a first word line different from the N word lines, storing address information and activation count information about the first word line in an entry from which information is evicted among the N entries; and generating first vulnerability information based on a number of times an eviction is performed on the register in the first cycle.

According to an aspect of an embodiment, a memory device includes: a memory cell array including a plurality of word lines; a refresh controller configured to control refresh operations on a plurality of word lines; a control logic circuit configured to store address information and activation count information about N word lines of a plurality of word lines in a register including N entries (N is an integer equal to or greater than 2), to evict information stored in at least one of the N entries based on activation of a first word line different from the N word lines, and to store address information and activation count information about the first word line in the at least one entry; and vulnerability detection circuitry configured to generate first vulnerability information based on a number of times an eviction is performed on the register in the first cycle.

According to an aspect of an embodiment, a memory device includes: a memory cell array including a plurality of word lines; a refresh controller configured to control refresh operations on a plurality of word lines; a control logic circuit configured to store address information and activation count information in a register including N entries (N is an integer equal to or greater than 2), and generate eviction information based on evictions performed on the register; and vulnerability detection circuitry configured to generate first vulnerability information corresponding to a first cycle and second vulnerability information corresponding to a second cycle that is longer than the first cycle based on the eviction information. The vulnerability detection circuit includes: a first current state counter configured to generate and store eviction count information indicating the number of evictions in a current first cycle; and a first previous state register configured to store eviction count information corresponding to a previous first cycle. The vulnerability detection circuitry is further configured to generate first vulnerability information based on a comparison between the eviction count information corresponding to the current first cycle and the eviction count information corresponding to the previous first cycle.

Drawings

The above and other aspects and features will become more apparent from the following description of embodiments taken in conjunction with the accompanying drawings in which:

FIG. 1 is a block diagram illustrating a memory system according to an embodiment;

fig. 2 is a diagram showing an example of determining a weak word line based on the number of activations with respect to the word line according to an embodiment;

FIG. 3 is a block diagram illustrating Target Row Refresh (TRR) logic, according to an embodiment;

FIG. 4 is a block diagram illustrating the weak point detector of FIG. 1 according to an embodiment;

FIG. 5 is a block diagram illustrating a memory device according to an embodiment;

FIG. 6 is a block diagram illustrating the level table shown in FIG. 5 according to an embodiment;

FIGS. 7 and 8 are flowcharts of methods of operating a memory system according to embodiments;

FIGS. 9 and 10 are block diagrams of memory systems illustrating examples of exploitation of vulnerability information;

FIG. 11 is a block diagram showing an example of operation of an eviction counter circuit according to an embodiment;

FIG. 12 is a block diagram illustrating a memory device performing vulnerability detection according to an embodiment;

FIG. 13 is a block diagram illustrating a memory device according to another embodiment;

fig. 14 is a block diagram showing an example of setting a cycle mode in a memory device; and

FIG. 15 is a block diagram illustrating a data center including a memory system according to an embodiment.

Detailed Description

Embodiments will now be described more fully with reference to the accompanying drawings. The embodiments described herein are provided as examples, and thus, the present disclosure is not limited thereto, and may be implemented in various other forms. The embodiments provided in the following description do not preclude association with one or more features of another example or embodiment also provided herein or not provided herein but consistent with the present disclosure. It will be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. When appearing after a column of elements, expressions such as "at least one of" modify the entire column of elements without modifying individual elements in the column. For example, the expression "at least one of a, b and c" should be understood to include: only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b and c.

FIG. 1 is a block diagram illustrating a memory system according to an embodiment.

Referring to fig. 1, a memory system 10 may include a memory controller 100 and a memory device 200. The memory device 200 may include a memory cell array 210, a refresh controller 220, control logic (i.e., control circuitry) 230, and a weak point detector (i.e., weak point detection circuitry) 240. Additionally, according to an embodiment, control logic 230 may include Target Row Refresh (TRR) logic 231. In addition to TRR logic 231, control logic 230 may also include other components for controlling memory operations. In this regard, control logic 230 may include various types of components in memory device 200.

The memory controller 100 controls memory operations such as writing and reading by providing various signals to the memory device 200 via the interface circuit. For example, the memory controller 100 may provide a command CMD and an address ADD to the memory device 200 to access the DATA of the memory cell array 210. The command CMD may include commands for normal memory operations such as data writing and data reading. In addition, when the memory device 200 includes Dynamic Random Access Memory (DRAM) cells, the command CMD may include commands for various DRAM-related operations, such as a refresh command for refreshing the memory cells.

Memory controller 100 may access memory device 200 upon request from HOST. Memory controller 100 may communicate with HOST by utilizing various protocols. The memory cell array 210 may include a plurality of memory cells. For example, the memory cell array 210 may include a plurality of word lines, and a plurality of memory cells may be connected to each word line. For example, memory cells connected to one word line may be referred to as a row. In this regard, the memory cell array 210 may include a plurality of rows. Refresh word lines may refer to refreshing memory cells (or a row) connected to one word line, so expressions such as refresh word lines and refresh a row may be used interchangeably.

When any one of the word lines of the memory device 200 is densely or frequently activated (or accessed), memory cells adjacent to the word line that is densely or frequently activated (hereinafter, referred to as a 'weak word line') are subjected to electromagnetic interference. Specifically, as the integration level of the memory device 200 increases, the degree of interference received by the weak word lines may increase. Thus, the data of the memory cells connected to the weak word line is more likely to flip (flip). To ensure reliability of data prevention flip, a target refresh may be performed regularly or irregularly for a weak word line at a certain period.

In addition, in the memory cell array 210, a plurality of word lines may be arranged side by side, and two word lines adjacent to both sides of the word line that is densely accessed may correspond to weak word lines, respectively. Alternatively, according to an embodiment, since at least two word lines adjacent to one side of the densely accessed word line correspond to the weak word lines described above, three or more weak word lines related to the densely accessed word lines may be targeted for refresh.

In addition, the refresh controller 220 may refresh the word lines (or rows) of the memory cell array 210 in response to refresh commands from the memory controller 100. Alternatively, the refresh controller 220 may refresh the word lines of the memory cell array 210 in the self-refresh mode without intervention of the memory controller 100. In addition, according to an embodiment, when a particular word line is densely accessed, the refresh controller 220 may control a target refresh operation performed on one or more weak word lines adjacent to the densely accessed word line based on the control of the control logic 230.

According to an embodiment, the TRR logic 231 may perform logic operations for determining a weak word line to be refreshed. According to an embodiment, the TRR logic 231 may include a counter for counting the number of activation times of a plurality of word lines, determining a word line most frequently activated within a certain period based on a result of counting the number of activation times of the plurality of word lines, and determining a position of one or more weak word lines adjacent to the most frequently activated word line. In addition, address information regarding the determined weak word line may be provided to the refresh controller 220. However, embodiments are not limited thereto, and the components for determining the weak word line may be implemented differently in the memory device 200. For example, the components for determining the weak word line may be implemented outside of control logic 230.

The refresh controller 220 may include circuitry (e.g., an address counter) that generates a normal address that indicates a word line to be subjected to a normal refresh operation, and the refresh controller 220 may control the normal refresh operation and the target refresh operation based on the normal address and address information about the weak word line from the control logic 230. For example, the normal refresh operation and the target refresh operation may be selectively performed in response to a refresh command from the memory controller 100. For example, the refresh controller 220 may include a scheduler 221, and the scheduler 221 may schedule a normal refresh operation and a target refresh operation.

According to an embodiment, the TRR logic 231 may include a register that stores address information about word lines and activation count information about activation counts of the respective word lines in a table form. In addition, a counter circuit for counting activation of the word line may be provided outside the TRR logic 231 or inside the TRR logic 231, and activation count information based on a count result of the counter circuit may be stored in a register within the TRR logic 231.

The registers of the TRR logic 231 may include a plurality of entries, and each entry may store address information and activation count information for any one word line. In addition, the number of entries may be less than the number of word lines included in the memory cell array 210, and thus address information and activation count information about some of the word lines included in the memory cell array 210 may be stored in registers of the TRR logic 231. When another word line is activated after information is stored in all entries of the register, information in any one of the entries of the register may be evicted, and address information and activation count information about the newly activated word line may be stored in the corresponding entry. As used herein, eviction may refer to deleting information stored in an entry, and may be said to be an eviction of an entry or an eviction of information of an entry.

According to an embodiment, the TRR logic 231 may include a component that provides eviction information each time an eviction occurs in an entry. For example, the TRR logic 231 may include a counter circuit (hereinafter referred to as an eviction counter circuit) that provides a count value of 1 in response to an eviction of an entry. According to an embodiment, the TRR logic 231 may provide eviction information in various forms that may indicate the frequency of evictions of registers. For example, the TRR logic 231 may provide eviction information having a value of 1 each time any entry is evicted, or the TRR logic 231 may provide eviction information having a value of 2 or more when some entries are evicted according to the weight applied to the eviction characteristics. Alternatively, according to an embodiment, the TRR logic 231 may provide a value obtained by accumulating counts of eviction times of entries in a certain set period as the above-described eviction information. According to an embodiment, the nature of the eviction information that may be provided by the TRR logic 231 need not be limited to a particular form.

According to an embodiment, the weak point detector 240 may detect a weak point of the memory device 200 based on the eviction information from the control logic 230 or the TRR logic 231 and output weak point information info_tier [1:Z ] indicating the weak point. For example, when the word lines of memory device 200 are frequently activated, the frequency of eviction of an entry may increase. In this case, as the activation count information stored in the entry is lost, the possibility that the data of the weak word line that needs to be subjected to the target refresh is flipped may increase. In addition, the likelihood of data inversion may be relatively low when the word lines are frequently activated in normal operation of the memory device 200. However, when a word line is frequently activated and the eviction frequency of an entry increases due to a malicious external attack, the data retention characteristics of the weak word line may deteriorate, and thus, the data of the weak word line is likely to flip.

According to an embodiment, the weak point detector 240 may determine an operation state and/or an operation mode of the memory device 200 based on the eviction information from the TRR logic 231, may detect a weak point related to the data loss of the memory device 200 based on the operation state and/or the operation mode, and output the weak point information info_tier [1:Z ]. For example, vulnerabilities of memory device 200 may be categorized into a plurality of ranks according to the eviction frequency of an entry, and when the vulnerability of memory device 200 increases as the eviction frequency of an entry increases, the rank of vulnerability information info_tier [1:Z ] may increase.

According to an embodiment, information regarding the number of times an eviction is performed on an entry in a first cycle may be provided to the weak point detector 240 based on the count operation of the eviction counter circuit of the TRR logic 231 for a particular period (e.g., the first cycle). Alternatively, the TRR logic 231 may provide a value of 1 or more as eviction information to the weak point detector 240 each time an eviction is performed on an entry, and the weak point detector 240 may count the eviction information to determine the number of times an eviction is performed on an entry in the first cycle.

According to an embodiment, vulnerabilities of memory device 200 may be detected by comparing the number of evictions in a previous first cycle with the number of evictions in a current first cycle. For example, when the number of evictions in the current first cycle is greater than the number of evictions in the previous first cycle (or at least a particular threshold greater than the number of evictions in the previous first cycle), the weak point detector 240 may determine that the vulnerability of the memory device 200 increases, and thus the level of vulnerability information info_tier [1:Z ] may increase. On the other hand, when the number of evictions in the current first cycle is smaller than the number of evictions in the previous first cycle, the weak point detector 240 may determine that the weak point of the memory device 200 is reduced, and thus, the rank of the weak point information info_tier [1:Z ] may be reduced. In this regard, the vulnerability information Info tier [1:Z ] may be updated such that the level of the vulnerability information Info tier [1:Z ] increases or decreases over time.

According to an embodiment, a vulnerability of the memory device 200 may be detected for each of a plurality of time periods, and when Z time periods are defined, the vulnerability information info_tier [1:Z ] may include Z pieces of vulnerability information. For example, with the definition of Z slots, the number of evictions may be determined for each of the Z slots based on the count operations of the TRR logic 231 and/or the weak point detector 240, and the weak point detector 240 may generate vulnerability information info_tier [1:Z ] indicating vulnerabilities in the Z slots.

For example, a second period longer than the first period is defined, and when the second period corresponds to a period including a plurality of first periods, based on the counting operation of the weak point detector 240, the actual number of evictions of the entry in the second period may be determined by accumulating the count of the actual number of evictions in the plurality of first periods. Alternatively, according to embodiments, when the number of evictions of an entry in each first cycle is greater than a certain threshold, the weak point detector 240 may perform a count operation of 1, and thus, the accumulated count result corresponding to the value of 1 in the plurality of first cycles of the second cycle may be used as the number of evictions in the second cycle. According to an embodiment, the vulnerability of memory device 200 in the second cycle may also be detected by comparing the number of evictions in the previous second cycle with the number of evictions in the current second cycle.

Further, vulnerability information info_tier [1:Z ] may be used within the memory controller 100 and/or the memory device 200, and based on the vulnerability information info_tier [1:Z ], a care operation for improving data retention characteristics may be performed. For example, when the possibility of data loss is high due to the high weak point of the memory device 200, the frequency of performing the refresh operation may be increased by setting the period of the refresh operation to be short. In addition, control operations may be performed to selectively perform or selectively not perform targeted refresh operations based on vulnerabilities of the memory device 200. Alternatively, depending on the degree of weakness of the memory device 200, various care operations such as adjusting the frequency at which targeted refresh operations are performed may be performed.

In addition, since the degree of weakness in a relatively short period and the degree of weakness in a relatively long period can be detected, the care operation can be performed in consideration of the period in which the weakness is determined. For example, when the vulnerability of memory device 200 increases significantly over a relatively short period, a high frequency control operation may be performed to temporarily delay or skip memory operations (e.g., including active operations) to reduce entry eviction. In addition, when the weak point of the memory device 200 increases significantly in a relatively long period, a control operation for setting a short refresh period may be performed to improve the overall data retention characteristic for a long period of time.

Further, the memory device 200 may include a DRAM such as a double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate LPDD (LPDDR) SDRAM, graphics Double Data Rate (GDDR) SDRAM, rambus Dynamic Random Access Memory (RDRAM), or the like. However, the embodiment is not limited thereto. For example, the embodiments may be applied to a memory device that performs a data retention operation corresponding to a refresh operation, and the memory device includes a nonvolatile memory such as a Magnetic RAM (MRAM), a ferroelectric RAM (FeRAM), a phase change RAM (PRAM), and a resistive RAM (ReRAM).

Further, the memory device 200 may include one memory chip, or may include a semiconductor package having two or more memory chips. Alternatively, the memory device 200 may include a memory module in which a plurality of memory chips are mounted on a module board. Alternatively, although fig. 1 shows memory controller 100 and memory device 200 as separate components, memory device 200 may also be implemented as a memory system in which memory control functions and memory cell arrays are integrated in a single semiconductor package.

In addition, while determining the vulnerability of the memory device 200 based on the number of evictions of an entry has been described, embodiments are not limited thereto. According to embodiments, vulnerabilities may be determined by various methods based on activation of the word line. For example, the vulnerability may be determined by counting the total number of activations in a specific period or counting the number of activated word lines in a specific period, and the information for determining the vulnerability may also be defined as information about the activation frequency according to an embodiment.

Fig. 2 is a diagram showing an example of determining a weak word line based on the number of activations with respect to the word line. For example, counting the number of activations and determining the weak word line may be performed based on the operation of the TRR logic.

Referring to fig. 1 and 2, the memory cell array 210 includes a plurality of word lines WL1 to WLm, and based on the result of counting the activation of the plurality of word lines WL1 to WLm according to a specific period, the most frequently activated word line among the plurality of word lines WL1 to WLm may be determined. When the kth word line WLk is the most frequently activated word line, at least one word line adjacent to the kth word line WLk may be significantly affected by electromagnetic interference, and thus, the at least one word line adjacent to the kth word line WLk may correspond to a weak word line.

The weak word line may be located at both sides of the kth word line WLk. For example, at least one weak word line located at one side of the kth word line WLk may be referred to as a first weak word line WWL1, and at least one weak word line located at the other side may be referred to as a second weak word line WWL2. In addition, when the target refresh operation is performed, the target refresh operation may be performed on the first and second weak word lines WWL1 and WWL2 according to a specific set period.

According to an embodiment, because the number of entries of the register provided in the TRR logic 231 is smaller than the number of word lines WL1 to WLm, the address information on a part of the word lines of the plurality of word lines WL1 to WLm and the activation count information of the part of the word lines corresponding to the plurality of word lines WL1 to WLm may be stored in the entries. In addition, when another word line whose address information is not stored in an entry is newly activated, information stored in any one of the entries may be evicted, and address information and activation count information about the newly activated word line may be stored in the evicted entry. When the above-described eviction operation is performed a plurality of times, since the activation count information on at least some of the plurality of word lines WL1 to WLm is deleted from the register, the accuracy of the information including the activation count of the word line may be lowered, and thus, the reliability of the data may be deteriorated.

On the other hand, according to an embodiment, the eviction frequency of the information of the entry may be determined based on the operation of the TRR logic 231, and the vulnerability of the memory device 200 may be detected based on the determination of the frequency of eviction. Accordingly, the reliability of the data may also be improved by the care operations for the memory device 200, depending on the degree of the detected vulnerability.

Fig. 3 is a block diagram illustrating TRR logic according to an embodiment.

Referring to fig. 1 through 3, the trr logic 231 may include a register 231_1 and an eviction counter circuit 231_2, and the register 231_1 may include N entries. As discussed above with reference to fig. 2, the number of N entries may be smaller than the number of word lines WL1 to WLm (N < m), and address information and activation count information about the N word lines may be stored in the register 231_1. For example, when address information ADD 1 to ADD N about N word lines are stored, first to nth activation count information CV 1 to CV N corresponding to the N word lines may be stored in the register 231_1.

When the (n+1) -th word line is newly activated, information on the (n+1) -th word line is not stored in N entries of the register 231_1. Accordingly, information stored in any one of N entries of the register 231_1 may be evicted, and information about the (n+1) -th word line may be stored in the evicted entry. The information entry may be arbitrarily selected or may be selected for eviction therefrom based on a particular criteria (e.g., the entry in which information about the word line with the smallest activation count is stored). Fig. 3 shows a case in which information about the second word line is evicted. In this regard, address information ADD 2 about the second word line and second activation count information CV 2 corresponding thereto may be evicted from the entry, and address information ADD (n+1) about the (n+1) th word line and (n+1) th activation count information CV (n+1) corresponding thereto may be newly stored in the entry.

In addition, with the execution of evictions in the entry of the register 231_1, the eviction counter circuit 231_2 may output eviction information info_evic. In addition, as described above, the TRR logic 231 may output information (or weak word line information info_ww) about the most frequently activated word line in a specific period. According to an embodiment, weak word line information info_ww may be used to perform a targeted refresh operation, and eviction information info_evic may be used to detect vulnerabilities of memory device 200.

Fig. 4 is a block diagram illustrating the weak point detector of fig. 1 according to an embodiment.

Referring to fig. 1 through 4, the weak point detector 240 may detect the weak point of the memory device 200 based on the eviction information info_evic from the control logic 230 or the TRR logic 231, and output the weak point information info_tier according to the weak point. According to an embodiment, the weak point detector 240 may include a current state register 241, a previous state register 242, a weak point setter 243, and a weak point information generator 244. Because one or both of the current state register 241 and the previous state register 242 may perform a counting function, the current state register 241 and the previous state register 242 may be referred to as a current state counter and a previous state counter, respectively.

The weak point detector 240 may receive the eviction information info_evic output from the TRR logic 231 at a specific first period and provide the eviction information info_evic to the current status register 241. A value obtained by counting the number of evictions in the first period may be supplied from the TRR logic 231 to the current status register 241 as the eviction information info_evic. Alternatively, as the current state register 241 counts the number of evictions each time an entry is evicted in the first cycle, the number of evictions in the first cycle may be counted, and the number of evictions in the first cycle may be stored in the current state register 241. In addition, in the next first period, the weak point detector 240 may receive the eviction information info_evic again, and the eviction count information about the previous first period may be moved to the previous state register 242, and the eviction count information about the current first period may be stored in the current state register 241.

The vulnerability setter 243 may determine vulnerabilities based on information stored in the current status register 241 and the previous status register 242, and may perform vulnerability setting operations based on the determined vulnerabilities. For example, the vulnerability setter 243 may compare the number of evictions in the current first cycle with the number of evictions in the previous first cycle, and may determine that the vulnerability of the memory device 200 increases when the number of evictions in the current first cycle is greater than the number of evictions in the previous first cycle. Alternatively, the vulnerability setter 243 may determine that the vulnerability of the memory device 200 increases when the number of evictions in the current first cycle is equal to or greater than the number of evictions in the previous first cycle by at least a threshold.

The vulnerability information generator 244 may include table information including a plurality of levels according to the degrees of vulnerability, and any one of the plurality of levels may be output as vulnerability information info_tier based on the setting of the vulnerability setter 243. For example, when the vulnerability increases with the number of evictions in the current first cycle being greater than the number of evictions in the previous first cycle, the vulnerability information generator 244 may output vulnerability information info_tier in which the level increases by one level.

On the other hand, although the embodiment in which the degree of vulnerability is adjusted by comparing the number of evictions in the previous cycle with the number of evictions in the current cycle has been described above, the embodiment is not limited thereto. For example, by comparing the number of evictions periodically determined in each first cycle to a particular threshold, the weak point detector 240 may determine that the weak point has increased whenever the number of evictions is greater than the threshold.

Fig. 5 is a block diagram illustrating a memory device according to an embodiment. Fig. 5 shows TRR logic 310 and a weak point detector 320 provided in a memory device 300 according to an embodiment. In addition, in fig. 5, a short first period corresponding to a relatively short period and a long second period corresponding to a relatively long period are defined, and a case in which vulnerability information is generated in each of the short first period and the long second period.

Referring to fig. 5, the memory device 300 may include TRR logic 310 and a weak point detector 320, and the circuits constituting the TRR logic 310 and the weak point detector 320 may be arranged within the memory device 300 in various ways. For example, at least some of the components provided in the TRR logic 310 and the weak point detector 320 may be provided in the control logic described above.

TRR logic 310 may include a register 311 and an eviction counter circuit 312, and register 311 may include a number of entries. With the plurality of word lines of the memory device 300 activated, address information and activation count information regarding some of the plurality of word lines may be stored in entries of the register 311, and when a new word line is activated while all entries are used, eviction for deleting information stored in at least one entry of the register 311 may be performed. The eviction counter circuit 312 may output eviction information info_evic by performing a counting operation in response to an eviction performed on an entry of the register 311.

The weak point detector 320 may include a first weak point detector 321, a second weak point detector 322, and a buffer 323, and the first weak point detector 321 may include a first current state register 321_1, a first previous state register 321_2, a first weak point setter 321_3, and a first weak point information generator 321_4. Similarly, the second weak point detector 322 may include a second current state register 322_1, a second previous state register 322_2, a second weak point setter 322_3, and a second weak point information generator 322_4. According to an embodiment, since the first and second vulnerability setters 321_3 and 322_3 may each perform a comparison operation, it can be said that the first and second vulnerability setters 321_3 and 322_3 each include a comparator, and the first and second vulnerability information generators 321_4 and 322_4 each include a table in which a plurality of levels are stored.

The eviction information info_evic from the TRR logic 310 may be provided to the first current status register 321_1 via buffer 323. In addition, the eviction count information regarding the entries in the specific first cycle may be stored in the first current state register 321_1, the eviction count information in the previous first cycle may be moved into the first previous state register 321_2, and the eviction count information in the current first cycle may be updated in the first current state register 321_1.

According to an embodiment, the first vulnerability setter 321_3 may perform an operation of comparing the number of evictions in the previous first cycle with the number of evictions in the current first cycle, and may perform a setting operation for the first vulnerability information generator 321_4 based on the comparison result. For example, the first vulnerability information generator 321_4 may output any one selected from a plurality of levels as the first vulnerability information info_tier 1 based on the setting of the first vulnerability setter 321_3.

According to an embodiment, the weak point detector 320 may output first weak point information info_tier 1 indicating weak points in a relatively short first period and second weak point information info_tier 2 indicating weak points in a relatively long second period. According to an embodiment, the eviction count information may be provided to the second weak point detector 322 in each of a plurality of first cycles, and the second weak point detector 322 may determine an eviction characteristic of an entry of the register 311 in a second cycle corresponding to a time period including the plurality of first cycles. For example, the eviction count information stored in the first previous state register 321_2 in each of the plurality of first cycles may be provided to the second current state register 322_1.

According to an embodiment, with the accumulated count of the number of evictions in the plurality of first cycles, the second current status register 322_1 may store eviction count information corresponding to the actual number of evictions of the entry in the second cycle. Alternatively, the value obtained by count 1 may be accumulated in the second current state register 322_1 whenever the number of evictions of an entry in each of the first cycles is greater than a particular threshold. In this regard, the weak point detector 320 may determine whether the number of evictions of an entry in the second cycle is increased or decreased according to the result of the accumulated values obtained by the plurality of first cycle counts 1 in the second current state register 322_1.

In addition, information (hereinafter, referred to as eviction count information) stored in the second current status register 322_1 every second period may be moved to the second previous status register 322_2. The second weak point detector 322 may output the second weak point information Info _ t ier 2 in a similar manner to the first weak point detector 321 described above. For example, the second vulnerability setter 322_3 may perform an operation of comparing the number of evictions in the previous second cycle with the number of evictions in the current second cycle, and may perform a setting operation for the second vulnerability information generator 322_4 based on the comparison result. For example, the second vulnerability information generator 322_4 may output any one selected from a plurality of levels based on the setting of the second vulnerability setter 322_3 as the second vulnerability information info_tier2.

Fig. 6 is a block diagram illustrating the level table shown in fig. 5 according to an embodiment. According to an embodiment, the first vulnerability information generator 321_4 and the second vulnerability information generator 322_4 may be identically implemented, and the hierarchical table of fig. 6 may be an element provided in each of the first vulnerability information generator 321_4 and the second vulnerability information generator 322_4. As shown, the hierarchy Table (Tier Table) may include eight levels, tier1 through Tier 8. For example, tier1 may be the lowest level indicating the lowest vulnerability level and Tier 8 may be the highest level indicating the highest vulnerability level.

When the level table of fig. 6 is a constituent part provided in the first vulnerability information generator 321_4 of fig. 5, the level is increased or decreased and selected based on the setting of the first vulnerability setter 321_3, and the selected level may be output as the first vulnerability information info_tier 1. For example, the level may increase when the number of evictions in the current first cycle is greater than the number of evictions in the previous first cycle based on the information stored in the first current status register 321_1 and the first previous status register 321_2. Conversely, the level may decrease when the number of evictions in the current first cycle is less than the number of evictions in the previous first cycle.

Similarly, in the case of operating the second weak point detector 322, the level may increase when the number of evictions in the current second cycle is greater than the number of evictions in the previous second cycle based on the information stored in the second current state register 322_1 and the second previous state register 322_2. Conversely, the level may decrease when the number of evictions in the current second cycle is less than the number of evictions in the previous second cycle.

Various policies may be applied to increase or decrease the level, depending on the embodiment. For example, to prevent frequent changes in the level, the level may be increased or decreased only when the number of evictions in the current first cycle is greater or less than the number of evictions in the previous first cycle by at least some threshold. Furthermore, the determination of vulnerabilities corresponding to fairly high metrics (e.g., level 7 or higher) may be limited to situations where the number of evictions of the current first cycle increases rapidly. In this case, a criterion for determining to increase the level to the level 7 or higher may be set differently from other cases. For example, even when the number of evictions in the current first period is greater than the number of evictions in the previous first period, when the number of evictions in the current first period is not greater than the number of evictions in the previous first period by at least some threshold, it is possible to manage that the level does not increase to a level higher than 7.

Fig. 7 and 8 are flowcharts of methods of operating a memory system according to embodiments. The object that performs each of the operations shown in fig. 7 and 8 may be a memory device or a memory controller (or an application processor).

Referring to fig. 7, as various memory operations are performed on the memory device, an activation operation may be performed on a plurality of word lines (operation S11), and a counter circuit provided in the memory device may count the number of activations of the plurality of word lines. In addition, a register provided in the memory device may include a plurality of entries, and address information and activation count information regarding some of the plurality of word lines provided in the memory device may be stored in the entries.

One or more time periods may be defined for determining vulnerabilities of the memory device. For example, as the activation characteristics of the word lines are determined for each of the plurality of first periods, the activation characteristics of the word lines in the previous first period may be determined (operation S12), and the activation characteristics of the word lines in the current first period may be determined (operation S13). The activation characteristic may be a criterion that determines an operating mode or operating characteristic of the memory device, e.g., a total number of activations performed in the first cycle. Alternatively, the activation characteristic may be defined as the number of word lines on which at least one activation is performed in the first period, or the activation characteristic may be defined as information obtained by counting the number of evictions of a plurality of entries according to the above-described embodiment. Since the number of evictions of an entry may increase as the word line activation frequency increases, the activation characteristics will be described below as corresponding to the activation frequency.

It may be determined whether the activation frequency in the current first period is increased compared to the activation frequency in the previous first period (operation S14), and when the activation frequency is increased, vulnerability information in which the level of vulnerability is increased may be generated (operation S15). On the other hand, when the activation frequency is not increased, vulnerability information in which the level of vulnerability is maintained or reduced may be generated (operation S16). The generated or updated vulnerability information described above may be stored in a storage circuit within the memory device and the vulnerability information may be utilized within the memory device or used by an external device. For example, vulnerability information may be provided to an application processor including a memory controller (operation S17).

Referring to fig. 8, vulnerability information stored in a memory device may be used within the memory device or provided to a memory controller, and the memory device or the memory controller may check the level of vulnerability through the vulnerability information (operation S21). As a result of the checking, it may be determined whether the level of the vulnerability information is increased compared to the previous period (e.g., the relatively short first period or the relatively long second period) (operation S22).

When the level of the vulnerability increases, it may be determined whether the increase in the level corresponds to the increase in the level within a short period of time (first period) (operation S23). According to an embodiment, when the level of the vulnerability increases, a care operation corresponding to the level increase of the vulnerability may be performed, wherein the care operation performed in the case where the level of the vulnerability increases in the first period and the care operation performed in the case where the level of the vulnerability increases in the second period may be different. When the level increases in a short period of time, delay or skip can be applied to the memory operation so that the high activation frequency of the word line can be reduced (operation S24). On the other hand, when the rank increases over a long period of time, in order to ensure the reliability of the data of the memory device over a relatively long period of time, the refresh frequency may be increased by decreasing the refresh period or increasing the frequency at which the target refresh operation is performed (operation S25), thereby ensuring the reliability of the data.

Fig. 9 and 10 are block diagrams of memory systems illustrating examples of utilizing vulnerability information. Fig. 9 shows an example in which vulnerability information is provided from a memory device to a memory controller, and fig. 10 shows an example in which vulnerability information is used within a memory device.

Referring to fig. 9, a memory system 400 may include a memory controller 410 and a memory device 420, and the memory controller 410 may include a vulnerability information receiver 411 and a command generator 412. In addition, memory device 420 may include a memory cell array 421, a refresh controller 422, control logic 423, and a mode register 424. Additionally, memory device 420 may also include a weak point detector.

According to an embodiment, the memory controller 410 may be a component included in an application processor, and the application processor may be implemented as a system on a chip (SoC). The SoC may include a system bus to which a predetermined standard bus protocol is applied, and may include various Intellectual Property (IP) blocks connected to the system bus. For example, an IP block may include circuitry to perform a particular function and may have a design that includes a trade secret. As a standard protocol for the system bus, a protocol such as an Advanced Microcontroller Bus Architecture (AMBA) protocol of an Advanced RISC Machine (ARM) may be applied. The bus types of AMBA protocols may include advanced high-performance bus (AHB), advanced Peripheral Bus (APB), advanced extensible interface (AXI), AXI4, AXI Coherent Expansion (ACE), and the like. In addition, other types of protocols may be applied, such as the uNetwork of SONICs, the CoreConnect of IBM, and the Open Core protocol of OCP-IP.

Vulnerability information Info _ tier generated by the memory device 420 according to the above-described embodiments may be stored in the mode register 424. The command generator 412 of the memory controller 410 may output a mode register read command MRR for reading information stored in the mode register 424 to the memory device 420, and may receive vulnerability information Info tier in response to the mode register read command MRR. According to an embodiment, vulnerability information Info tier may be sent through a data channel between memory controller 410 and memory device 420.

The memory controller 410 may control the refresh period of the memory device 420 according to the level of vulnerability information Info _ t ier. For example, a plurality of refresh commands cmd_ref may be output from the memory controller 410 within one refresh cycle. When the refresh period is short, the refresh command reception period tREFI corresponding to the timing interval in which the memory device 420 receives the refresh command cmd_ref may be reduced. For example, the command generator 412 may output a refresh command cmd_ref in which the refresh command reception period tREFI varies according to the level of the vulnerability information info_tier.

Referring to fig. 10, a memory device 500 may include a memory cell array 510, a refresh controller 520, control logic 530, and a weak point detector 540, wherein the control logic 530 may include a target refresh controller 531, TRR logic 532, and delay/skip logic 533. The memory device 500 may receive a command CMD and/or an address ADD from the memory controller, and transfer DATA, where the command CMD may include a refresh command.

The weak point detector 540 may generate the weak point information Info _ tier according to the above-described embodiments, and the weak point information Info _ tier may be provided to the control logic 530. The control logic 530 may control various operations of the memory device 500 based on the vulnerability information Info tier. According to the above-described embodiment, the TRR logic 532 may determine the location of the weak word line based on the activation count for the word line pair, and the target refresh controller 531 may provide the target refresh control signal ctrl_tr including information about the target refresh, so that the refresh controller 520 performs the target refresh operation at a specific timing.

In addition, control logic 530 may control memory operations differently based on vulnerability information Info tier. For example, when the possibility of information loss regarding the activation count of a plurality of word lines increases due to frequent activation of the plurality of word lines, a control operation for reducing the activation frequency of the plurality of word lines may be performed. For example, the delay/skip logic 533 may include control circuitry to delay or skip activation of the word line in accordance with a memory operation request from the memory controller, and may provide an activation control signal ctrl_act to the memory cell array 510. For example, according to the activation control signal ctrl_act, the activation timing of the word lines included in the memory cell array 510 may be delayed, or some memory operations may not be performed due to skipping activation for the memory operations.

Fig. 11 is a block diagram showing an operation example of the eviction counter circuit according to the embodiment. Fig. 11 shows an example in which a weight is applied to the counted number of evictions.

Referring to fig. 11, memory device 600 may include a first register 610, a second register 620, and an eviction counter circuit 630. The first register 610 may store address information and activation count information regarding some of the plurality of word lines according to the above-described embodiments, and the eviction counter circuit 630 may perform an operation of outputting the eviction information according to evictions of the entries Entry1 to Entry K of the first register 610.

The second register 620 may include a plurality of entries Entry1 through Entry L and may store address information and/or activation count information about word lines evicted from the first register 610. According to an embodiment, the number of entries Entry1 through Entry L of the second register 620 may be equal to or less than the number of entries Entry1 through Entry K of the first register 610. In the entries Entry1 to Entry L of the second register 620, address information and/or activation count information about the word line evicted from the first register 610 may be stored in a first-in-first-out (FIFO) manner. In this regard, when information is stored in all of the entries Entry1 to Entry L of the second register 620 and additional information needs to be stored in the second register 620, an eviction may be performed on an Entry in which information is first stored in the entries Entry1 to Entry L of the second register 620.

According to an embodiment, as an Entry of the first register 610 (e.g., the second Entry 2) is evicted, the eviction counter circuit 630 may perform a counting operation. At this time, the eviction counter circuit 630 may determine whether information (e.g., address ADD 4 of the fourth word line) evicted from the second Entry2 of the first register 610 has been stored in the entries Entry 1 to Entry L of the second register 620, and when the address ADD 4 of the fourth word line evicted from the first register 610 matches the address information stored in the second register 620, the eviction counter circuit 630 may count a value greater than 1 (e.g., 2 or more).

In this regard, even though the address ADD 4 of the fourth word line has been previously evicted from the first register 610, as the fourth word line is activated again, the address ADD 4 of the fourth word line is stored in the first register 610 and is evicted from the first register 610 again later, the eviction counter circuit 630 may determine that the entry of the first register 610 is evicted very frequently. In this case, to increase the level of vulnerability of memory device 600, eviction counter circuit 630 may count a value greater than 1 by applying a weight to the count, and provide the count result as eviction information.

FIG. 12 is a block diagram illustrating a memory device performing vulnerability detection according to an embodiment. In fig. 12, an example of determining the number of evictions in the previous cycle and the number of evictions in the current cycle is shown. In addition, according to an embodiment, the components shown in fig. 12 may be applied to the weak point detector of the above-described embodiment.

The memory device 700 may include components for detecting vulnerabilities in a first period (short period), such as a first current state counter 710, a first previous state register 720, and a first vulnerability setter 730. In addition, the memory device 700 may also include components for detecting vulnerabilities in a second period (long period), such as a second current state counter 740, a second previous state register 750, and a second vulnerability setter 760.

The first current state counter 710 may receive the eviction information info_evic from the TRR logic every time an entry is evicted, and perform a counting operation based on the eviction information info_evic in a first cycle. For example, the eviction information info_evic may correspond to information having a value of 1 every time an eviction entry is performed, and the first current state counter 710 may perform a counting operation of accumulating the eviction information info_evic received in the first period. Alternatively, when the weight is applied to the eviction operation according to the above-described embodiment, the eviction information info_evic having a value of 2 or more may be provided to the first current state counter 710.

In addition, the first current state counter 710 may provide a count result to the first previous state register 720 every time the first period elapses, and the first current state counter 710 may perform a count operation in the current first period. The information stored in the first current state counter 710 and the first previous state register 720 may be provided to the first vulnerability setter 730 and may perform the vulnerability detection operation in a short period according to the above-described embodiment.

The information stored in the first previous state register 720 may be provided to the second current state counter 740 in each first cycle, and the information provided to the second current state counter 740 may correspond to the eviction count information num_cnt indicating the number of evictions of the entry in the first cycle. According to an embodiment, the second current state counter 740 may perform a counting operation based on the eviction count information num_cnt provided from the first previous state register 720 every first period. For example, the second current state counter 740 may count value 1 when the number of evictions in each first cycle is greater than a certain threshold Th. In addition, the second current state counter 740 may perform the above-described counting operation in the second period, and may provide a counting result every second period.

In addition, the second current state counter 740 may provide a count result to the second previous state register 750 every time the second period elapses, and the second current state counter 740 may perform a count operation in the current second period. The information stored in the second current state counter 740 and the second previous state register 750 may be provided to the second vulnerability setter 760 and may perform the vulnerability detection operation in the long period according to the above-described embodiment.

In the above-described embodiment, the first period and the second period may be set in various ways. For example, the first period may correspond to a refresh command receiving period tREFI, and the second period may correspond to a refresh period in which all word lines included in the memory device 700 are refreshed at least once.

Fig. 13 is a block diagram illustrating a memory device according to another embodiment. In fig. 13, an example is shown in which the memory device 800 changes a first cycle and a second cycle for performing vulnerability detection.

Referring to fig. 13, the memory device 800 may include control logic 810 and a weak point detector 820, and the control logic 810 may include a period setter 811 and TRR logic 812. In addition, the weak point detector 820 may include a first weak point detector 821 and a second weak point detector 822.

The control logic 810 may adjust the first period and the second period based on various information and/or commands. For example, the control logic 810 may receive at least one of temperature information Temp, first and second vulnerability information info_tier 1 and info_tier 2, and information info_trefi indicating a refresh command reception period. In addition, the memory device 800 may receive commands from a memory controller and the commands from the memory controller may be provided to the control logic 810, or an internal command cmd_i generated in the memory device 800 by decoding the commands may be provided to the control logic 810.

In operation of the memory system, the refresh period may change according to a temperature change of the memory device 800. For example, when the refresh period is set longer, the refresh frequency may decrease as the refresh command reception period tREFI increases. In this case, as the frequency of performing the refresh operation decreases, power consumption of the refresh operation may decrease, but data retention characteristics may deteriorate. In this case, the period setter 811 may detect the degree of weakness of the memory device 800 in a short period by setting at least one of the first period and the second period to be short, and may perform a nursing operation to handle degradation of the data retention characteristic. Based on the above-described period setting, the period setter 811 may supply the information info_p1 about the first period and the information info_p2 about the second period to the weak point detector 820. In addition, according to the above-described embodiments, the TRR logic 812 may generate the eviction information info_evic and provide the eviction information info_evic to the weak point detector 820.

On the other hand, when the first vulnerability information info_tier 1 and the second vulnerability information info_tier 2 are changed very frequently as the first period and/or the second period is set to be short, a large overhead may occur in managing and setting care operations in response to the change. Accordingly, the period setter 811 may determine the frequency of receiving the first vulnerability information info_tier1 and the second vulnerability information info_tier 2 and increase at least one of the first period and the second period based on the frequency. Alternatively, when the levels of the first vulnerability information info_tier 1 and the second vulnerability information info_tier 2 are low for a long period of time, the vulnerability detector 820 may determine that the vulnerability of the memory device 800 remains relatively low. In this case, the period of time for determining the vulnerability may be set longer by increasing at least one of the first period and the second period.

According to the above-described embodiments, in response to attacks of various patterns receivable by the memory device, the memory device itself can recognize the attack pattern and provide information to the memory controller and the application processor according to the result of the determination or internally utilize the information, and thus, the efficiency of a defending algorithm against various types of attacks from the outside can be improved.

Fig. 14 is a block diagram showing an example of setting a cycle mode in a memory device. Fig. 14 illustrates an example in which a short cycle mode or a long cycle mode is selected based on various factors when detecting a weakness of the memory device 900.

The memory device 900 may include control logic 910, a weak point detector 912, and a period selector 913, and the control logic 910 may include a mode selector 911. Since the control logic 910 and the weak point detector 912 operate in the same or similar manner as described above, a detailed description thereof will be omitted.

The control logic 910 may control the mode setting based on various information (e.g., at least one of information about frequency info_freq/vol, voltage of a clock signal used by the memory device 900, temperature information Temp). The weak point detector 912 may output first weak point information info_tier 1 indicating weak points in a relatively short period and second weak point information info_tier 2 indicating weak points in a relatively long period. In addition, based on the control of the control logic 910, the mode selector 911 may supply the control signal ctrl to the weak point detector 912, or the selection signal sel to the period selector 913.

According to an embodiment, the memory device 900 may selectively exploit weak points in relatively short periods or weak points in relatively long periods. According to an embodiment, the weak point detector 912 may include a first weak point detector outputting the first weak point information info_tier 1 and a second weak point detector outputting the second weak point information info_tier 2. The control signal ctrl may disable the first weak point detector or the second weak point detector.

Alternatively, the period selector 913 may multiplex and output the first vulnerability information info_tier 1 and the second vulnerability information info_tier2, or selectively output any one of the first vulnerability information info_tier 1 and the second vulnerability information info_tier2 according to the selection signal sel. The vulnerability information output from the cycle selector 913 may also be provided to various components (e.g., refresh controller, etc.) in the memory device 900.

According to an embodiment, as memory device 900 operates with high performance, when the frequency of the clock signal is relatively high, the voltage level of the clock signal is high, or the temperature within memory device 900 is relatively high, memory device 900 may be in a state sensitive to refresh, and may correspond to a situation in which data loss is highly likely according to the refresh frequency. When the memory device 900 operates in a refresh-sensitive state as described above, it is necessary to detect the weak point of the memory device 900 every short period, and thus, the mode selector 911 may generate the selection signal sel and/or the control signal ctrl for setting the weak point detection mode to the short period detection mode.

On the other hand, when the memory device 900 operates in low performance, the frequency of the clock signal is relatively low, the voltage level of the clock signal is low, or the temperature within the memory device 900 is relatively low, the weak point of the memory device 900 may be detected every relatively long period, and thus, the mode selector 911 may generate the selection signal sel and/or the control signal ctrl for setting the weak point detection mode to the long period detection mode.

Fig. 15 is a block diagram illustrating a data center 1000 including a memory system according to an embodiment. According to some embodiments, the memory device or memory system described above with reference to the figures may be included in an application server and/or a storage server of the data center 1000.

Referring to fig. 15, a data center 1000 may collect various data and provide services, and may also be referred to as a data storage center. For example, the data center 1000 may be a system for operating search engines and databases, or may be a computing system used by an entity such as a bank or government agency. As shown in fig. 15, the data center 1000 may include application servers 50_1 to 50—n and storage servers 60_1 to 60—m (m and n are integers greater than 1). The number n of the application servers 50_1 to 50—n and the number m of the storage servers 60_1 to 60—m may be selected differently according to embodiments, and the number n of the application servers 50_1 to 50—n and the number m of the storage servers 60_1 to 60—m may be different from each other.

The application servers 50_1 to 50_n may include at least one of processors 51_1 to 51_n, memories 52_1 to 52_n, switches 53_1 to 53_n, network Interface Controllers (NICs) 54_1 to 54_n, and storage devices 55_1 to 55_n. The processors 51_1 to 51—n may control the overall operation of the application servers 50_1 to 50—n, and execute instructions and/or data loaded into the memories 52_1 to 52—n by accessing the memories 52_1 to 52—n. As non-limiting examples, the memories 52_1-52—n may include a dual data rate sync DRAM (DDR SDRAM), a High Bandwidth Memory (HBM), a hybrid memory pipe (HMC), a Dual Inline Memory Module (DIMM), an aotom DIMM, or a nonvolatile memory DIMM (NVMDIMM).

According to an embodiment, the number of processors and the number of memories included in the application servers 50_1 to 50—n may be selected differently. According to some embodiments, the processors 51_1 to 51_n and the memories 52_1 to 52_n may provide processor-memory pairs. In some embodiments, the number of processors 51_1 to 51—n and the number of memories 52_1 to 52—n may be different from each other. The processors 51_1 to 51—n may each include a single core processor or a multi-core processor. According to some embodiments, as indicated by the dashed lines in fig. 15, the application servers 50_1 to 50—n may omit the storage devices 55_1 to 55—n. The number of storage devices 55_1 to 55—n included in the application servers 50_1 to 50—n may be selected differently according to embodiments. The processors 51_1 to 51_n, the memories 52_1 to 52_n, the switches 53_1 to 53_n, the NICs 54_1 to 54_n, and/or the storage devices 55_1 to 55_n may communicate with each other through links described above with reference to the drawings.

The storage servers 60_1 to 60_m may include at least one of processors 61_1 to 61_m, memories 62_1 to 62_m, switches 63_1 to 63_m, NICs 64_1 to 64_m, and storage devices 65_1 to 65_m. The processors 61_1 to 61_m and the memories 62_1 to 62_m may operate similarly to the processors 51_1 to 51_n and the memories 52_1 to 52_n of the application servers 50_1 to 50_n described above.

The memories 52_1 to 52_n and the memories 62_1 to 62_m included in the application servers 50_1 to 50_n and the storage servers 60_1 to 60_m may include the memory devices according to the above-described embodiments. For example, the memories 52_1 to 52—n and 62_1 to 62—m may each include a volatile memory device such as a DRAM, and the operation of generating the vulnerability information according to the embodiment may be performed based on the operation of counting the number of activations with respect to the word line and the operation of counting the number of times of performing eviction with respect to the register including a plurality of entries.

The application servers 50_1 to 50—n and the storage servers 60_1 to 60—m may communicate with each other through the network 70. According to some embodiments, the network 70 may be implemented by utilizing Fibre Channel (FC) or ethernet. FC may be a medium for relatively high-speed data transmission, and an optical switch providing high performance/high availability may be used. The storage servers 60_1 to 60_m may be set as file storage, block storage or object storage according to the access method of the network 70.

According to some embodiments, the network 70 may be a storage-only network such as a Storage Area Network (SAN). For example, a SAN may use a FC network and may be a FC-SAN implemented according to the FC protocol (FCP). Alternatively, the SAN may be an IP-SAN implemented using a TCP/IP network and according to the iSCSI (SCSI over TCP/IP or Internet SCSI) protocol. According to some embodiments, the network 70 may be a general purpose network such as a TCP/IP network. For example, the network 70 may be implemented according to protocols such as FC over Ethernet (FCoE), network Attached Storage (NAS), and NVMe over structure (NVMe oF)

Hereinafter, the application server 50_1 and the storage server 60_1 are mainly described, but it should be noted that the description of the application server 50_1 is also applicable to other application servers (e.g., 50—n), and the description of the storage server 60_1 is also applicable to other storage servers (e.g., 60—m).

The application server 50_1 may store data requested to be stored by a user or client in one of the storage servers 60_1 to 60_m through the network 70. In addition, the application server 50_1 may obtain data requested to be read by a user or client from one of the storage servers 60_1 to 60_m through the network 70. For example, the application server 50_1 may be implemented as a web server or a database management system (DBMS).

The application server 50_1 may access the memory 52_n and/or the storage device 55_n comprised in another application server 50_n via the network 70 and/or the memories 62_1 to 62_m and/or the storage devices 65_1 to 65_m comprised in the memory devices 60_1 to 60_m via the network 70. Accordingly, the application server 50_1 may perform various operations on the data stored in the application servers 50_1 to 50—n and/or the storage servers 60_1 to 60—m. For example, the application server 50_1 may execute instructions for moving or copying data between the application servers 50_1 to 50—n and/or the storage servers 60_1 to 60—m. At this time, the data can be moved from the storage devices 65_1 to 65_m of the storage servers 60_1 to 60_m to or directly to the memories 52_1 to 52_n of the application servers 50_1 to 50_n through the memories 62_1 to 62_m of the storage servers 60_1 to 60_m. In some embodiments, the data moved through the network 70 may be data encrypted for security or privacy.

In the storage server 60_1, the interface IF may provide a physical connection between the processor 61_1 and the controller CTRL and a physical connection between the NIC 64_1 and the controller CTRL. For example, the interface IF may be implemented as a direct connection storage section in which the storage device 65_1 is directly accessed through a dedicated cable. In addition, for example, the interface IF may be implemented as one of various interface protocols, such as Advanced Technology Attachment (ATA), serial ATA (ATA), external SATA (e-SATA), small computer interface (SCSI), attached SCSI over the air (SAS), peripheral Component Interconnect (PCI), PCI express (PCIe), NVM express (NVMe), IEEE 1394, universal Serial Bus (USB), secure Digital (SD) card, multimedia card (MMC), embedded multimedia card (eMC), universal Flash (UFS), embedded universal flash (eUFS), and Compact Flash (CF) card interfaces.

In the storage server 60_1, the switch 63_1 may selectively connect the processor 61_1 and the storage 65_1, or may selectively connect the NIC 64_1 and the storage 65_1, under the control of the processor 61_1.

According to some embodiments, NIC 64_1 may include a network interface card, a network adapter, or the like. NIC 64_1 may be connected to network 70 via a wired interface, a wireless interface, a bluetooth interface, an optical interface, etc. The NIC 64_1 may include an internal memory, a DSP, a host bus interface, etc., and may be connected to the processor 61_1 and/or the switch 63_1 through the host bus interface. According to some embodiments, NIC 64_1 may be integrated with at least one of processor 61_1, switch 63_1, and storage 65_1.

The processors 51_1 to 51_n or 61_1 to 61_m in the application servers 50_1 to 50_n or the storage servers 60_1 to 60_m may program data or read data by sending commands to the storage devices 55_1 to 55_n or 65_1 to 65_m or the memories 52_1 to 52_n or 62_1 to 62_m. In this case, the data may be data error-corrected by an Error Correction Code (ECC) engine. The data is data processed through a Data Bus Inversion (DBI) or a Data Mask (DM) and may include Cyclic Redundancy Code (CRC) information. The data may be encrypted data for security or privacy.

In response to read commands received from the processors 51_1 to 51_n and 61_1 to 61_m, the storage devices 55_1 to 55_n and 65_1 to 65_m may send control signals and command/address signals to the non-volatile memory devices NVM (e.g., NAND flash memory devices). Accordingly, when data is read from the nonvolatile memory device NVM, a read enable signal may be input as a data output control signal, and the read enable signal is used to output the data to the DQ bus. The data strobe signal may be generated using a read enable signal. The command and address signals may be latched according to a rising or falling edge of the write enable signal.

The controller CTRL may control the overall operation of the storage device 65_1. According to an embodiment, the controller CTRL may comprise a Static Random Access Memory (SRAM). The controller CTRL may write data to the non-volatile memory device NVM in response to a write command or read data from the non-volatile memory device NVM in response to a read command. For example, the write command and/or the read command may be generated based on a request provided by a host (e.g., the processor 61_1 in the storage server 60_1, the processor 61_m in another storage server 60_m, or the processors 51_1 to 51_n in the application servers 50_1 to 50_n). The buffer BUF may temporarily store (buffer) data to be written to or read from the nonvolatile memory device NVM. According to some embodiments, the buffer BUF may comprise DRAM. In addition, the buffer BUF may store metadata, and the metadata may refer to user data or data generated by the controller CTRL to manage the nonvolatile memory device NVM. The storage device 65_1 may comprise a Security Element (SE) for security or privacy.

In some embodiments, each of the components represented by the blocks shown in fig. 1, 3-6, and 9-15 may be implemented as a variety of numbers of hardware, software, and/or firmware structures that perform the corresponding functions described above according to embodiments. For example, at least one of these components may include various hardware components including digital circuits, programmable or non-programmable logic devices or arrays, application Specific Integrated Circuits (ASICs), transistors, capacitors, logic gates, or other circuits employing direct circuit structures (such as memories, processors, logic circuits, look-up tables, etc.), which may be controlled by one or more microprocessors or other control devices to perform the corresponding functions. Additionally, at least one of these components may comprise a module, program, or portion of code that contains one or more executable instructions for performing specific logic functions and is executed by one or more microprocessors or other control devices. In addition, at least one of these components may further include or be implemented by a processor such as a Central Processing Unit (CPU), microprocessor, etc. that performs the corresponding functions. The functional aspects of the embodiments may be implemented in algorithms that execute on one or more processors. Furthermore, the components, elements, modules or units represented by blocks or processing steps may employ any number of related techniques for electronic configuration, signal processing and/or control, data processing, etc.

While aspects of the embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A method of operating a memory device comprising a plurality of word lines and a register comprising N entries, N being an integer equal to or greater than 2, the method comprising:

storing address information and activation count information about N word lines of the plurality of word lines in the register;

storing address information and activation count information about a first word line different from the N word lines in an entry from which information is evicted among the N entries based on activation of the first word line; and

first vulnerability information is generated based on a number of times an eviction is performed on the register in a first cycle.

2. The method of claim 1, further comprising: the first vulnerability information is output to a memory controller.

3. The method of claim 2, wherein the first vulnerability information is configured to control the memory controller to change a reception cycle of a refresh command provided from the memory controller.

4. The method of claim 1, further comprising: providing the first vulnerability information to a refresh controller in the memory device; and

a refresh operation for the memory device is controlled in accordance with the first vulnerability information.

5. The method of claim 4, further comprising:

identifying frequently activated word lines and weak word lines adjacent to the frequently activated word lines from the plurality of word lines; and

the weak word lines are selectively refreshed.

6. The method of claim 1, further comprising: the number of evictions counted in the previous first cycle is compared with the number of evictions counted in the current first cycle,

wherein the step of generating the first vulnerability information comprises: the first vulnerability information is ranked up based on the number of evictions counted in the current first cycle being greater than the number of evictions counted in the previous first cycle.

7. The method of claim 1, further comprising: second vulnerability information is generated based on a number of evictions in a second cycle that is longer than the first cycle.

8. The method of claim 7, further comprising: outputting the first vulnerability information and the second vulnerability information to a memory controller.

9. The method of claim 7, further comprising: the number of evictions counted in the previous second cycle is compared with the number of evictions counted in the current second cycle,

wherein the step of generating the second vulnerability information comprises: the level of the second vulnerability information is increased based on the number of evictions counted in the current second cycle being greater than the number of evictions counted in the previous second cycle.

10. The method of claim 1, wherein the first vulnerability information indicates one of a plurality of levels, and

wherein the method further comprises delaying or skipping a memory operation based on the first vulnerability information augmentation.

11. A memory device, comprising:

a memory cell array including a plurality of word lines;

a refresh controller configured to control refresh operations on the plurality of word lines;

a control logic circuit configured to store address information and activation count information about N word lines of the plurality of word lines in a register including N entries, N being an integer equal to or greater than 2, evicting information stored in at least one entry of the N entries based on activation of a first word line different from the N word lines, and storing address information and activation count information about the first word line in the at least one entry; and

A vulnerability detection circuit configured to generate first vulnerability information based on a number of times an eviction is performed on the register in a first cycle.

12. The memory device of claim 11, wherein the first vulnerability information indicates one of a plurality of levels, and

wherein the vulnerability detection circuitry is further configured to increase the level of the first vulnerability information based on an increase in the number of times an eviction is performed on the register.

13. The memory device of claim 11, wherein the control logic is further configured to provide eviction information to the vulnerability detection circuitry based on an eviction performed on the register, and

wherein the vulnerability detection circuitry comprises a counter configured to count the eviction information provided in the first cycle.

14. The memory device of claim 11, wherein the vulnerability detection circuit is configured to: the first vulnerability information is generated based on a comparison between the number of evictions in a previous first cycle and the number of evictions in a current first cycle.

15. The memory device of claim 11, wherein the vulnerability detection circuitry is further configured to: second vulnerability information is generated based on second eviction count information based on a number of times eviction is performed in a second period longer than the first period.

16. The memory device of claim 15, wherein the vulnerability detection circuitry is further configured to generate the second vulnerability information based on a comparison between a number of evictions in a previous second cycle and a number of evictions in a current second cycle.

17. The memory device of claim 15, wherein the second period comprises a plurality of first periods, and

wherein the second eviction count information corresponds to a value obtained by counting the number of the plurality of first cycles in which the number of evictions exceeds a threshold.

18. A memory device, comprising:

a memory cell array including a plurality of word lines;

control logic configured to store address information and activation count information in a register comprising N entries, N being an integer equal to or greater than 2, and to generate eviction information based on evictions performed on the register; and

a vulnerability detection circuit configured to generate first vulnerability information corresponding to a first period and second vulnerability information corresponding to a second period longer than the first period based on the eviction information,

Wherein the vulnerability detection circuit comprises:

a first current state counter configured to generate and store eviction count information indicating the number of evictions in a current first cycle; and

a first previous state register configured to store eviction count information corresponding to a previous first cycle, an

Wherein the vulnerability detection circuitry is further configured to generate the first vulnerability information based on a comparison between the eviction count information corresponding to the current first cycle and the eviction count information corresponding to the previous first cycle.

19. The memory device of claim 18, wherein the vulnerability detection circuit further comprises:

a second current state counter configured to receive the eviction count information corresponding to the previous first period from the first previous state register, and to generate and store eviction count information corresponding to a current second period by counting eviction count information for a plurality of first periods in the second period; and

a second previous state register configured to store eviction count information corresponding to a previous second cycle, an

Wherein the vulnerability detection circuitry is further configured to generate the second vulnerability information based on a comparison between the eviction count information corresponding to the current second cycle and the eviction count information corresponding to the previous second cycle.

20. The memory device of claim 19, wherein the second current state counter is further configured to generate, as the eviction count information corresponding to the current second period, a value obtained by counting the number of the plurality of first periods in the second period in which a number of evictions exceeds a certain threshold.