CN1163434A

CN1163434A - Computer incorporating power supply control system therein

Info

Publication number: CN1163434A
Application number: CN 96120851
Authority: CN
Inventors: 金起弘; 洪琎基; 咸盛植; 崔昌勋
Original assignee: Daewoo Telecom Ltd
Current assignee: Daewoo Telecom Ltd
Priority date: 1996-04-24
Filing date: 1996-11-26
Publication date: 1997-10-29

Abstract

A computer incorporates therein a power supply control system. In the control system, a power detection signal is derived first based on a power selection signal generated when a power on/off key of the computer is actuated to control the on-off operations of the computer at a signal detector. And then, at a first generator, a first power control signal and a selection control signal are obtained from the derived power detection signal in response to a first mode control signal. Next, a second power control signal is derived from the power detection signal, the selection control signal and a second mode control signal at a second generator. Finally, the first and the second power control signals are logically combined at a second logic circuit to generate and provide a definitive power control signal to the power supply, thereby selectively supplying DC output voltages to designated components of the computer to control the on-off operations of the computer.

Description

The computing machine of power control system is housed

The present invention relates to a kind of computing machine that power control system is housed, and more specifically, thereby relate to a kind of control system of Switching Power Supply control computer switching manipulation effectively that is used for.

As everyone knows, adopt common power supply widely in comprising the various electric power/electronic equipments of computing machine, wherein the interior required a plurality of dc voltages of a series of processes of object computer are offered the element of appointment in this computing machine from the power supply that is connected to an ac-input power supply.When all required dc voltages were provided for the element of appointment in the computing machine, it can be started working by following in the prior art user instruction of one of well-known several bootstrap algorithms.

Yet in the common power supply that has in such computing machine, when power supply is turned off, this computing machine can not be accessed from for example other communicating terminal.And if when computing machine just moves, power supply is by accidental shutoff, and data in the computing machine and the program of just moving may be lost or interrupt.

Therefore, thus fundamental purpose of the present invention provides a kind of computing machine of the control system of the switching manipulation of Switching Power Supply control computer effectively that is equipped with in it.

According to an aspect of the present invention, provide a kind of computing machine that a control system is housed in it, this control system be used to control provide a plurality of DC output voltages to the operation of a power supply of the designated components of this computing machine to control the switching manipulation of this computing machine, wherein this control system comprises:

Device is used to detect a power supply that is generated during with the switching manipulation of control computer when an electric power on/off key that activates this computing machine and selects signal, to provide a detected power supply selection signal as a power detection signal;

Device is used for producing one first, 1 second and one Third Way control signal when the computer user provides predetermined instruction corresponding to these signals respectively;

First generating apparatus in response to the first mode control signal, is used for selecting control signal by using this power detection signal to generate one first power control signal and;

Second generating apparatus is selected control signal and second and third mode control signal in response to this, is used for by adopting this power detection signal to generate a second source control signal; And

Composite set is used for logically making up first and second power control signals generating a last power control signal and to provide it to power supply, thereby provides the DC output voltage to the switching manipulation with control computer of the element of the appointment of computing machine selectively.

According to another aspect of the present invention, provide a kind of computing machine that a control system is housed in it, this control system be used to control provide a plurality of DC output voltages to the operation of a power supply of the designated components of this computing machine to control the switching manipulation of this computing machine, wherein this control system comprises:

First pick-up unit is used to detect one first power supply that is generated during with the switching manipulation of control computer when an electric power on/off key that activates this computing machine and selects signal, selects signal so that the first detected power supply to be provided;

Second pick-up unit is used to detect a ringdown that is generated during with the operation of starting this computing machine when a received communication terminal of the customer call of arbitrary telecommunication terminal and the coupling of this computing machine, to produce a detected ringdown;

Device is used for producing one first, 1 second, 1 the 3rd and one cubic formula control signal when this computer user provides predetermined instruction corresponding to these signals respectively;

First generating apparatus in response to the first mode control signal, is used for selecting signal by using this detected ringdown to generate a second source;

First composite set is used for logically making up the first detected power supply and selects the signal and second power supply that generates to select signal to produce a power detection signal;

Second generating apparatus in response to the second mode control signal, is used for selecting control signal by adopting this power detection signal to generate one first power control signal and;

The 3rd generating apparatus is selected control signal and the 3rd and cubic formula control signal in response to this, is used for by using this power detection signal to generate a second source control signal; And

Second composite set, be used for logically making up first and second power control signal generating and to provide a last power control signal to this power supply, thus provide selectively the DC output voltage to the element of the appointment of this computing machine to control the switching manipulation of this computing machine.

With reference to the accompanying drawing description of preferred embodiments, above-mentioned and other purpose of the present invention and feature will become obviously by following, in the accompanying drawing:

Fig. 1 shows the block scheme of explanation according to of the present invention one new control system;

Fig. 2 has provided the more detailed block diagram of the ringdown selected cell shown in Fig. 1; And

Fig. 3 has provided the more detailed block diagram of the first power control signal maker shown in Fig. 1.

With reference to Fig. 1, provide the new control system 100 that is used for a computing machine (not shown) one power supply 200 according to of the present invention.Control system 100 of the present invention comprises a power detection signal maker (PDSG) 130, one ringdown selected cell (RSSU) 140, one first and one second source control signal maker (a power control signal maker (DPCSG) 170 and a control module 180 that PCSG ' S) 150 and 160, is last.

When the power lead 201 that connects power supply 200 when 202 link to each other with a power supply source (not shown), no matter the current operation status of computing machine, AC input electric energy passes through these power leads and is provided for first and

second power supply

210 and 220 that comprises in the power supply 200.This first power supply 210 by adopt a common electric rectification method to the AC input electric energy from

power lead

201 and 202 carry out rectification with generate one for example+the dc voltage Vs of 5V to be to wait to be used as the standby voltages in the control system 100 of the present invention.The dc voltage that should generate like this is provided for the element (although not being illustrated for convenience's sake) of appointment included in the control system 100 so that they can be operated by a standby mode through a line 110 then in Fig. 1 to 3.This second source 220 is selectively exported for example V1 to V4 of a plurality of dc voltages by adopting power supply controlling schemes of the present invention, use the AC input electric energy that provides by

line

201 and 202, and this power supply controlling schemes is described in detail with reference to Fig. 1 to 3.

Simultaneously, first power supply selects signal PSS1 warp 120 to be provided for PDSG130, wherein generates this first power supply selection signal and uses this signal selectively to control the switching manipulation of this computing machine by an electric power on/off key (not shown) that activates in this computing machine.For example, if press this electric power on/off key with the initial calculation machine operation, this power supply selects signal to become logic low; And if opposite, then this power supply selects signal to become logic high.It should be noted that the electric power on/off key on the remote controllers that can use this computing machine selects signal so that this first power supply to be provided.

A second source that generates from each ringdown by RSSU140 select signal PSS2 also warp 141 be input to PDSG130, wherein each ringdown be by

telephone wire

122 and 123 and the photo-coupler that is coupled between them be sent out from an Electronic Switching System (ESS).Particularly, a for example phone that is associated with this computing machine when a remote phone or facsimile recorder customer call one and the receiver of a facsimile recorder device (not shown) send to photo-coupler 126 and receiver from ESS sequence ground each ringdown of generation and the

warp

122 and 123 that link to each other with this receiver during with transfers voice information or data.

126 pairs of the photo-couplers that should be made of a light emitting diode and a phototransistor provide to its each ringdown and detect so that the pulse signal of a logic high and low state to be provided, and wherein one has the unusual resistor 127 of small resistor value and is connected between the collector of phototransistor and the line 111 to provide dc voltage on the line 111 to this collector.In a preferred embodiment of the present invention, be designed to when detecting each ringdown by light emitting diode, this phototransistor output is a logic low pulse signal certainly.The pulse signal of this output warp 128 then is provided for the single nothing 180 of control, and gives RSSU140, and this RSSU140 selectively output logic second source high and a logic low selects signal PSS2 warp 141 to give PDSG130.

RSSU140 shown in Fig. 1 comprises one first three-state buffer 144, a phase inverter 145 and ringdown selection circuit (RSSC) 146, and this ringdown selects the more detailed block diagram of circuit (RSSC) 146 to be illustrated in Fig. 2.

Only when the expression logic low pulse signal that at first generates that corresponding ringdown has been detected is provided from phototransistor to first three-state buffer 144, this first three-state buffer 144 is activated, otherwise, if what promptly input to it is any logic low pulse signal that expression detects the corresponding ringdown of following this first signal, then this first three-state buffer 144 can not be activated.Particularly, inputed to an input end of first three-state buffer 144 from this pulse signal of phototransistor by warp 128 at first, this first three-state buffer 144 is according to an input end of selectively the pulse signal relaying of input being given the second three-state buffer 146C from one first impact damper control signal BCS1 of phase inverter 145.

By will be from the anti-phase first impact damper control signal BCS1 that derives of the second source control signal PCS2 on the 2nd PCSG160 shown in Fig. 1 online 161.In other words, the second source control signal on the line 161 by phase inverter 145 by anti-phase with provide one by anti-phase second source control signal IPCS2 to of first three-state buffer 144 as the first impact damper control signal BCS1.

In a preferred embodiment of the present invention,, a default value or the level of second source control signal PCS2 are set to+5V or logic high at PCSG160 when computing machine is not opened or is in the off-position.Two power supplys that send according to the control module 180 on a system address bus 101 and the system data bus 102 are selected signal PSS1 and PSS2, one first address signal ADDS1 and one first data-signal DATAS1, and the default level of this second source control signal PCS2 is one to be suitable for controlling the logic level of this computer operation by adaptively modifying.Provide the details of second source control signal PCS2 with reference to the 2nd PCSG160 shown in Fig. 1 and control module 180 in the back.Should be noted that after the long computing machine that can be as requested of all of first address signal, first data-signal, second address signal, second data-signal, three-address signal and the 3rd data-signal that will come into question performance and be determined.

First three-state buffer 144 is in response to from the first impact damper control signal BCS1 of phase inverter 145 and be activated or be not activated, thereby selectively will be transferred to RSSC146 from the pulse signal of line 128.Include the selection of the RSSC146 of one first programmable array logic (PAL) 146a and one first D flip-flop (DF/F) 146b and one second three-state buffer 146C, selectively export pulse signal from first three-state buffer 144 according to the computer user.

Especially, the one second address signal ADDS2 that is sent by the control module on the system address bus 101 180 is provided for a PAL146a, and is provided for the input end (D) of a DF/F146b by the one second data-signal DATAS2 that the control module on the system data bus 102 180 sends.Be a plurality of programmable read only memory (among the PROM ' S) one can by one or gate array and one and the PAL146a that constitutes of the matrix (not shown) of gate array select in its a plurality of input ends one at the response second address signal ADDS2, for example 103 o'clock, produce a logic high signal, wherein the logic high signal of this generation is provided for another input end of a DF/F146b then as a clock (CLK) signal.

Only (PGT ' S) goes up and triggers the one DF/F146b, shown in the little triangle on its CLK input end in each forward conversion of this CLK signal.From the output of a DF/F146b (/Q) can irrespectively be configured to a logic low or high level by computer user's selection with the current operation status of computing machine in advance.Selection that can be by obtaining such user by the predetermined key on the keyboard (not shown) of for example this computing machine is high or low with the logic that the level to the second data-signal DATAS2 of the input end (D) of a DF/F146b is set on each PGT ' S.In a preferred embodiment of the present invention, for example,, be output as logic low from a DF/F146b if be arranged to wait to be operated according to the ringdown RSSC146 that detects; Otherwise, be logic high.Be fed into of the second three-state buffer 146c then as the second impact damper control signal BCS2 from this output of a DF/F146b.

If input to the second three-state buffer 146c the door be the second logic low impact damper control signal BCS2, it is activated; Otherwise, if promptly input to the second three-state buffer 146c the door be the second logic high impact damper control signal BCS2, it can not be activated.If the second three-state buffer 146c is activated, is transmitted to the PDSG130 shown in Fig. 1 from the pulse signal warp 141 of first three-state buffer 144 and selects signal PCS2 as second source; Otherwise, do not have signal to send PDSG130 to.As shown in Figure 2, for no matter the ringdown RSSC146 that detects is set under the operated situation dc voltage Vs warp 141 on the line 111 be offered PDSG130, connect one between online 111 and 141 and have the very resistor 147 of small resistor value.

Return with reference to Fig. 1, what input to PDSG130 is that first and second power supplys are selected signal PSS1 and PSS2.Be that one only to select signal at two power supplys with the PDSG130 of door all be when representing the logic high of power-off state, to produce a logic high signal; Otherwise produce one and have very closely-spaced logic low signal.Then, be transmitted to the 3rd three-state buffer 142 and a PCSG150 as power detection signal PDS from the output warp 131 of PDSG130.

At a PCSG150, confirm that the 3rd impact damper control signal BCS3 that will be used in the function and the first power control signal PCS1 are by as being derived descriptively in the back selectively carrying out electric power on/off intention.This used electric power on/off intention confirm functional representation when selecting signal PSS1 to become logic low suddenly when first power supply by control module 180 handled functions, wherein said first power supply select signal PSS1 become suddenly logic low be since one is not expected when computer run by the electric power on/off key of this computing machine its operation is caused by termination.The back is described in detail this electric power on/off intention with reference to the 2nd PCSG160 and control module 180 and confirms function.

Referring now to Fig. 3, provide the example block diagram of the PCSG150 shown in Fig. 1.The one PCSG150 comprises one the 2nd PAL152, one the 2nd DF/F153 and a power control signal generative circuit (PCSGC) 157.

Particularly, can be by one or gate array and one and the three-address signal ADDS3 that sends by the control module on the system address bus 101 180 in response of the 2nd PAL152 that constitutes of the matrix (not shown) of gate array and select in its a plurality of output terminals one, for example 104 o'clock, produce a logic high signal and provide this signal, shown in the little triangle on its CLK input end as a CLK signal another input end to the 2nd DF/F153.As everyone knows, if input to its preset (/PR) and remove (/CLR) port all is logic high, then determined by the operation of timing according to one from the output of the 2nd DF/F153.Otherwise its according to input to this/PR and/ signal that CLR holds is determined.As shown in Figure 3, two

resistors

154 and 155 are connected respectively/PR port and line 111 between and/CLR port and ground between, and resistor 156 be connected one be used for output dc voltage V1 second source 220 output line and should/the CLR port between.All these three resistors be used to stably to provide respectively the dc voltage Vs of the output line that is coupled to line 111 and second source 220 and V1 to the 2nd DF/F /PR and/the CLR port.

When computing machine is in off-position, along with the dc voltage from second source 220 will will be cleared for 0, the two DF/F153; And therefore, in this case, will be logic low from its output (Q), wherein the 3rd data-signal DATAS3 that is sent by the control module on the system data bus 102 180 is unimportant and is provided for the input end (D) of the 2nd DF/F153.On the other hand, by suitably changing the place value of the 3rd data-signal DATAS3, when computing machine just is being operated or is being in "on" position, selectively realize electric power on/off intention affirmation function.That is to say, in a preferred embodiment of the present invention, confirm function if set 3 these electric power on/off intentions by the computer user, the 3rd data-signal DATAS3 is set as a logic low, stop aforesaid sudden power operation, wherein the output (Q) from the 2nd DF/F153 will be logic low; Otherwise the 3rd data-signal DATAS3 is set as logic high, and wherein the output (Q) from it will be logic high.Output (Q) from the 2nd DF/F153 is transmitted to PCSGC157 then, and offers the three-state buffer 142 shown in Fig. 1 as the 3rd buffer controller signal BCS3.

When the computer user is not provided with electric power on/off intention affirmation function, the PCSGC157 that includes two

phase inverter

157a and 157d and one the 4th three-state buffer 157b is advantageously used, wherein input to this PCSGC157 phase inverter 157a be a logic high signal.Particularly, phase inverter 157a will carry out from the logic high signal of the 2nd DF/F153 anti-phase with provide a logic low signal to of the 4th three-state buffer 157b as the 4th impact damper control signal BCS4.Respond the 4th logic low impact damper control signal BCS4, the 4th three-state buffer 157b is activated, and therefore, is transmitted to phase inverter 157d from the power detection signal PDS of the PDSG130 shown in the Fig. 1 on the line 131 through resistor 157c.Be provided with that electric power on/off intention is confirmed function and when the 4th three-state buffer 157b responds the 4th logic high impact damper control signal BCS4 in the computer user, adopt resistor 157c that OV or the logic low signal that is connected to ground are offered phase inverter 157d.

At phase inverter 157d, be inverted into one by an anti-phase power detection signal IPDS or a logic high signal from the power detection signal PDS of the 4th three-state buffer 157b or from the logic low signal of resistor 157c, and this signal offered the DPCSG170 shown in Fig. 1 as the first power control signal PCS1 warp 151, for stably offering DPCSG170, between two

lines

111 and 151, connect a resistor 157e with very big resistance value from the output warp 151 of phase inverter 157d.

As can be seen from the above, if computing machine is in off-position or the computer user has set electric power on/off intention affirmation function, the first power control signal CS1 on the line 151 is a logic high; Otherwise this first power control signal is according to being determined from the power detection signal on the line 131.

Return with reference to Fig. 1,142 responses of the 3rd three-state buffer selectively will send the 2nd PCSG160 from the power detection signal PDS of line 131 to from the 3rd impact damper control signal BCS3 of the 2nd DF/F153 shown in Fig. 3.Particularly, when computing machine was in off-position, the 3rd three-state buffer 142 responded from the 3rd logic low impact damper control signal BCS3 of the 2nd DF/F153 and is activated; And therefore, the power detection signal PDS from line 131 is transmitted to the 2nd PCSG160.Yet when computing machine just moved, the 3rd three-state buffer 142 responded from the 3rd impact damper control signal BCS3 of the 2nd DF/F153 and is activated or is not activated, thereby selectively sends power detection signal PDS to the 2nd PCSG160.As what can see, whether be provided with electric power on/off intention affirmation function according to the computer user and carry out such one transfer operation of selecting from above.

The 2nd PCSG160 that can include several register (not shown) that are widely used in the prior art is according to the power detection signal PDS from the 3rd three-state buffer 142, the first address signal ADDS1 on the

bus

101 and 102 and the first data-signal DATAS1 generate a second source control signal PCS2.As mentioned above, the default level of second source control signal is+5V or logic high.

If when computing machine is in off-position, offer the power detection signal PDS that expression that the 2nd PCSG160 should have a logical value has activated the electric power on/off key or detected a ringdown from the 3rd three-state buffer 142, to realize computer operation, the default level of this second source control signal PCS2 is transformed into logic low immediately.This second logic low power control signal PCS2 warp 161 is provided for DPCSG170 and RSSU140.For stably sending DPCSG170 to by line 161, connect a resistor 162 with very big resistance value between online 111 and 161 from the output of the 2nd PCSG160.Then, synchronously offered DPCSG170 from the first logic low power control signal PCS1 of a PCSG150 with through line 161 from the second logic low power control signal of the 2nd PCSG160 by line 151.

This DPCSG, promptly one with door, two inputs that offer it certainly produce logic low signals and the last power control signal DPCS of this logic low signal as a logic low value are provided, warp 171 is given second source 220.Respond the last power control signal DPCS of this logic low, second source 220 generates a plurality of dc voltages, for example V1 to V4 by the AC input electric energy that provides through

power lead

201 and 202 is provided, and they are offered the element of appointment in the computing machine, thereby computing machine can be operated.The power supply that is an on-off mode of one of a plurality of power supplys of knowing in the prior art can advantageously be used on second source 220.

When dc voltage V1 to V4 is provided for the element of appointment in the computing machine, be installed in a CPU (central processing unit) (CPU) (not shown) in the control module 180 and begin boot process according to one of well-known several bootstrap algorithms object computer in the prior art immediately, the register initial value that wherein writes among the 2nd PCSG160 is a logic high.Should be noted that the register initial value the long computing machine that can be as requested in position performance and be determined in advance.After execute protection is handled; control module 180 is exported and is provided a four-address signal ADDS4 and one the 4th data-signal DATAS4 to the 2nd PCSG160 through

bus

101 and 102, thereby the buffer status value that will write among the 2nd PCSG160 is rearranged into logic low.

When computing machine just moved, from other telecommunication terminal, voice messaging or data that for

example telephone wire

122 and 123, or the phone on the order wire 124, facsimile recorder and computing machine send can be received by this control module 180.This control module 180 can comprise a random-access memory (ram), a ROM (read-only memory) (ROM), CPU, a tonal signal detector and a modulator-demodular unit (not shown).Should be noted that CPU, the RAM, ROM and the modulator-demodular unit (not shown) that are installed in the computing machine can be advantageously employed on control module 180.

When receiving voice messaging or data, voice messaging that this receives or data are stored in a first area or the second area of RAM, wherein by using a common ringdown Processing Algorithm to realize that ringdown processing operation is to receive voice messaging or the data that send effectively.

On the other hand, return with reference to Fig. 2, undertaken anti-phasely so that the second source control signal PCS2 of a logic-high value to be provided by 145 couples of second logic low power control signal PCS2 of phase inverter, give the door of first three-state buffer 144 as the first impact damper control signal BCS1 of a logic-high value from the 2nd PCSG160 shown in the Fig. 1 on the line 161.In response to this first logic high impact damper control signal BCS1, first three-state buffer 144 is not activated, and therefore, expression from the pulse signal of the detected ringdown of respectively following of line 128 no longer be transmitted to the second three-state buffer 146c and only from first power supply 210 on the line 111+the dc voltage Vs of 5V or logic high is passed to the PDSG130 shown in Fig. 1 by resistor 147 and line 141.

Return with reference to Fig. 1, select signal PCS1 to become logic low suddenly if offer first power supply of PCSG130 by line 120, if promptly the user supresses the electric power on/off key on the computing machine and ended its operation when computer run, its output one has very closely-spaced logic low signal and with the power detection signal PDS of this signal as a logic low value, sends a PCSG and the 3rd three-state buffer 142 to through 131.Under these circumstances, intention is confirmed function if the computer user is provided with electric power on/off, and the 3rd three-state buffer 142 responds from the 3rd logic low impact damper control signal BCS3 of the 2nd DF/F153 shown in Fig. 3 and is activated; And therefore, be transmitted to the 2nd PCSG160 from the logic low power detection signal PDS of line 131, wherein the buffer status value of the 2nd PCSG160 is transformed into a logic high.In a preferred embodiment of the present invention, be designed on the basis of a schedule time, can monitor by

bus

101 and 102 buffer status values by control module 180 from the 2nd PCSG160.

If the buffer status value that is monitored is a logic high, control module 180 is exported the predetermined guidance information that is pre-stored among its ROM immediately and is confirmed function to be used for the electric power on/off intention, thereby this guidance information (not shown) to the monitor of this computing machine is provided, thereby on this display monitor central monitoring system, shows.In this case, in a preferred embodiment of the present invention, exemplary guidance information is readable for so following: " please import or by the predetermined key on the computer keyboard to end or continue to use a computer ".

In one embodiment of this invention, if offer the signal that control module 180 1 expression computer users wish to end its operation from keyboard, control module 180 outputs and

warp

101 and 102 provide one the 5th address signal ADDS5 and the 5th data-signal DATAS5 to the 2nd PCSG160.In response to the 5th address signal ADDS5 and the 5th data-signal DATAS5, the 2nd PCSG160 will write therein buffer status value and reset to a logic low and export a second source control signal PCS2 who has a logic-high value.Then, Shu Chu the second logic high power control signal PCS2 warp 161 is provided for DPCSG170 like this, and is logic high from the first power control signal PCS1 that a PCSG offers DPCSG170.The basis of DPCSG170 offers its two input signals, generates the last power control signal DPCS of a logic-high value and this signal is offered second source 220.In response to the last power control signal DPCS of this logic high, power supply 220 is turned off, and therefore, does not have voltage to offer computing machine from it.As a result, not having operation in computing machine is performed.

If offer the signal that 180 1 expressions of control module computer user wishes to continue its operation from keyboard, it sends one the 6th address signal ADDS6 to the 2nd PCSG and becomes a logic low with one the 6th data-signal DATAS6 with the buffer status value set that will write therein.Yet in this case, the 2nd PCSG160 exports the second logic low control signal PCS2 more again; Certainly, second source 220 continues dc voltage V1 to V4 is offered the element of appointment in the computing machine so that it can continue operation.

In another preferred embodiment of the present invention, if the guidance information in cycle is not sometime made answer, control system 100 of the present invention is designed to and can handles according in aforesaid two schemes any.

On the other hand, when computing machine just moves, control module 180 monitors voice messaging or the data that are stored among the RAM on a preset time basis, whether receive voice messaging or data termly and be stored among the RAM to verify, if verify the result negate, promptly the cycle is not received voice messaging or data sometime, control module 180 produces one the 7th address signal ADDS7 and one the 7th data-signal DATAS7, thereby through

bus

101 and 102 they is offered the 2nd PCSG160 respectively.In response to the 7th address signal ADDS7 and the 7th data-signal DATAS7, the buffer status value set that the 2nd PCSG160 will write therein becomes a logic low and output to have the second source control signal PCS2 warp 161 of a logic-high value to DPCSG170.DPCSG170 has last power control signal DPCS by adopting the second logic high power control signal PCS2 to generate the band logic high, to provide it to second source 220, and first power control signal PCS1 or the logic high wherein.In response to the last power control signal DPCS of this logic high, power supply 220 is turned off; And therefore, no-voltage offers computing machine from it.Certainly, this computing machine also just is turned off.

When computing machine just moves, if receive data of sending from long-range other computing machine by line 124 corresponding to similar predetermined instructions such as for example CLOSE, or receive one by

line

122 and 123 from remote phone send corresponding to the data of a tone signal and be stored in the RAM to interrupt computer operation, control module 180 sends one the 8th address signal ADDS8 and one the 8th data-signal DATAS8 gives the 2nd PCSG160.In this case, the 2nd PCSG160 also will write the second source control signal PCS2 warp 161 that thereon buffer status value set becomes a logic low and output to have logic-high value and give DPCSG170.This DPCSG170 produces from this first logic high power control signal PCS1 and has the last power control signal DPCS of logic-high value, and provides it to second source 220, and wherein first power control signal also is a logic high.In response to the last power control signal DPCS of this logic high, power supply 220 is turned off; And therefore, no-voltage offers computing machine from it, thereby computing machine also is turned off.As implied above, control system of the present invention is by adopting the power supply controlling schemes of a novelty of the present invention, ON/OFF computer power supply effectively, thereby the switch of control computer operation.

Though specific embodiment illustrates and describes the present invention relatively,, under the prerequisite that does not break away from the spirit and scope of the present invention that define by claims, obviously can make many variations and remodeling to those of ordinary skill in the art.

Claims

1, a kind of computing machine that a control system is housed in it, this control system are used to control the operation of power supply that its interior one designated components to computing machine provides a plurality of DC output voltages with the switching manipulation of control computer, and wherein this control system comprises:

Be used to detect the power supply that generates when the electric power on/off key that activates computing machine is operated with the on-off of control computer and select signal, select the device of signal as a power detection signal so that a detected power supply to be provided;

Be used for when the predetermined instruction that provides respectively by the computer user corresponding to one first, 1 second and one Third Way signal, producing the device of these signals;

First generating apparatus in response to the first mode control signal, is used for selecting control signal by using power detection signal to generate one first power control signal and;

Second generating apparatus responds this selection control signal and second and third mode control signal, is used for by using this power detection signal to generate a second source control signal; And

Composite set is used for logically making up first and second power control signal generating a last power control signal and to provide it to power supply, thereby selectively provides the DC output voltage to the on-off operation with control computer of the designated components of computing machine.

2, the described computing machine of claim 1, wherein second generating apparatus comprises:

First check device is used to verify power detection signal and whether is in first logic state, and wherein this first logic state represents that the electric power on/off key has activated with initial its operation when computing machine is turned off; And if to be used for this power detection signal be to be in first logic state, generate the second source control signal of first logic state;

Second check device, be used to verify power detection signal and whether be in second logic state, wherein this second logic state represents that the electric power on/off key has activated to end its operation when computing machine just moves, if and to be used for this power detection signal be to be in second logic state, control signal and second and the Third Way control signal are selected in response, selectively produce the second source control signal of first logical OR, second logic state; And

Be used for when computing machine turn-offs, power detection signal being coupled to first check device, and response selection control signal, when being used for computer operation, selectively power detection signal is coupled to the device of second check device.

3, the described computing machine of claim 2, wherein second check device comprises:

Be in second logic state if be used for power detection signal, extract the device of the predetermined guidance information that predetermined guidance information is extracted with demonstration from a storer of computing machine;

The second mode control signal that response provides after the demonstration of this predetermined guidance information is used to generate the device of the second source control signal of first logic state with the operation of termination of computations machine; And

The Third Way control signal that response provides after the demonstration of this predetermined guidance information is used to generate the second source control signal of second logic state to continue the operation of computing machine.

4, the described computing machine of claim 2, wherein each comprises an address and a data-signal with the Third Way control signal.

5, the described computing machine of claim 3, wherein first generating apparatus comprises:

One latch means responds the address signal of the first mode control signal, is used to latch its data-signal and selects control signal to produce; And

Control signal is selected in response, is used for by using power detection signal selectively to generate the device of first power control signal of first or second logic state.

6, the described computing machine of claim 2, wherein composite set is by adopting D flip-flop to be operated.

7, the described computing machine of claim 5, wherein latch means is operated by adopting a D flip-flop.

8, the described computing machine of claim 7, wherein first generating apparatus also comprises and being used for by using address signal to generate and provide the clock input end of a clock signal to this D flip-flop.

9, the described computing machine of claim 8, wherein said generation and the device of clock signal is provided is operated by adopting a programmable logic array.

10, the described computing machine of claim 1 wherein is to generate this power supply to select signal when the electric power on/off key on the remote controllers that activate this computing machine is operated with the on-off of control computer.

11, a kind of computing machine that a control system is housed in it, this control system are used to control the operation of power supply that its interior one designated components to computing machine provides a plurality of DC output voltages with the switching manipulation of control computer, and wherein this control system comprises:

First pick-up unit is used to detect first power supply that generates and selects signal when an electric power on/off key that activates computing machine is operated with the on-off of control computer, select signal so that one first detected power supply to be provided;

Second pick-up unit, a ringdown that generates when being used to detect a received communication terminal that the customer call when any one telecommunication terminal links to each other with this computing machine with the initial calculation machine operation is to produce a detected ringdown;

Be used for when providing corresponding predetermined instruction respectively, producing one first, 1 second, 1 the 3rd and the device of a cubic formula control signal by the computer user;

First generating apparatus in response to the first mode control signal, is used for selecting signal by using tested ringdown then to generate a second source;

Second generating apparatus in response to the second mode control signal, is used for selecting control signal by adopting this power detection signal to generate first power control signal and;

Second composite set is used for logically making up first and second power control signal generating and to provide a last power control signal to power supply, thereby selectively provides the DC output voltage to the on-off operation with control computer of the designated components of computing machine.

12, the described computing machine of claim 11, wherein first generating apparatus comprises:

If be used for when computing machine turn-offs, detecting a ringdown, respond the device that the first mode control signal generates the 3rd power supply selection signal of first logic state; And

If be used for detecting the ringdown of following first when computing machine is opened, response second source control signal generates the 3rd power supply of second logic state and selects signal.

13, the described computing machine of claim 12, wherein the 3rd generating apparatus comprises:

First check device is used to verify power detection signal and whether is in first logic state, and this first logic state is represented to activate the electric power on/off key or detected a ringdown with initial its operation when computing machine turn-offs; And if be used for power detection signal and be in first logic state, generate the second source control signal of first logic state;

Second check device, be used to verify power detection signal and whether be in second logic state, this second logic state represents to activate the electric power on/off key to end its operation when computing machine is opened, if and be used for power detection signal and be in second logic state, response selects the control signal and the third and fourth mode control signal selectively to produce the second source control signal of first or second logic state; And

Be used for when computing machine turn-offs power detection signal is coupled to first check device, and response selects control signal, be used for when computing machine is opened, selectively power detection signal being coupled to second check device.

14, the described computing machine of claim 13, wherein second check device comprises:

Be in second logic state if be used for power detection signal, extract the device of the predetermined guidance information that predetermined guidance information is extracted with demonstration from the storage of computing machine;

The Third Way control signal that response provides after the demonstration of predetermined guidance information is used to generate the device of the second source control signal of first logic state with the operation of interruption computing machine; And

The cubic formula control signal that response provides after the demonstration of predetermined guidance information is used to generate the device of the second source control signal of second logic state with the operation of continuation computing machine.

15, the described computing machine of claim 14, wherein said second check device also comprises:

If be used for importing any voice messaging and data from any one telecommunication terminal when computing machine is opened, the second source control signal that generates first logic state is to continue the operation of computing machine; And

If be used for a preset time in the cycle no information be transfused to from any one telecommunication terminal, generate of the operation of the second source control signal of second logic state with the termination of computations machine.

16, the described computing machine of claim 12, wherein each first, second, third and cubic formula control signal comprise an address and a data-signal.

17, the described computing machine of claim 16, wherein second generating apparatus comprises:

One latch means is used to respond the address signal of the second mode control signal, latchs its data-signal and selects control signal to produce; And

Control signal is selected in response, is used for by adopting power detection signal to generate first power control signal.

18, the described computing machine of claim 17, wherein latch means is by adopting a D flip-flop to be operated.

19, the described computing machine of claim 17, wherein second generating apparatus also comprises and being used for by using address signal to generate a clock signal and providing it to the device of a clock input end of this D flip-flop.

20, the described computing machine of claim 19, wherein said to be used to generate and provide the device of clock signal be operated by adopting a programmable logic array.

21, the described computing machine of claim 12, wherein second pick-up unit is operated by adopting a photo-coupler.

22, the described computing machine of claim 12, wherein first composite set be by use one with the door and operated.

23, the described computing machine of claim 12, wherein second composite set be by adopt one with the door and operated.

24, the described computing machine of claim 11 wherein is to generate first power supply to select signal when the electric power on/off key on the actuating computer remote controller is operated with the on-off of control computer.