CN116340240A - Double-chain LVDS synchronous communication method - Google Patents

Double-chain LVDS synchronous communication method Download PDF

Info

Publication number
CN116340240A
CN116340240A CN202310338356.5A CN202310338356A CN116340240A CN 116340240 A CN116340240 A CN 116340240A CN 202310338356 A CN202310338356 A CN 202310338356A CN 116340240 A CN116340240 A CN 116340240A
Authority
CN
China
Prior art keywords
state
lvds
clock
data
pxie
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310338356.5A
Other languages
Chinese (zh)
Inventor
李超
张可立
黄锡汝
郑佳俊
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hefei Zhongke Caixiang Technology Co ltd
Original Assignee
Hefei Zhongke Caixiang Technology Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hefei Zhongke Caixiang Technology Co ltd filed Critical Hefei Zhongke Caixiang Technology Co ltd
Priority to CN202310338356.5A priority Critical patent/CN116340240A/en
Publication of CN116340240A publication Critical patent/CN116340240A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G06F13/4295—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using an embedded synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express

Abstract

The invention relates to LVDS synchronous communication, in particular to a double-chain LVDS synchronous communication method, which utilizes a PXIe_DSTARA bus of a PXIe backboard to realize global clock synchronization, realizes LVDS link clock homology of PXIe_DSTARB and PXIe_DSTARC buses based on the global clock synchronization, carries out link training verification only by receiving and transmitting two LVDS links, and realizes double-chain LVDS synchronous communication in a self-adaptive way; the technical scheme provided by the invention can effectively overcome the defect that the double-chain LVDS stable synchronous communication cannot be realized based on the PXIe backboard in the prior art.

Description

Double-chain LVDS synchronous communication method
Technical Field
The invention relates to LVDS synchronous communication, in particular to a double-chain LVDS synchronous communication method.
Background
Xilinx SelectIO IPCore can instantiate and configure the I/O logic as required to implement the input SERDES, output SERDES and delay functions, such IPCORE has the following characteristics: an input, output or bi-directional bus and a data bus supporting up to 16 bits wide; clock circuitry required to drive the I/O logic may be created; optional data or clock delay insertion; single data rate and double data rate. Thus, the IPcore can be used to implement SERDES communications between field programmable logic arrays (FPGAs), but requires the user to adjust the data to clock relative delay TAP value and select the correct bit edge alignment bitslip value to implement data serial-to-parallel conversion.
The PXIe machine box is added with three groups of high-performance differential star trigger buses PXIe_DSTARA, PXIe_DSTARB and PXIe_DSTARC on the basis of the PXI machine box, and based on the three groups of high-performance differential star trigger buses PXIe_DSTARA, PXIe_DSTARB and PXIe_DSTARC, synchronization and communication between a system clock slot and a peripheral slot can be realized. In experimental matters, a system clock slot of the PXIe chassis can be used as a chassis center node, a synchronous clock is output to a peripheral slot through the PXIe backboard, and information interaction is carried out on the peripheral slot, so that global synchronization and trigger processing are realized. The double-chain LVDS synchronous communication based on the PXIe backboard is significant to the PXIe chassis.
Disclosure of Invention
(one) solving the technical problems
Aiming at the defects existing in the prior art, the invention provides a double-chain LVDS synchronous communication method, which can effectively overcome the defect that the double-chain LVDS stable synchronous communication cannot be realized based on a PXIe backboard in the prior art.
(II) technical scheme
In order to achieve the above purpose, the invention is realized by the following technical scheme:
a double-chain LVDS synchronous communication method utilizes a PXIe_DSTARA bus of a PXIe backboard to realize global clock synchronization, realizes LVDS link clock homology of the PXIe_DSTARB and PXIe_DSTARC buses based on the global clock synchronization, carries out link training verification only by receiving and transmitting two LVDS links, and realizes double-chain LVDS synchronous communication in a self-adaptive mode.
Preferably, the implementing global clock synchronization by using the pxie_dstara bus of the PXIe backplane includes:
the clock card outputs synchronous clocks to all peripheral cards through the PXIe_DSTARA bus, and provides synchronous clock sources for a transmitting end and a receiving end of the LVDS link;
the clock card is a system clock slot board card of the PXIe chassis, and the peripheral card is a peripheral slot board card.
Preferably, the implementation of the LVDS link clock homology of the pxie_dstarb and pxie_dstarc buses performs link training verification only by receiving and transmitting two LVDS links, and the self-adaptive implementation of double-chain LVDS synchronous communication includes:
the clock card sends serial data through a SelectIO internal serializer to the peripheral card through a PXIe_DSTARB bus, and the peripheral card receives the serial data through a SelectIO internal deserializer;
the peripheral card sends serial data via the SelectIO internal serializer to the clock card over the PXIe_DSTARC bus, which receives using the SelectIO internal deserializer.
Preferably, for a transmitting end for transmitting serial data, the serial parameter m of the SelectIO is set to be in a range of 1-16;
for a receiving end for receiving serial data, the delay TAP value and the bit edge alignment bit slip value of the data of the SelectIO and the clock thereof need to be adjusted so as to correctly receive the serial data and realize data serial-parallel conversion.
Preferably, a link from a clock card to a peripheral card is taken as an LVDS link 1, TX1 is used for representing a transmitting end in the LVDS link 1, and RX1 is used for representing a receiving end in the LVDS link 1;
the link from the peripheral card to the clock card is taken as an LVDS link 2, TX2 is used for representing a transmitting end in the LVDS link 2, and RX2 is used for representing a receiving end in the LVDS link 2.
Preferably, TX1 in the LVDS link 1 is divided into 5 states:
the first State tx_state1 of TX1 is RX2, and no connection is established, and the signature K1 is transmitted: entering a second State Tx_State2 of TX1 if RX2 establishes a connection;
the second State tx_state2 of TX1 is RX2 established connection, transmitting signature K2: entering a third State Tx_State3 of TX1 if RX1 establishes a connection; entering a first State Tx_State1 of TX1 if RX2 is disconnected;
the third State tx_state3 of TX1 establishes a connection for both RX1 and RX2, and if the RX2 buffer is full, the signature K3 is sent, otherwise the signature K2 is sent: if RX1 is cached to be full, entering a fourth State Tx_State4 of TX 1; if there is data transmission in LVDS link 1, entering a fifth State Tx_State5 of TX 1; entering a first State Tx_State1 of TX1 if RX2 is disconnected; entering a second State Tx_State2 of TX1 if RX1 is disconnected;
the fourth State tx_state4 of TX1 is the RX1 buffer full State, if the RX2 buffer is full, the signature K3 is sent, otherwise the signature K2 is sent: if RX1 is not fully cached, entering a third State Tx_State3 of TX 1;
the fifth State tx_state5 of TX1 is the TX1 data transmission State, and after transmitting a signature K4, n data codes are transmitted, and the process ends with the signature K5: after the data transmission is completed, the third State tx_state3 of TX1 is entered.
Preferably, RX1 in the LVDS link 1 is divided into 7 states:
the first State rx_state1 of RX1 is a bit edge alignment bit slice value adjustment State, and performs a reception scan from 0 to serial parameter m on the data and clock relative delay TAP value at this time: if the RX1 receives the feature code K1/K2/K3, entering a third State Rx_State3 of the RX 1; if the scanning is finished RX1 still does not receive the feature codes K1/K2/K3, entering a second State Rx_State2 of RX 1;
the second State rx_state2 of RX1 is the data and clock relative delay TAP value adjustment State, adding 1 to the TAP value: if the TAP scanning is completed, entering a fourth State Rx_State4 of the RX 1; otherwise, entering a first State Rx_State1 of RX 1;
the third State Rx_State3 of the RX1 is a data and clock relative delay TAP value recording State, and the usable TAP value is recorded and enters the second State Rx_State2 of the RX 1;
the fourth State Rx_State4 of the RX1 is a data and clock relative delay TAP value selection State, and because the TAP value represents the relative delay relation of the data and the clock, each TAPbin has a much smaller relative data establishment holding time, a continuous TAP value can be established, the State selects the intermediate value of the continuously available TAP value as the final use value of the RX1, and enters the fifth State Rx_State5 of the RX 1;
the fifth State rx_state5 of RX1 is a bit edge alignment bitskip value confirmation State, and the bitskip value is adjusted again according to the final TAP value to perform connection establishment: if the connection is established, entering a sixth State Rx_State6 of RX 1; if the bitslip scanning is finished and connection is not established yet, entering a first State Rx_State1 of RX1 to reselect the TAP value;
the sixth State rx_state6 of RX1 is RX1 established connection, sends RX1 connected signal to TX2, and sends RX1 buffer full signal to TX2 if RX1 buffer is less than 3n data frames: if the feature code K2 is received, sending an RX2 connected signal to TX2; if the characteristic code K3 code is received, an RX2 buffer full signal is sent to TX2; if the feature code K4 is received, entering a seventh State Rx_State7 of the RX 1; if other feature codes are received, entering a first State Rx_State1 of RX1, and pulling down an RX1 connected signal;
the seventh State rx_state7 of RX1 is an RX1 data reception State, and receives n data codes: if the feature code K5 is received after the nth data code, the sixth State rx_state6 of RX1 is entered, and if the feature code K5 is not received, the first State rx_state1 of RX1 is entered and the RX1 connected signal is pulled down.
(III) beneficial effects
Compared with the prior art, the double-chain LVDS synchronous communication method provided by the invention realizes self-adaptive synchronous communication between the system clock slot and the peripheral slot on the PXIe backboard, can establish an LVDS data transmission link with self-adaption, delay fixing and stable connection, and has the following advantages:
(1) Double-chain LVDS self-adaptive connection without extra signal link
The clocks of the nodes at the two ends of the LVDS link are homologous, and data transmission is carried out through mutual authentication of the establishment condition of the link;
(2) Transmission delay fixing
Under the clock domain of the receiving end, the data output is fixed, so the data transmission delay of the receiving end is fixed;
(3) High reliability
The data and clock relative delay TAP value and the bit edge alignment bitslip value are regulated through SelectIO, a section of intermediate value of the continuous usable TAP value is selected as connection, the maximum time margin is ensured to be established between the data and the clock, the connection can be stably established, and in addition, the connection is automatically reconnected after being disconnected, so that the stable transmission of the data is ensured;
4) Extensibility and method for making same
The method is not limited to the PXIe case, can be used under the condition of receiving and transmitting end clock homology, and has expandability.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a clock card in a PXIe chassis connected to a peripheral card in the present invention;
FIG. 2 is a diagram showing a dual-chain LVDS synchronous communication model between a clock card and a peripheral card according to the present invention;
fig. 3 is a schematic state diagram of a transmitting end in an LVDS link from a clock card to a peripheral card according to the present invention;
fig. 4 is a schematic diagram illustrating a state of a receiving end in an LVDS link from a clock card to a peripheral card according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more clear, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in FIG. 1, global clock synchronization is realized by using a PXIe_DSTARA bus of a PXIe backboard, LVDS link clocks of the PXIe_DSTARB and PXIe_DSTARC buses are realized based on the global clock synchronization, link training verification is carried out only by receiving and transmitting two LVDS links, and double-chain LVDS synchronous communication is realized in a self-adaptive mode.
(1) Global clock synchronization using the PXIe DSTARA bus of the PXIe backplane includes:
the clock card outputs synchronous clocks to all peripheral cards through the PXIe_DSTARA bus, and provides synchronous clock sources for a transmitting end and a receiving end of the LVDS link;
the clock card is a system clock slot board card of the PXIe chassis, and the peripheral card is a peripheral slot board card.
(2) The method for realizing LVDS link clock homology of PXIe_DSTARB and PXIe_DSTARC buses, carrying out link training verification only by receiving and transmitting two LVDS links, and realizing double-chain LVDS synchronous communication in a self-adaptive manner comprises the following steps:
the clock card sends serial data through a SelectIO internal serializer to the peripheral card through a PXIe_DSTARB bus, and the peripheral card receives the serial data through a SelectIO internal deserializer;
the peripheral card sends serial data via the SelectIO internal serializer to the clock card over the PXIe_DSTARC bus, which receives using the SelectIO internal deserializer.
In the technical scheme, for a transmitting end for transmitting serial data, the serial parameter m of SelectIO is set to be 1-16;
for a receiving end for receiving serial data, the delay TAP value and the bit edge alignment bit slip value of the data of the SelectIO and the clock thereof need to be adjusted so as to correctly receive the serial data and realize data serial-parallel conversion.
As shown in FIG. 1, the PXIe chassis is added with three groups of high-performance differential star trigger buses PXIe_DSTARA, PXIe_DSTARB and PXIe_DSTARC on the basis of the PXI chassis, so that a star-shaped interconnection channel between a system clock slot and a peripheral slot in the chassis can be realized. The PXIe_DSTARA is LVPECL level standard, and the direction is from a system clock slot to a peripheral slot; PXIe_DSTARB is LVDS level standard, and the direction is from a system clock slot to a peripheral slot; pxie_dstarc is the LVDS level standard, oriented from peripheral slot to system clock slot.
As shown in fig. 2, a link from a clock card to a peripheral card is taken as an LVDS link 1, TX1 represents a transmitting end in the LVDS link 1, and RX1 represents a receiving end in the LVDS link 1;
the link from the peripheral card to the clock card is taken as an LVDS link 2, TX2 is used for representing a transmitting end in the LVDS link 2, and RX2 is used for representing a receiving end in the LVDS link 2.
As shown in fig. 3, TX1 in LVDS link 1 is divided into 5 states:
the first State tx_state1 of TX1 is RX2, and no connection is established, and the signature K1 is transmitted: entering a second State Tx_State2 of TX1 if RX2 establishes a connection;
the second State tx_state2 of TX1 is RX2 established connection, transmitting signature K2: entering a third State Tx_State3 of TX1 if RX1 establishes a connection; entering a first State Tx_State1 of TX1 if RX2 is disconnected;
the third State tx_state3 of TX1 establishes a connection for both RX1 and RX2, and if the RX2 buffer is full, the signature K3 is sent, otherwise the signature K2 is sent: if RX1 is cached to be full, entering a fourth State Tx_State4 of TX 1; if there is data transmission in LVDS link 1, entering a fifth State Tx_State5 of TX 1; entering a first State Tx_State1 of TX1 if RX2 is disconnected; entering a second State Tx_State2 of TX1 if RX1 is disconnected;
the fourth State tx_state4 of TX1 is the RX1 buffer full State, if the RX2 buffer is full, the signature K3 is sent, otherwise the signature K2 is sent: if RX1 is not fully cached, entering a third State Tx_State3 of TX 1;
the fifth State tx_state5 of TX1 is the TX1 data transmission State, and after transmitting a signature K4, n data codes are transmitted, and the process ends with the signature K5: after the data transmission is completed, the third State tx_state3 of TX1 is entered.
As shown in fig. 4, RX1 in LVDS link 1 is divided into 7 states:
the first State rx_state1 of RX1 is a bit edge alignment bit slice value adjustment State, and performs a reception scan from 0 to serial parameter m on the data and clock relative delay TAP value at this time: if the RX1 receives the feature code K1/K2/K3, entering a third State Rx_State3 of the RX 1; if the scanning is finished RX1 still does not receive the feature codes K1/K2/K3, entering a second State Rx_State2 of RX 1;
the second State rx_state2 of RX1 is the data and clock relative delay TAP value adjustment State, adding 1 to the TAP value: if the TAP scanning is completed, entering a fourth State Rx_State4 of the RX 1; otherwise, entering a first State Rx_State1 of RX 1;
the third State Rx_State3 of the RX1 is a data and clock relative delay TAP value recording State, and the usable TAP value is recorded and enters the second State Rx_State2 of the RX 1;
the fourth State Rx_State4 of the RX1 is a data and clock relative delay TAP value selection State, and because the TAP value represents the relative delay relation of the data and the clock, each TAPbin has a much smaller relative data establishment holding time, a continuous TAP value can be established, the State selects the intermediate value of the continuously available TAP value as the final use value of the RX1, and enters the fifth State Rx_State5 of the RX 1;
the fifth State rx_state5 of RX1 is a bit edge alignment bitskip value confirmation State, and the bitskip value is adjusted again according to the final TAP value to perform connection establishment: if the connection is established, entering a sixth State Rx_State6 of RX 1; if the bitslip scanning is finished and connection is not established yet, entering a first State Rx_State1 of RX1 to reselect the TAP value;
the sixth State rx_state6 of RX1 is RX1 established connection, sends RX1 connected signal to TX2, and sends RX1 buffer full signal to TX2 if RX1 buffer is less than 3n data frames: if the feature code K2 is received, sending an RX2 connected signal to TX2; if the characteristic code K3 code is received, an RX2 buffer full signal is sent to TX2; if the feature code K4 is received, entering a seventh State Rx_State7 of the RX 1; if other feature codes are received, entering a first State Rx_State1 of RX1, and pulling down an RX1 connected signal;
the seventh State rx_state7 of RX1 is an RX1 data reception State, and receives n data codes: if the feature code K5 is received after the nth data code, the sixth State rx_state6 of RX1 is entered, and if the feature code K5 is not received, the first State rx_state1 of RX1 is entered and the RX1 connected signal is pulled down.
In the technical scheme of the application, the connection processes of the LVDS link 1 and the LVDS link 2 are mirror images, and after the RX1 and the RX2 are connected, the double-chain LDVS realizes a data transmission channel. Because the global clock source is output by the clock card through the PXIe_DSTARA bus, the data output is fixed in the LVDS link transmission path under the clock domain of the receiving end, thereby realizing the synchronous transmission of the data. In addition, the method realizes the link reconnection operation, and can adaptively reconnection after the link is disconnected, thereby ensuring stable data transmission.
The above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims (7)

1. A double-chain LVDS synchronous communication method is characterized in that: global clock synchronization is realized by using the PXIe_DSTARA bus of the PXIe backboard, LVDS link clock homology of the PXIe_DSTARB and the PXIe_DSTARC buses is realized based on the global clock synchronization, link training verification is carried out only by receiving and transmitting two LVDS links, and double-chain LVDS synchronous communication is realized in a self-adaptive mode.
2. The method for double-chain LVDS synchronous communication according to claim 1, wherein: the method for realizing global clock synchronization by using the PXIe_DSTARA bus of the PXIe backboard comprises the following steps:
the clock card outputs synchronous clocks to all peripheral cards through the PXIe_DSTARA bus, and provides synchronous clock sources for a transmitting end and a receiving end of the LVDS link;
the clock card is a system clock slot board card of the PXIe chassis, and the peripheral card is a peripheral slot board card.
3. The method for double-chain LVDS synchronous communication according to claim 2, wherein: the implementation of the LVDS link clock homology of the PXIe_DSTARB and PXIe_DSTARC buses only carries out link training verification by receiving and transmitting two LVDS links, and the self-adaptation implementation of double-chain LVDS synchronous communication comprises the following steps:
the clock card sends serial data through a SelectIO internal serializer to the peripheral card through a PXIe_DSTARB bus, and the peripheral card receives the serial data through a SelectIO internal deserializer;
the peripheral card sends serial data via the SelectIO internal serializer to the clock card over the PXIe_DSTARC bus, which receives using the SelectIO internal deserializer.
4. A method of double-chain LVDS synchronous communication according to claim 3, wherein: for a transmitting end for transmitting serial data, setting a serial parameter m of SelectIO to be 1-16;
for a receiving end for receiving serial data, the delay TAP value and the bit edge alignment bit slip value of the data of the SelectIO and the clock thereof need to be adjusted so as to correctly receive the serial data and realize data serial-parallel conversion.
5. The method for dual-chain LVDS synchronous communication according to claim 4, wherein: taking a link from a clock card to a peripheral card as an LVDS link 1, wherein TX1 represents a transmitting end in the LVDS link 1, and RX1 represents a receiving end in the LVDS link 1;
the link from the peripheral card to the clock card is taken as an LVDS link 2, TX2 is used for representing a transmitting end in the LVDS link 2, and RX2 is used for representing a receiving end in the LVDS link 2.
6. The method for dual-chain LVDS synchronous communication according to claim 5, wherein: TX1 in LVDS link 1 is divided into 5 states:
the first State tx_state1 of TX1 is RX2, and no connection is established, and the signature K1 is transmitted: entering a second State Tx_State2 of TX1 if RX2 establishes a connection;
the second State tx_state2 of TX1 is RX2 established connection, transmitting signature K2: entering a third State Tx_State3 of TX1 if RX1 establishes a connection; entering a first State Tx_State1 of TX1 if RX2 is disconnected;
the third State tx_state3 of TX1 establishes a connection for both RX1 and RX2, and if the RX2 buffer is full, the signature K3 is sent, otherwise the signature K2 is sent: if RX1 is cached to be full, entering a fourth State Tx_State4 of TX 1; if there is data transmission in LVDS link 1, entering a fifth State Tx_State5 of TX 1; entering a first State Tx_State1 of TX1 if RX2 is disconnected; entering a second State Tx_State2 of TX1 if RX1 is disconnected;
the fourth State tx_state4 of TX1 is the RX1 buffer full State, if the RX2 buffer is full, the signature K3 is sent, otherwise the signature K2 is sent: if RX1 is not fully cached, entering a third State Tx_State3 of TX 1;
the fifth State tx_state5 of TX1 is the TX1 data transmission State, and after transmitting a signature K4, n data codes are transmitted, and the process ends with the signature K5: after the data transmission is completed, the third State tx_state3 of TX1 is entered.
7. The method for dual-chain LVDS synchronous communication according to claim 6, wherein: RX1 in LVDS link 1 is divided into 7 states:
the first State rx_state1 of RX1 is a bit edge alignment bit slice value adjustment State, and performs a reception scan from 0 to serial parameter m on the data and clock relative delay TAP value at this time: if the RX1 receives the feature code K1/K2/K3, entering a third State Rx_State3 of the RX 1; if the scanning is finished RX1 still does not receive the feature codes K1/K2/K3, entering a second State Rx_State2 of RX 1;
the second State rx_state2 of RX1 is the data and clock relative delay TAP value adjustment State, adding 1 to the TAP value: if the TAP scanning is completed, entering a fourth State Rx_State4 of the RX 1; otherwise, entering a first State Rx_State1 of RX 1;
the third State Rx_State3 of the RX1 is a data and clock relative delay TAP value recording State, and the usable TAP value is recorded and enters the second State Rx_State2 of the RX 1;
the fourth State Rx_State4 of the RX1 is a data and clock relative delay TAP value selection State, and because the TAP value represents the relative delay relation of the data and the clock, each TAPbin has a much smaller relative data establishment holding time, a continuous TAP value can be established, the State selects the intermediate value of the continuously available TAP value as the final use value of the RX1, and enters the fifth State Rx_State5 of the RX 1;
the fifth State rx_state5 of RX1 is a bit edge alignment bitskip value confirmation State, and the bitskip value is adjusted again according to the final TAP value to perform connection establishment: if the connection is established, entering a sixth State Rx_State6 of RX 1; if the bitslip scanning is finished and connection is not established yet, entering a first State Rx_State1 of RX1 to reselect the TAP value;
the sixth State rx_state6 of RX1 is RX1 established connection, sends RX1 connected signal to TX2, and sends RX1 buffer full signal to TX2 if RX1 buffer is less than 3n data frames: if the feature code K2 is received, sending an RX2 connected signal to TX2; if the characteristic code K3 code is received, an RX2 buffer full signal is sent to TX2; if the feature code K4 is received, entering a seventh State Rx_State7 of the RX 1; if other feature codes are received, entering a first State Rx_State1 of RX1, and pulling down an RX1 connected signal;
the seventh State rx_state7 of RX1 is an RX1 data reception State, and receives n data codes: if the feature code K5 is received after the nth data code, the sixth State rx_state6 of RX1 is entered, and if the feature code K5 is not received, the first State rx_state1 of RX1 is entered and the RX1 connected signal is pulled down.
CN202310338356.5A 2023-03-31 2023-03-31 Double-chain LVDS synchronous communication method Pending CN116340240A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310338356.5A CN116340240A (en) 2023-03-31 2023-03-31 Double-chain LVDS synchronous communication method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310338356.5A CN116340240A (en) 2023-03-31 2023-03-31 Double-chain LVDS synchronous communication method

Publications (1)

Publication Number Publication Date
CN116340240A true CN116340240A (en) 2023-06-27

Family

ID=86880382

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310338356.5A Pending CN116340240A (en) 2023-03-31 2023-03-31 Double-chain LVDS synchronous communication method

Country Status (1)

Country Link
CN (1) CN116340240A (en)

Similar Documents

Publication Publication Date Title
CN204906388U (en) Repeater circuit
EP2552026B1 (en) Low output skew double data rate serial encoder
CN109947681B (en) Serializer/deserializer and high-speed interface protocol exchange chip
US20140006649A1 (en) N-phase polarity output pin mode multiplexer
JP4783245B2 (en) Transceiver, transmitter, and receiver
US6703866B1 (en) Selectable interface for interfacing integrated circuit modules
US20100246658A1 (en) System and method for programmably adjusting gain and frequency response in a 10-gigabit ethernet/fibre channel system
JP2014523189A5 (en)
WO1994022247A1 (en) Bus transceiver with binary data transmission mode and ternary control transmission mode
JP3448241B2 (en) Interface device for communication device
CN110868228A (en) Retimer data communication device
US20200389244A1 (en) Method for a slave device for calibrating its output timing, method for a master device for enabling a slave device to calibrate its output timing, master device and slave device
KR20110101250A (en) Transmission of parallel data flows on a parallel bus
US20050018760A1 (en) Source synchronous I/O bus retimer
JP4652393B2 (en) Receiving device and receiving method
CN106953825A (en) Multi-user's multiple access communication transmitting and method of reseptance based on weight score Fourier conversion
CN116340240A (en) Double-chain LVDS synchronous communication method
US7764614B2 (en) Multi-mode management of a serial communication link
CN113890553B (en) Receiver for high speed data and low speed command signal transmission
CN113992209A (en) Conversion circuit and serializer/deserializer
CN114374124A (en) Bidirectional signal transmission connecting line
US8294503B1 (en) Method and apparatus for reducing jitter in a transmitter
JP2000332741A (en) Communication apparatus
US20110181335A1 (en) Interface circuit, lsi, server device, and method of training the interface circuit
KR100986042B1 (en) A source driver integrated circuit capable of interfacing multi pair data and display panel driving system including the integrated circuit

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination