CN116338241A

CN116338241A - Accelerometer digitizing circuit

Info

Publication number: CN116338241A
Application number: CN202111585400.XA
Authority: CN
Inventors: 韩旭; 于湘涛; 许中生; 魏超; 彭振新; 李贺; 顾文华; 刘超; 刘伶艳
Original assignee: Aerospace Science and Industry Inertia Technology Co Ltd
Current assignee: Aerospace Science and Industry Inertia Technology Co Ltd
Priority date: 2021-12-22
Filing date: 2021-12-22
Publication date: 2023-06-27

Abstract

The invention provides an accelerometer digitizing circuit, which comprises a power supply functional unit, a reference source unit, an analog interface unit, an AD converter, a controller and a communication interface unit, wherein the power supply functional unit is used for supplying power to the reference source unit, the analog interface unit, the AD converter, the controller and the communication interface unit, the reference source unit is respectively connected with the analog interface unit and the AD converter, the reference source unit is used for providing a voltage reference for the AD converter and providing offset voltage for the analog interface unit, the analog interface unit is used for converting a current signal output by a speedometer into a voltage signal and realizing impedance matching, the AD converter is used for converting the voltage signal of an analog quantity into the voltage signal of a digital quantity, the controller is used for realizing the time sequence control of the AD converter and the communication and transmission of the digital signal, and the communication interface unit is used for realizing the data communication with external equipment. The technical scheme of the invention is applied to solve the technical problem of low circuit conversion precision of the digital circuit scheme in the prior art.

Description

Accelerometer digitizing circuit

Technical Field

The invention relates to the technical field of accelerometers, in particular to an accelerometer digitizing circuit.

Background

Quartz flexible accelerometers (accelerometers for short) are used as important inertial devices, mainly for measuring acceleration signals input along their sensitive axes. The method has the characteristics of high resolution, high stability and the like, and is widely applied to the fields of aerospace, aviation, petroleum and the like.

The accelerometer outputs an analog current signal, and the upper system is applied digitally, and the current signal is required to be converted into digital quantity by a digital circuit and then participates in the operation of a processor. Along with the continuous expansion of application, in some fields (such as the gravity measurement field), the focus is on the resolution index of the digital circuit in a certain bandwidth range, and the existing digital circuit scheme has low circuit conversion precision and can not meet the application requirement.

Disclosure of Invention

The invention provides an accelerometer digitizing circuit, which can solve the technical problem of low circuit conversion precision of the digitizing circuit scheme in the prior art.

The invention provides an accelerometer digitizing circuit, which comprises a power supply functional unit, a reference source unit, an analog interface unit, an AD converter, a controller and a communication interface unit, wherein the power supply functional unit is respectively connected with the reference source unit, the analog interface unit, the AD converter, the controller and the communication interface unit, the power supply functional unit is used for supplying power to the reference source unit, the analog interface unit, the AD converter, the controller and the communication interface unit, the reference source unit is respectively connected with the analog interface unit and the AD converter, the reference source unit is used for providing voltage reference for the AD converter and providing offset voltage for the analog interface unit, the analog interface unit is used for converting a current signal output by a speedometer into a voltage signal and realizing impedance matching, the AD converter is used for converting the voltage signal of an analog quantity into a voltage signal of a digital quantity, the controller is used for realizing time sequence control of the AD converter, communication and transmission of the digital signal, and the communication interface unit is used for realizing data communication with external equipment.

Further, the sampling rate of the AD converter is less than or equal to 100Hz, and the minimum current resolution capability of the AD converter is less than or equal to 1nA.

Further, the input of the power supply functional unit includes a +15v analog power supply and a +5v digital power supply, the output of the power supply functional unit includes a +15v analog power supply, a +5v analog power supply and a +3.3v digital power supply, the +15v output analog power supply is used for supplying power to the analog interface unit, the +5v output analog power supply is used for supplying power to the AD converter and the reference source unit, and the +3.3v output digital power supply is used for supplying power to the AD converter, the controller and the communication interface unit.

Further, the reference source unit has an input of +5v analog voltage and outputs a reference voltage of +2.5v.

Further, the analog interface unit includes an inverse proportional operational amplifier circuit.

Further, the inverse proportion operational amplifier circuit comprises an operational amplifier and a sampling resistor, wherein the power supply rejection ratio and the common mode rejection ratio of the operational amplifier are both greater than or equal to 100dB, the input offset current is less than or equal to 10nA, the open loop gain is greater than or equal to 120dB, and the sampling resistor is a winding resistor.

Further, the controller realizes the timing control of the AD converter, the communication and transmission of the digital signal, and specifically comprises: initializing a register; initializing an interrupt flag bit; initializing an AD converter; the AD converter is started, converts the voltage signal of the analog quantity into the voltage signal of the digital quantity, reads data from the AD converter when receiving the external interrupt trigger, and sends the data to the communication interface unit.

By means of the technical scheme, the invention provides the accelerometer digitizing circuit, analog current signals output by the accelerometer are subjected to signal conditioning, analog-to-digital conversion and are converted into digital signals to be output through the communication interface unit, and the reference source unit is arranged to provide voltage references for the AD converter and offset voltages for the analog interface unit. Therefore, compared with the prior art, the accelerometer digitizing circuit provided by the invention can ensure the circuit conversion precision and reduce the reference source voltage fluctuation caused by overlarge load change.

Drawings

The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 shows a schematic diagram of the structural composition of an accelerometer digitizing circuit provided in accordance with a specific embodiment of the invention;

FIG. 2 illustrates a flow chart of software within a controller provided in accordance with a specific embodiment of the present invention;

fig. 3 shows a schematic diagram of an accelerometer digitizing circuit printed board, provided in accordance with a specific embodiment of the invention.

Wherein the above figures include the following reference numerals:

10. a power supply functional unit; 20. a reference source unit; 30. an analog interface unit; 40. an AD converter; 50. a controller; 60. and a communication interface unit.

Detailed Description

It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. The following description of at least one exemplary embodiment is merely exemplary in nature and is in no way intended to limit the invention, its application, or uses. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments in accordance with the present application. As used herein, the singular is also intended to include the plural unless the context clearly indicates otherwise, and furthermore, it is to be understood that the terms "comprises" and/or "comprising" when used in this specification are taken to specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof.

The relative arrangement of the components and steps, numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise. Meanwhile, it should be understood that the sizes of the respective parts shown in the drawings are not drawn in actual scale for convenience of description. Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but should be considered part of the specification where appropriate. In all examples shown and discussed herein, any specific values should be construed as merely illustrative, and not a limitation. Thus, other examples of the exemplary embodiments may have different values. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further discussion thereof is necessary in subsequent figures.

As shown in fig. 1 to 3, according to an embodiment of the present invention, there is provided an accelerometer digitizing circuit including a power supply function unit 10, a reference source unit 20, an analog interface unit 30, an AD converter 40, a controller 50 and a communication interface unit 60, the power supply function unit 10 being respectively connected to the reference source unit 20, the analog interface unit 30, the AD converter 40, the controller 50 and the communication interface unit 60, the power supply function unit 10 being configured to supply power to the reference source unit 20, the analog interface unit 30, the AD converter 40, the controller 50 and the communication interface unit 60, the reference source unit 20 being respectively connected to the analog interface unit 30 and the AD converter 40, the reference source unit 20 being configured to provide a voltage reference to the AD converter 40 and a bias voltage to the analog interface unit 30, the analog interface unit 30 being configured to convert a current signal outputted from a speedometer into a voltage signal and to implement impedance matching, the AD converter 40 being configured to convert a voltage signal of an analog quantity into a digital quantity, the controller 50 being configured to implement timing control of the AD converter 40, the communication and the communication interface unit 60 being configured to implement data transmission of the digital signal.

By means of the configuration mode, the accelerometer digitizing circuit is provided, analog current signals output by the accelerometer are subjected to signal conditioning, analog-to-digital conversion and are converted into digital signals to be output through the communication interface unit, and the reference source unit is arranged to provide voltage references for the AD converter and offset voltages for the analog interface unit. Therefore, compared with the prior art, the accelerometer digitizing circuit provided by the invention can ensure the circuit conversion precision and reduce the reference source voltage fluctuation caused by overlarge load change.

Further, in the present invention, the AD converter 40 mainly realizes the conditioning of the accelerometer output current signal, and completes the current/voltage signal conversion and impedance matching, in order to ensure the circuit conversion accuracy, the sampling rate of the AD converter 40 is less than or equal to 100hz, and the minimum current resolution of the AD converter 40 is less than or equal to 1nA.

Further, in the present invention, in order to ensure stable power supply of the respective components in the circuit, the input of the power supply function unit 10 may be configured to include ±15V analog power supply and +5V digital power supply, the output of the power supply function unit 10 includes ±15V analog power supply, +5V analog power supply and +3.3v digital power supply, the output analog power supply of ±15V is used to supply power to the analog interface unit 30, the output analog power supply of +5V is used to supply power to the AD converter 40 and the reference source unit 20, and the output digital power supply of +3.3v is used to supply power to the AD converter 40, the controller 50 and the communication interface unit 60. Wherein the AD converter 40 includes an analog part and a digital part, the +5v output analog power supply is used to supply power to the analog part of the AD converter 40, and the +3.3v output digital power supply is used to supply power to the digital part of the AD converter 40.

Further, in the present invention, the reference source unit 20 functions to provide a voltage reference and a bias voltage, the input of the reference source unit 20 is an analog voltage of +5v, and the output is a reference voltage of +2.5v.

Further, in the present invention, the analog interface unit 30 includes an inverse proportional operational amplifier circuit. The reverse proportion operational amplification circuit comprises an operational amplifier and a sampling resistor, wherein the power supply rejection ratio and the common mode rejection ratio of the operational amplifier are both greater than or equal to 100dB, the input offset current is less than or equal to 10nA, the open loop gain is greater than or equal to 120dB, and the sampling resistor is a winding resistor. As a specific embodiment of the invention, the operational amplifier is an OP series high-precision low-noise operational amplifier of TI company, and the sampling resistor affecting the current/voltage conversion precision is a precision winding resistor with low temperature drift.

Further, in the present invention, as shown in fig. 2, the controller 50 implements timing control of the AD converter 40, communication and transmission of digital signals, and specifically includes: initializing a register; initializing an interrupt flag bit; initializing an AD converter; the AD converter 40 is started, the AD converter 40 converts the voltage signal of the analog quantity into the voltage signal of the digital quantity, and when an external interrupt trigger is received, the data is read from the AD converter 40 and sent to the communication interface unit 60.

For a further understanding of the present invention, the accelerometer digitizing circuit provided by the present invention is described in detail below in conjunction with FIGS. 1-3.

As shown in fig. 1 to 3, according to an embodiment of the present invention, there is provided an accelerometer digitizing circuit capable of conditioning and converting an accelerometer current signal and outputting the same as a digital signal, the accelerometer digitizing circuit having a minimum current resolution of 1nA or less, the accelerometer digitizing circuit comprising a power supply function unit 10, a reference source unit 20, an analog interface unit 30, an AD converter 40, a controller 50 and a communication interface unit 60, the power supply function unit 10 being respectively connected to the reference source unit 20, the analog interface unit 30, the AD converter 40, the controller 50 and the communication interface unit 60, the reference source unit 20 being respectively connected to the analog interface unit 30 and the AD converter 40, the reference source unit 20 being adapted to provide a voltage reference for the AD converter 40 and a bias voltage for the analog interface unit 30, the analog interface unit 30 being adapted to convert a current signal outputted by the accelerometer into a voltage signal and to realize an impedance conversion for the AD converter 40 being adapted to realize a time-sequential signal and the communication device being adapted to the digital signal and the communication device being adapted to realize the communication of the digital signal and the communication signal.

In the embodiment, the power supply functional unit and the core device are low-noise voltage stabilizing source chips of LINEAR company, the series of voltage stabilizing devices have good noise characteristics, and the output voltage noise is 20 MuVrms (10 Hz-100 kHz). The power supply functional unit realizes the function of converting input voltage and supplying power to other functional units. The input of the power supply functional unit is + -15V analog power supply and +5V digital power supply. The output of which comprises a + -15V analog power supply, +5V analog power supply and +3.3V digital power supply, the + -15V output analog power supply being used to power the analog interface unit 30; the +5v output analog power supply is used to supply power to the analog part of the AD converter and the reference source unit 20; the +3.3V output digital power supply is used for supplying power to the digital part of the AD converter, the controller and the communication interface unit.

The reference source unit 20 functions to provide a voltage reference with an input of +5v analog voltage and an output of +2.5v reference voltage. In the scheme, the condition that the voltage reference source drives a plurality of loads is avoided, the voltage reference source is only used for the voltage reference of the AD converter and the offset voltage of the analog interface, reference source voltage fluctuation caused by overlarge load change is reduced, and the circuit conversion precision is improved. The core device of the reference source unit 20 is a reference source chip of Maxim company, the temperature coefficient is 1 ppm/DEG C, the output voltage peak value is 1.5 mu V, and the stability is 30ppm (1000 h).

The analog interface unit 30 mainly realizes the conditioning of the accelerometer output current signal, completes the conversion of the current/voltage signal and the impedance matching, and the analog interface unit 30 selects an inverse proportion operational amplifier circuit to output the analog voltage signal to the AD converter functional unit. The reverse proportion operational amplifier circuit comprises an operational amplifier and a sampling resistor, wherein the operational amplifier is an OP series high-precision low-noise operational amplifier of TI company, the power supply rejection ratio and the common mode rejection ratio are not less than 100dB, the input offset current is not more than 10nA, and the open loop gain is not less than 120dB. The sampling resistor affecting the current/voltage conversion precision selects a precision winding resistor with low temperature drift.

The AD converter 40 mainly realizes the digital conversion function, the number of bits of the converter directly affects the current resolution, in the scheme, a 24-bit high-precision converter is adopted, a 24-bit delta-sigma AD converter of ADI company is selected, the sampling rate is not more than 100Hz, and the minimum current resolution of the scheme is less than or equal to 1nA.

The controller 50 mainly completes the timing control, digital signal communication and transmission of the AD converter. The internal software flow mainly comprises the steps of initializing a controller, initializing an AD converter, starting the AD converter, reading data from the AD converter and sending the data to a communication interface, wherein a SILICON LAB company C8051F33X series singlechip is adopted as a scheme, and the core of the SILICON LAB is configured as an 8051 core and 768bytes RAM,8kB Flash. The controller is equipped with standard UART and SPI interfaces, and can realize the control and communication transmission functions of the converter.

The communication interface unit 60 mainly realizes a matching function with a standard communication protocol between external devices, and externally transmits the digital quantity of the acceleration measurement information. The proposal adopts an RS422 standard asynchronous serial communication interface, and the baud rate is not less than 9600bit/s. The scheme selects Max348X series RS422/RS485 standard communication interface chip of Maxim company to communicate data with the outside, and the baud rate is not less than 9600bit/s.

In summary, the present invention provides an accelerometer digitizing circuit, which conditions an analog current signal output by an accelerometer through an analog interface unit and converts the analog current signal into an analog voltage signal, the analog voltage signal is converted into a digital signal by an AD converter according to a predetermined sampling frequency, the digital signal is output through a communication interface unit, and a reference source unit is provided to provide a voltage reference for the AD converter and a bias voltage for the analog interface unit. Therefore, compared with the prior art, the accelerometer digitizing circuit provided by the invention can ensure the circuit conversion precision and reduce the reference source voltage fluctuation caused by overlarge load variation; the accelerometer output digitization can be realized, and the minimum current resolution capability is better than 1nA.

Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be positioned in other different ways (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In addition, the terms "first", "second", etc. are used to define the components, and are only for convenience of distinguishing the corresponding components, and the terms have no special meaning unless otherwise stated, and therefore should not be construed as limiting the scope of the present invention.

The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. An accelerometer digitizing circuit, characterized in that the accelerometer digitizing circuit comprises a power supply functional unit (10), a reference source unit (20), an analog interface unit (30), an AD converter (40), a controller (50) and a communication interface unit (60), the power supply functional unit (10) is respectively connected with the reference source unit (20), the analog interface unit (30), the AD converter (40), the controller (50) and the communication interface unit (60), the power supply functional unit (10) is used for supplying power to the reference source unit (20), the analog interface unit (30), the AD converter (40), the controller (50) and the communication interface unit (60), the reference source unit (20) is respectively connected with the analog interface unit (30) and the AD converter (40), the reference source unit (20) is used for providing a voltage reference for the AD converter (40) and a value voltage for the analog interface unit (30), the analog interface unit (30) is used for converting an output signal to an analog signal, the analog interface unit (30) is used for realizing a time-sequential voltage-to-sequence, the analog interface unit (30) is used for realizing a voltage-to-sequence signal, the analog interface unit (40) is used for realizing a time-sequence-to-sequence-match the signal, and the analog signal (40) is used for the analog signal (40) and the analog signal (40) is converted, the communication interface unit (60) is used for realizing data communication with external equipment.

2. Accelerometer digitizing circuit according to claim 1, characterized in that the sampling rate of the AD converter (40) is less than or equal to 100Hz, the minimum current resolution capability of the AD converter (40) being less than or equal to 1nA.

3. Accelerometer digitizing circuit according to claim 1, characterized in that the input of the power supply functional unit (10) comprises a ± 15V analog power supply and a +5V digital power supply, the output of the power supply functional unit (10) comprises a ± 15V analog power supply, a +5V analog power supply and a +3.3v digital power supply, the ± 15V output analog power supply being used for powering the analog interface unit (30), the +5V output analog power supply being used for powering the AD converter (40) and the reference source unit (20), the +3.3v output digital power supply being used for powering the AD converter (40), the controller (50) and the communication interface unit (60).

4. An accelerometer digitizing circuit according to claim 3, wherein the reference source unit (20) has an input of +5v analog voltage and an output of +2.5v reference voltage.

5. Accelerometer digitizing circuit according to claim 4, characterized in that the analog interface unit (30) comprises an inverse proportional operational amplifying circuit.

6. The accelerometer digitizing circuit of claim 5, wherein the inverse proportional operational amplifier circuit comprises an operational amplifier and a sampling resistor, the power supply rejection ratio and the common mode rejection ratio of the operational amplifier are both greater than or equal to 100dB, the input offset current is less than or equal to 10nA, the open loop gain is greater than or equal to 120dB, and the sampling resistor is a wound resistor.

7. Accelerometer digitizing circuit according to claim 1, wherein the controller (50) implements the timing control of the AD converter (40), the communication and transmission of digital signals, in particular comprising: initializing a register; initializing an interrupt flag bit; initializing the AD converter; the AD converter (40) is started, the AD converter (40) converts the voltage signal of the analog quantity into the voltage signal of the digital quantity, and when the external interrupt trigger is received, the data is read from the AD converter (40) and sent to the communication interface unit (60).