CN111342785B - Signal conditioning circuit - Google Patents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
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Abstract
The invention discloses a signal conditioning circuit and a signal conditioning method, wherein the signal conditioning circuit comprises a sensor, and the input end of the sensor is connected with a direct current power supply VCC; the reverse input end of the first amplifying circuit is connected with the output end of the sensor; the analog-to-digital conversion unit is connected with the output end of the first amplifying circuit; the control unit is connected with the output end of the analog-to-digital conversion unit and generates an output signal according to the change of the output signal of the first amplifying circuit; the input end of the digital-to-analog conversion unit is connected with the output end of the control unit; and the reverse input end of the second amplifying circuit is connected with the output end of the analog-digital conversion unit, the output end of the second amplifying circuit is connected with one end of a feedback resistor (R0), and the other end of the feedback resistor (R0) is connected with the reverse input end of the first amplifying circuit. The signal conditioning circuit realizes the simultaneous consideration of the detection range and the detection precision, and can improve the anti-interference capability of the detection circuit.
Description
Technical Field
The invention relates to the technical field of signal measurement, in particular to a signal conditioning circuit.
Background
In the technical fields of aerospace, unmanned aerial vehicles and the like, the acceleration signal can represent the running condition of the device, so that the control requirement on the acceleration is high. The quartz accelerometer can detect the external acceleration signal by detecting the quality, then the signal is demodulated and amplified by a circuit, and finally the output current signal is in direct proportion to the acceleration signal, so that the output current of the accelerometer head of the quartz accelerometer is generally adopted to reflect the acceleration. In the prior art, a signal conditioning circuit for detecting output current usually adopts a sampling resistor to convert the current into voltage, then the voltage follower is used for enhancing the load capacity of the signal, and then the signal is amplified and voltage biased and then transmitted to an analog-to-digital converter ADC. However, in the detection method in the prior art, although the acquisition capability and the load capability of signals are improved, no current is generated on the signal line of the voltage follower, and the anti-interference capability is weakened; if the range of the output ADC is required to be increased, the sampling resistance needs to be reduced, but when the acceleration signal is weak, the signal input to the ADC only occupies a small part of the input range of the ADC; if the sampling resistor is increased, although the weak acceleration signal can fully utilize the input range of the ADC to improve the precision, the acceleration signal exceeds the input range of the ADC when the acceleration signal is large, and the measuring range and the precision cannot be simultaneously considered.
Disclosure of Invention
Therefore, the invention aims to overcome the defects that the detection circuit in the prior art has low anti-interference capability and cannot consider the range and the precision, thereby providing a signal conditioning circuit.
According to a first aspect, an embodiment of the present invention provides a signal conditioning circuit, including: the input end of the sensor is connected with a direct current power supply VCC; the reverse input end of the first amplifying circuit is connected with the output end of the sensor; the analog-to-digital conversion unit is connected with the output end of the first amplifying circuit; the control unit is connected with the output end of the analog-to-digital conversion unit and generates an output signal according to the change of the output signal of the first amplifying circuit; the input end of the digital-to-analog conversion unit is connected with the output end of the control unit; and the reverse input end of the second amplifying circuit is connected with the output end of the analog-digital conversion unit, the output end of the second amplifying circuit is connected with one end of a feedback resistor R0, and the other end of the feedback resistor R0 is connected with the reverse input end of the first amplifying circuit.
With reference to the first aspect, in a first implementation manner of the first aspect, the first amplifying circuit includes a first operational amplifier U1, a first resistor R1 and a bias resistor R2, where the first resistor R1 is connected between a reverse input end and an output end of the first operational amplifier U1, and one end of the bias resistor R2 is connected to a forward input end of the first operational amplifier U1, and the other end is grounded.
With reference to the first aspect, in a second implementation manner of the first aspect, the second amplifying circuit includes a second operational amplifier U2, a second resistor R3, and a bias resistor R4, where the second resistor R3 is connected between an inverting input terminal and an output terminal of the second operational amplifier U2, and one end of the bias resistor R4 is connected to a forward input terminal of the second operational amplifier U2, and the other end is grounded.
With reference to the first aspect, in a third implementation manner of the first aspect, the control unit includes an FPGA or an ARM or a DSP or an MCU.
With reference to the first aspect, in a fourth implementation manner of the first aspect, the circuit further includes: and the voltage stabilizing circuit is connected with the output end of the first amplifying circuit and the input end of the analog-digital conversion unit.
With reference to the fourth implementation manner of the first aspect, in a fifth implementation manner of the first aspect, the voltage stabilizing circuit includes: the capacitor comprises a third resistor R5, a fourth resistor R6 and a capacitor C3, wherein one end of the fourth resistor R6 is connected with one end of the capacitor C1 in series, and two ends of the third resistor R5 are respectively connected with the other end of the fourth resistor R6 and the other end of the capacitor C1.
With reference to the fifth implementation manner of the first aspect, in a sixth implementation manner of the first aspect, the circuit further includes: and one end of the fifth resistor R7 is connected with the output end of the digital-to-analog conversion unit, and the other end of the fifth resistor R7 is connected with the reverse input end of the second operational amplifier U2.
According to a second aspect, an embodiment of the present invention provides a signal conditioning method, for use in the signal conditioning circuit according to the first aspect or any implementation manner of the first aspect, including: the control unit adjusts the output current of the digital-to-analog conversion unit to counteract the current change of the input end of the first amplifying circuit, and the adjusting formula is as follows:
Ifb＝(Vo2-Vi)/R0
wherein Ifb is the output current, vo2 is the output voltage of the second amplifying circuit, vi is the input voltage of the inverting input terminal of the first amplifying circuit, and R0 is the feedback resistor.
The technical scheme of the invention has the following advantages:
The invention provides a signal conditioning circuit and a signal conditioning method, wherein the signal conditioning circuit comprises a sensor, and the input end of the sensor is connected with a direct current power supply VCC; the reverse input end of the first amplifying circuit is connected with the output end of the sensor; the analog-to-digital conversion unit is connected with the output end of the first amplifying circuit; the control unit is connected with the output end of the analog-to-digital conversion unit and generates an output signal according to the change of the output signal of the first amplifying circuit; the input end of the digital-to-analog conversion unit is connected with the output end of the control unit; and the reverse input end of the second amplifying circuit is connected with the output end of the analog-digital conversion unit, the output end of the second amplifying circuit is connected with one end of the feedback resistor R0, and the other end of the feedback resistor R0 is connected with the reverse input end of the first amplifying circuit. The signal conditioning circuit improves the anti-interference capability of the detection circuit, and realizes the simultaneous consideration of the detection range and the detection precision.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a circuit diagram of signal conditioning according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of signal conditioning according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of signal conditioning according to an embodiment of the present invention;
fig. 4 is a circuit diagram of signal conditioning according to an embodiment of the invention.
Detailed Description
The following description of the embodiments of the present invention will be made apparent and fully in view of the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the present invention, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
In addition, the technical features of the different embodiments of the present invention described below may be combined with each other as long as they do not collide with each other.
The embodiment provides a signal conditioning circuit which can be applied to the field of high-precision current measurement of aerospace, unmanned aerial vehicles and the like. As shown in fig. 1, includes: the device comprises a sensor, a first amplifying circuit, an analog-to-digital conversion unit, a control unit, a digital-to-analog conversion unit, a second amplifying circuit and a feedback resistor. The input end of the sensor is connected with a direct current power supply VCC, and the output end of the sensor is connected with the reverse input end of the first amplifying circuit; the analog-to-digital conversion unit is connected with the output end of the first amplifying circuit; the control unit is connected with the output end of the analog-to-digital conversion unit and generates an output signal according to the change of the output signal of the first amplifying circuit; the input end of the digital-to-analog conversion unit is connected with the output end of the control unit; the reverse input end of the second amplifying circuit is connected with the output end of the analog-digital conversion unit, the output end of the second amplifying circuit is connected with one end of the feedback resistor R0, and the other end of the feedback resistor R0 is connected with the reverse input end of the first amplifying circuit.
The sensor is exemplified by a sensor reflecting physical characteristic parameters, i.e. a sensor capable of reflecting physical characteristic changes through output current, such as an acceleration sensor and a temperature sensor, the sensor is not limited by the application, and the sensor can be determined by a person skilled in the art according to actual needs. The input end of the sensor may include two input terminals, namely a positive terminal connected to the positive electrode of the dc power supply VCC and a ground terminal connected to the ground terminal of the dc power supply VCC, such as an acceleration sensor; a power supply access terminal may also be included, through which it is connected to the dc power supply VCC, such as a temperature sensor. In the application, dan Yingjia is taken as an example, namely, an acceleration sensor is taken as an example, the analog-digital conversion unit, the digital-analog conversion unit and the control unit are connected into a closed loop, the analog-digital conversion unit can send the detected output voltage of the first amplifying circuit to the control unit, the control unit can adjust the output current of the digital-analog conversion unit based on a target algorithm, so that the output voltage of the second amplifying circuit is adjusted, the current passing through the feedback resistor R0 is changed, the current change of the output end of the sensor caused by the acceleration change is counteracted, namely, the voltage change of the input end of the first amplifying circuit is counteracted, and the detection value of the analog-digital conversion unit is returned to an initial value. The initial value of the analog-to-digital conversion unit may be set to an intermediate value of the operating voltage of the analog-to-digital conversion unit, because the sensitivity of the analog-to-digital conversion unit is optimal when at the intermediate value of the operating voltage. The signal conditioning circuit can ensure that the detection value of the analog-to-digital conversion unit is in an initial value no matter how much the voltage of the direct-current power supply VCC is input to the sensor, namely, no matter how much the current of the sensor output end is input to the input end of the first amplifying circuit, so that the detection precision is irrelevant to the measuring range, and certain current can be provided on the signal path through reasonable parameter configuration, thereby improving the anti-interference capability of the circuit.
As an alternative embodiment of the present application, as shown in fig. 2, the first amplifying circuit includes a first operational amplifier U1, a first resistor R1 and a bias resistor R2, where the first resistor R1 is connected between the inverting input terminal and the output terminal of the first operational amplifier U1, and one end of the bias resistor R2 is connected to the positive input terminal of the first operational amplifier U1, and the other end is grounded. The second amplifying circuit comprises a second operational amplifier U2, a second resistor R3 and a bias resistor R4, wherein the second resistor R3 is connected between the reverse input end and the output end of the second operational amplifier U2, one end of the bias resistor R4 is connected with the positive input end of the second operational amplifier U2, and the other end of the bias resistor R4 is grounded. The control unit comprises an FPGA or a singlechip or a DSP.
The control unit is taken as an FPGA, the analog-to-digital conversion unit is an ADC, the working voltage of the ADC is 0-V, the digital-to-analog conversion unit is taken as a DAC, the working voltage of the ADC is regulated to be V/2, and the output current of the DAC can be set through the FPGA, so that the ADC works at the middle value of the measuring range of the ADC, namely, the input current is zero, and the working voltage of the ADC is V/2. The positive input end of the first operational amplifier U1 and the positive input end of the second operational amplifier U2 are respectively connected with reference voltages Vbias1 and Vbias2, and the reference voltages of the positive input ends of the first operational amplifier U1 and the second operational amplifier U2 are V/2 and V respectively. The specific adjusting steps are as follows:
(1) When the input current Iacc1=0 of the quartz gauge head, the FPGA sets the output current of the DAC as I 0, so that the output voltage Vo2=V-R3×I 0 =V/2 of the second operational amplifier; the input voltage Vi at the inverting input terminal of the first operational amplifier is constantly equal to V/2, so that the total current isum=iacc1+ifb=0 input to the inverting input terminal of the first operational amplifier, after passing through the first resistor R1, the output voltage vo1=v/2-isum×r1=v/2 of the first operational amplifier, i.e. the ADC works at the intermediate value of its measurement range.
(2) When the input current Iacc1 of the quartz gauge head is not equal to 0, the input voltage Vi of the reverse input end of the first operational amplifier is constant to be V/2, and the total current Isum=Iacc 1+Ifb input to the reverse input end of the first operational amplifier; after passing through the first resistor R1, the output voltage of the first operational amplifier vo1=v/2-Isum R1;
(3) The ADC transmits the detection value of V1 to the FPGA;
(4) The FPGA controls the DAC to change the output current delta I, and then Vo2=V-R3 (I 0 < + > delta I);
(5) Calculating feedback currents Ifb, ifb= (Vo 2-Vi)/r0=c×Δi through the feedback resistor R0 according to Vo2, vi and the feedback resistor, so that c×Δi just counteracts iac 1, and when isum=iac1+ifb=0, vo1 returns to the midpoint V/2 of the ADC operating range.
In the process of adjusting the working voltage of the ADC, the current digital quantity output by the DAC can reflect the acceleration, and when Dan Yingjia is output with large current, the DAC can adjust the current output so as to offset the large current output by the quartz adder, so that the problem of over-range of the output of the ADC does not occur. And a resistor is arranged between the output end and the reverse input end of the first operational amplifier and the second operational amplifier, so that current passing on the signal line is ensured at the moment, and the anti-interference capability is enhanced.
As an alternative embodiment of the present application, as shown in fig. 3, the signal conditioning circuit further includes: the voltage stabilizing circuit is connected with the output end of the first amplifying circuit and the input end of the analog-digital conversion unit; the voltage stabilizing circuit comprises: the third resistor R5, the fourth resistor R6 and the capacitor C1 are connected in series, and are connected in parallel with the third resistor R5. The voltage stabilizing circuit is arranged to enable the voltage on the signal line to be more stable, and the third resistor R5, the fourth resistor R6 and the capacitor C1 are arranged to enable the output voltage of the first amplifying circuit to be detected more easily, so that the detection effect is better.
As an alternative embodiment of the present application, as shown in fig. 3, the signal conditioning circuit further includes: and one end of the fifth resistor R7 is connected with the output end of the digital-to-analog conversion unit, and the other end of the fifth resistor R7 is connected with the reverse input end of the second amplifying circuit. The output voltage on the signal line between the digital-to-analog conversion unit and the second amplifying circuit can be made more stable by providing the fifth resistor R7.
The present embodiment provides a signal conditioning method, which may be used in the signal conditioning circuit described in the foregoing embodiment, and the method includes:
the control unit adjusts the output current of the digital-to-analog conversion unit to counteract the current change of the input end of the first amplifying circuit, and the adjusting formula is as follows:
Ifb＝(Vo2-Vi)/R0
wherein Ifb is the output current, vo2 is the output voltage of the second amplifying circuit, vi is the input voltage of the inverting input terminal of the first amplifying circuit, and R0 is the feedback resistor.
Illustratively, the adjusting step is referred to the description of the corresponding portion of the above embodiment, and will not be repeated here. As shown in fig. 4, when the first amplifying circuit includes a first operational amplifier U1, a first resistor R1, and a bias resistor R2; the second amplifying circuit comprises a second operational amplifier U2, a second resistor R3 and a bias resistor R4; the control unit comprises an FPGA; the voltage stabilizing circuit comprises a third resistor R5, a fourth resistor R6 and a capacitor C3, and is connected with the output end of the first operational amplifier U1 and the input end of the analog-to-digital conversion unit; one end of the fifth resistor R7 is connected with the output end of the digital-to-analog conversion unit, and the other end of the fifth resistor R7 is connected with the reverse input end of the second operational amplifier U2. Wherein the first operational amplifier U1 and the second operational amplifier U2 adopt chips OPA21871DR, a feedback resistor R0 is 100 omega/1206, a first resistor R1 is 1KΩ/1206, a second resistor R3 is 200 omega/1206, a bias resistor R2 and a bias resistor R4 are 1KΩ/0603, a third resistor R5, a fourth resistor R6 and a capacitor C3 are respectively 1KΩ/0603, 1KΩ/0603 and 0.1 mu 50V/0603, a fifth resistor R7 is 15 omega/1206, an analog-digital conversion unit ADC is 700-MAX1168BEEG, the working range is 0-4.096V, a digital-analog conversion unit DAC is DAC8750IPWP, the working voltage of the ADC is set to be always 2.048V,
First, the reference voltages at the positive input terminals of the first operational amplifier U1 and the second operational amplifier U2 are 2.048V and 4.096V, respectively. When the input current iacc1=0 of the quartz gauge head, the FPGA sets the output current Iout of the DAC to 10.24mA, so that the output voltage vo2=4.096-200×10.24ma=2.048v of the second operational amplifier; the input voltage Vi at the inverting input terminal of the first operational amplifier is equal to 2.048V, ifb= (Vo 2-Vi)/r1=0, so the total current isum=iac1+ifb=0 input to the inverting input terminal of the first operational amplifier, after passing through the first resistor R1, the output voltage vo1=2.048v-Isum 1kΩ=2.048v of the first operational amplifier, i.e. the ADC operates at the middle value of its range.
Secondly, when the input current Iacc1 of the quartz gauge head is not equal to 0, the input voltage Vi of the reverse input end of the first operational amplifier is equal to 2.048V, and the total current Isum=Iacc 1+Ifb is input to the reverse input end of the first operational amplifier; after passing through the first resistor R1, the output voltage of the first operational amplifier vo1=2.048v—isum 1kΩ;
Thirdly, the ADC transmits the detection value of Vo3 to the FPGA; the FPGA controls the DAC to change the output current delta I, and then Vo2=4.096V-200Ω (10.24mA+delta I);
again, the feedback current Ifb, ifb= (Vo 2-Vi)/r0= -200 Δi/100= -2 Δi is calculated from Vo2, vi and feedback resistor R0 such that-2 Δi just counteracts Iacc1, when isum=iac1+ifb=0, vo1 returns to the mid-point of the ADC operating range at 2.048V.
When Dan Yingjia is output with large current, namely the current at the input end of the first amplifying circuit changes, the current output by the quartz adding meter can represent acceleration, if the current is too large, the problem that the output of the analog-to-digital conversion unit generates an overscan is caused, and then the acceleration measurement precision is reduced. The FPGA is used for adjusting the current output of the digital-to-analog conversion unit so as to offset the large current output by the quartz adder, so that the problem of over-range cannot occur in the output of the analog-to-digital conversion unit, the range and the measurement precision are considered, and the accuracy of acceleration measurement is ensured.
It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the invention.
Claims (6)
1. A signal conditioning circuit, comprising:
the input end of the sensor is connected with a direct current power supply (VCC);
The reverse input end of the first amplifying circuit is connected with the output end of the sensor;
The analog-to-digital conversion unit is connected with the output end of the first amplifying circuit;
The control unit is connected with the output end of the analog-to-digital conversion unit and generates an output signal according to the change of the output signal of the first amplifying circuit;
The input end of the digital-to-analog conversion unit is connected with the output end of the control unit;
The reverse input end of the second amplifying circuit is connected with the output end of the analog-to-digital conversion unit, the output end of the second amplifying circuit is connected with one end of a feedback resistor (R0), and the other end of the feedback resistor (R0) is connected with the reverse input end of the first amplifying circuit;
the control unit adjusts the output current of the digital-to-analog conversion unit to counteract the current change of the input end of the first amplifying circuit, and the adjusting formula is as follows:
Ifb＝(Vo2-Vi)/R0
wherein Ifb is output current, vo2 is output voltage of the second amplifying circuit, vi is input voltage of the reverse input end of the first amplifying circuit, and R0 is feedback resistor;
the first amplifying circuit comprises a first operational amplifier (U1), a first resistor (R1) and a bias resistor (R2), wherein the first resistor (R1) is connected between the reverse input end and the output end of the first operational amplifier (U1), one end of the bias resistor (R2) is connected with the positive input end of the first operational amplifier (U1), and the other end of the bias resistor is grounded;
The second amplifying circuit comprises a second operational amplifier (U2), a second resistor (R3) and a bias resistor (R4), wherein the second resistor (R3) is connected between the reverse input end and the output end of the second operational amplifier (U2), one end of the bias resistor (R4) is connected with the positive input end of the second operational amplifier (U2), and the other end of the bias resistor is grounded;
The reference voltage of the first operational amplifier is half the reference voltage of the second operational amplifier.
2. The circuit according to claim 1, wherein the control unit comprises an FPGA or an ARM or a DSP or an MCU.
3. The circuit of claim 1, wherein the circuit further comprises: and the voltage stabilizing circuit is connected with the output end of the first amplifying circuit and the input end of the analog-digital conversion unit.
4. The circuit of claim 3, wherein the voltage stabilizing circuit comprises: the capacitor comprises a third resistor (R5), a fourth resistor (R6) and a capacitor (C1), wherein one end of the fourth resistor (R6) is connected with one end of the capacitor (C1) in series, and two ends of the third resistor (R5) are respectively connected with the other end of the fourth resistor (R6) and the other end of the capacitor (C1).
5. The circuit of claim 4, wherein the circuit further comprises: and one end of the fifth resistor (R7) is connected with the output end of the digital-to-analog conversion unit, and the other end of the fifth resistor (R7) is connected with the reverse input end of the second amplifying circuit.
6. A signal conditioning method for a signal conditioning circuit according to any of claims 1-5, comprising:
the control unit adjusts the output current of the digital-to-analog conversion unit to counteract the current change of the input end of the first amplifying circuit, and the adjusting formula is as follows:
Ifb＝(Vo2-Vi)/R0
wherein Ifb is the output current, vo2 is the output voltage of the second amplifying circuit, vi is the input voltage of the inverting input terminal of the first amplifying circuit, and R0 is the feedback resistor.
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