CN116325145A - 用于无源组件与裸片关键距离减少的封装结构 - Google Patents
用于无源组件与裸片关键距离减少的封装结构 Download PDFInfo
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- CN116325145A CN116325145A CN202180067660.XA CN202180067660A CN116325145A CN 116325145 A CN116325145 A CN 116325145A CN 202180067660 A CN202180067660 A CN 202180067660A CN 116325145 A CN116325145 A CN 116325145A
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Abstract
公开了一种封装及其制造方法。封装包括:衬底,其具有包括数目为N的金属化层的第一区域和包括数目为M的金属化层的第二区域,其中M小于N;位于衬底的第一表面上的第二区域内的无源组件;以及位于衬底的第二表面上的第二区域内的裸片,衬底的第二表面与衬底的第一表面相对,裸片通过第二区域内的数目为M的金属化层中的至少一个金属化层电耦合到无源组件。
Description
相关申请的交叉引用
本专利申请要求2020年10月27日提交的、题目为“PACKAGE STRUCTURE FORPASSIVE COMPONENT TO DIE CRITICAL DISTANCE REDUCTION”的美国非临时申请号17/081340的权益,该申请被转让给本申请的受让人,并且通过引用以其整体明确并入本文。
技术领域
本公开总体涉及封装设备,并且更具体地但不排他地涉及用于无源组件与裸片关键距离减少的封装结构及其制造技术。
背景技术
集成电路技术通过有源组件的小型化在提高计算能力方面取得了长足进步。对速度更快、功能更强、性能更高但封装尺寸越来越小的芯片组有持续的需求。一种封装解决方案是使用所谓的“倒装芯片”设备,其中芯片焊垫侧朝下直接安装到衬底上,而不是安装在使用引线键合进行电气连接的封装中。
关键距离是指代有源设备的端子与电耦合到有源设备的端子的无源组件的端子之间的距离的术语。将关键距离最小化是有益的,因为这样做可以减少环路电感和寄生电容,这改进了性能。
图1图示了基于层压衬底102的这种常规封装100,倒装芯片设备、裸片104已经经由常规方法被安装在层压衬底102上,常规方法涉及裸片104上的裸片凸块和层压衬底102上的键合垫。无源组件106(诸如线路侧电容器(LSC))被安装得尽可能靠近裸片104,以便保持寄生电容和电感较低,以避免限制设备的操作的频率、使设备之间的信号失真,以及由寄生引起的其他损害。为此,裸片104和用于该裸片的无源组件106通常被安装在相同层压衬底102的相对侧上。这允许无源组件106与裸片104以从裸片104到层压衬底102的电连接的厚度、层压衬底102的厚度以及从层压衬底102到无源组件106的电连接的厚度的总和进行分离。裸片104和无源组件106之间的该总距离被称为关键距离。对于常规封装100,这些距离分别是用于将裸片104连接到层压衬底102的裸片凸块的40μm、用于衬底102的120μm、和用于层压衬底102与无源组件106之间的焊料连接的30μm,这产生大约200μm的关键距离。
图2图示了被称为扇出晶片级封装(FO-WLP)的另一种常规封装200,其中多个重分布层202(通常是堆叠中的三层或更多层)被构建在无凸块裸片204之上,无源组件106使用焊料接点被安装到多个重分布层202。这里,关键距离是从裸片204到重分布层202的电连接的厚度(实际上为零)、重分布层202的堆叠的厚度(通常为50μm)、和从重分布层202到无源组件106的电连接的厚度(通常为30μm)的总和,即大约80μm。
然而,随着芯片组速度继续增加,关键距离将继续是限制性能和贡献功耗的制约因素。因此,对克服常规封装(受大关键距离限制)的缺陷的方法、系统和装置存在需求。
发明内容
以下呈现与一个或多个方面和/或示例有关的简化概述,该一个或多个方面和/或示例与本文公开的装置和方法相关联。如此,以下概述不应当被视为与所有预期的方面和/或示例有关的详尽纵览,以下概述也不应当被认为标识与所有预期的方面和/或示例有关的关键或重要元素,或描绘与任何特定方面和/或示例相关联的范围。相应地,以下概述仅具有在下面呈现的详细描述之前,以简化形式呈现与关于本文公开的装置和方法的一个或多个方面和/或示例有关的某些概念的目的。
根据本文公开的各个方面,至少一个方面包括一种封装,封装包括:衬底,具有第一区域和第二区域,第一区域具有数目为N的金属化层,第二区域具有数目为M的金属化层,其中M小于N;被设置在衬底的第一表面上的第二区域内的无源组件;被设置在衬底的第二表面上的第二区域内的裸片,衬底的第二表面与衬底的第一表面相对,裸片通过第二区域内的数目为M的金属化层中的至少一个金属化层电耦合到无源组件。
根据本文公开的各个方面,至少一个方面包括一种用于制造封装的方法,方法包括:提供衬底,衬底具有第一区域和第二区域,第一区域具有数目为N的金属化层,第二区域具有数目为M的金属化层,其中M小于N;提供被设置在衬底的第一表面上的第二区域内的无源组件;以及提供被设置在衬底的第二表面上的第二区域内的裸片,衬底的第二表面与衬底的第一表面相对,裸片通过第二区域内的数目为M的金属化层中的至少一个金属化层电耦合到无源组件。
基于附图和详细描述,与本文公开的装置和方法相关联的其他特征和优点对于本领域技术人员将是明显的。
附图说明
对本公开的方面及其许多伴随优点的更完整理解将因其在参考结合附图考虑的以下详细描述时变得更好理解而易于获得,其中相同的附图标记表示相同的部件,附图仅出于图示目的被呈现,而不是对本公开的限制。
图1图示了一种常规封装;
图2图示了另一种常规封装;
图3图示了根据本公开的一个或多个方面的示例性封装;
图4图示了根据本公开的一个或多个方面的用于制造封装的示例性部分方法的流程图;
图5A至图5C图示了根据本公开的一个或多个方面的制造技术;
图6图示了根据本公开的一个或多个方面的示例性移动设备;以及
图7图示了根据本公开的一个或多个方面的可以与上述集成设备或半导体设备中的任一个集成的各种电子设备。
根据惯例,由附图描绘的特征可以未按比例绘制。因此,为了清楚起见,可以任意扩大或缩小所描绘特征的尺寸。根据惯例,为了清楚起见,附图中的一些附图被简化。因此,附图可以未描绘特定装置或方法的所有组件。此外,贯穿说明书和附图,相同的附图标记表示相同的特征。
具体实施方式
在针对特定实施例的以下描述和相关附图中说明了本公开的方面。在不脱离本文教导的范围的情况下,可以设计备选方面或实施例。此外,本文的说明性实施例的众所周知的元素可能未被详细描述或可能被省略,以免混淆本公开中教导的相关细节。
在某些描述的示例实施方式中,标识了其中各种组件结构和操作部分可以从已知的常规技术取得并且随后根据一个或多个示例性实施例进行布置的实例。在这种实例中,已知的常规组件结构和/或操作部分的内部细节可以被省略,以帮助避免对本文公开的说明性实施例中图示的概念的潜在混淆。
本文使用的术语仅用于描述特定实施例的目的,并不旨在进行限制。如本文所使用的,单数形式“一”、“一个”和“该”也旨在包括复数形式,除非上下文另有明确指示。将进一步理解,术语“包括”、“包含”、“具有”和/或“含有”在本文中使用时指定所陈述的特征、整数、步骤、操作、元素和/或组件的存在,但不排除一个或多个其他特征、整数、步骤、操作、元素、组件和/或它们的组的存在或添加。
为了解决常规封装的缺陷,特别是为了减小有源设备(例如裸片)和与该裸片相关联的无源组件之间的关键距离,本公开提出了一种改进的封装,其使用连接有源组件和无源组件所需的最小层数目,这使得有源组件和无源组件之间的封装的厚度被最小化,而封装的其他部分使用更多层,并且因此更厚。本公开还提出了一种制造这种改进封装的过程:过程包括在无源组件端子上构建层,从而避免了对与无源组件的焊料接点连接的需要。其余层被构建为与无源组件相邻,这利用了与无源组件相邻的3D空间。这给出了结构的派生优势,例如整体封装高度减少。此外,使用裸片-晶片附接过程来将裸片附接到改进的封装,与常规的倒装芯片附接(例如,~40um)相比,这导致小得多的间隔高度(例如,~5um)。这些技术的组合导致结构具有~20um的关键距离,这比常规封装解决方案小4倍。
图3图示了根据本公开的一个或多个方面的示例性封装。在图3中,封装300包括衬底302,衬底302具有包括数目为N的金属化层的第一区域304,以及包括数目为M的金属化层303的第二区域306,其中M小于N。在一些方面,衬底302包括由一个或多个电介质层(未具体图示)分离的一个或多个金属化层303。金属化层303可以被配置为迹线、垫等。金属化层303可以通过一个或多个通孔彼此耦合和/或耦合到外部连接。在一些方面,金属化层303可以被配置为重分布层(RDL)以对信号、功率等进行重分布。封装300还包括无源组件308,无源组件308被定位在第二区域306内并且在衬底302的第一表面上。在图3中,无源组件308在衬底302的底表面上,如该图中所定向的。封装300还包括裸片310,裸片310被定位在第二区域306内并且在衬底302的与衬底302的第一表面相对的第二表面上。在图3中,裸片310在衬底302的顶表面上,如该图中所定向的。无源组件308和裸片310通过第二区域306内的数目为M的金属化层303中的至少一个金属化层彼此电耦合。如图3中所示,第一区域304具有第一厚度T1,并且第二区域306具有小于T1的第二厚度T2。因此,在图3中,无源组件308和裸片310之间的关键距离是T2。
根据一些方面,第二区域306内的金属化层303的数目M是1,在该情况下,第一区域304内的金属化层303的数目N是2或更多。根据一些方面,第二区域306内的金属化层303的数目M大于1,在该情况下,第一区域304内的金属化层303的数目N大于2。根据一些方面,裸片310使用裸片-晶片连接(不使用焊料接点)被电耦合到封装300。根据一些方面,裸片310是倒装芯片封装的一部分。根据一些方面,无源组件308是线路侧组件,诸如线路侧电容器、电阻器、或电感器。根据一些实施例,金属化层303使用铜导体。根据一些实施例,衬底302由预浸料(PPG)制成。
封装300提供包括但不限于以下内容的几个技术优势。通过制造具有减少数目的金属化层303的区域(裸片310及其对应的无源组件308被定位在该区域中),裸片310和无源组件308之间的关键距离被极大地减小。在一个示例中,与常规封装相比,关键距离小四倍,即封装300为20μm,常规扇出晶片级封装(FO-WLP)为80μm。因为组件(裸片310或无源组件308)被定位在衬底302的较薄的嵌入区域上,所以与没有嵌入区域的常规封装相比,封装300的总高度潜在地减少。此外,第二区域306中的层数目M可以仅仅是在裸片310和无源组件308之间进行必要连接所需的最少层数,层数目M可以少至1。此外,因为裸片310最后被附接,如下面将更详细描述的,封装产量可以增加。
图4图示了根据本公开的一些示例的用于制造封装的示例性部分方法700的流程图。如图4中所示,部分方法400可以开始于框402,提供具有第一区域304和第二区域306的衬底302,第一区域304具有数目为N的金属化层,第二区域306具有数目为M的金属化层,其中M小于N。部分方法400可以在框404中继续,提供被定位在第二区域306内并且在衬底302的第一表面上的无源组件308。部分方法400可以在框406中继续,提供被定位在第二区域306内并且在衬底302的与衬底302的第一表面相对的第二表面上的裸片310,其中无源组件308和裸片310通过衬底302的第二区域306中的数目为M的金属化层中的至少一个金属化层彼此电耦合。应当理解,在M=1的情况下,无源组件308将使用单个金属化层电耦合到裸片310。还应当理解,在M>1的情况下,无源组件308可以使用衬底302的第二区域306内可用的金属化层中的任何一个或多个金属化层电耦合到裸片310。
图5A至图5C图示了根据本公开的一个或多个方面的制造技术。参考图5A,在部分过程500的部分(i)中,提供第一载体501。在过程部分(ii)中,在第一载体501上方提供粘合层504。在过程部分(iii)中,在粘合层504上方提供第一组件侧光成像电介质(PID)506。在过程部分(iv)中,例如使用光刻过程在第一组件侧PID 506中产生开口,包括但不限于涉及光致抗蚀剂层压或涂覆、紫外(UV)光曝光、显影步骤等的常规光刻过程。在过程部分(v)中,在第一组件侧PID 506上产生第一层导体508。这些第一层导体508可以是例如金属层或金属化层,并且可以使用金、银、铜、铝或其他导电材料形成。在过程部分(vi)中,产生第二组件侧PID 510,第二组件侧PID 510在第一层导体508上方并且覆盖第一层导体508。在过程部分(vii)中,在第二组件侧PID 510中产生开口。在过程部分(viii)中,产生附加金属化结构(512),诸如通孔和附加金属层。
在过程部分(ix)中,产生第三组件侧PID 514。在过程部分(x)中,在第三组件侧PID 514中产生开口。在过程部分(xi)中,在第三组件侧PID 514上并且穿过第三组件侧PID514产生第二层导体516。这些第二层导体516可以是例如金属层或金属化层,并且可以使用金、银、铜、铝或其他导电材料形成。在过程部分(xii)中,将焊球518安装到第二层导体516中的至少一些第二层导体。在过程部分(xiii)中,将无源组件520放置在现在暴露的粘合层504的一部分上,即,在载体的未被第一层导体508或第二层导体516覆盖的部分中。在过程部分(xiv)中,施加临时键合膜522,覆盖结构(例如,焊球518和无源组件520)并且提供平面顶表面。部分过程500在图5B中继续。
现在参考图5B,在过程部分(xv)中,将第二载体524附接到临时键合膜522。在过程部分(xvi)中,将现有的组装件翻转。在过程部分(xvii)中,去除第一载体501和粘合层504,暴露第一组件侧PID 506。在过程部分(xviii)中,在第一组件侧PID 506中产生用于前侧金属化层的开口。在过程部分(xix)中,产生电耦合到无源组件520的第一前侧金属化层526。
在过程部分(xx)中,在第一前侧金属化层526之上产生第一裸片侧PID 528。在过程部分(xxi)中,在第一裸片侧PID 528中产生开口,暴露第一前侧金属化层526。在过程部分(xxii)中,产生电耦合到第一前侧金属化层526的第二前侧金属化层530。在过程部分(xxiii)中,在第二前侧金属化层530之上产生第二裸片侧PID 532,并且在第二裸片侧PID532中产生开口,以用于裸片附接的铜柱镀覆。在过程部分(xxiv)中,产生用于裸片-晶片附接的封装侧铜柱534。部分过程500在图5C中继续。
现在参考图5C,在过程步骤(xxv)中,将具有氧化物层538和裸片侧铜柱540的裸片536附接到封装组装件,使得裸片侧铜柱540电耦合到封装侧铜柱534。在过程步骤(xxvi)中,根据一些方面,裸片-晶片附接过程涉及在150摄氏度-250摄氏度处固化封装-裸片组装件,这使得氧化物层538与第二裸片侧PID 532共价键合,并且引起封装侧铜柱534和裸片侧铜柱540之间的金属扩散。在过程步骤(xxvii)中,去除第二载体524和临时键合膜522。以该方式,与常规封装解决方案相比,可以制造具有更小关键距离(CD)的封装500(类似于封装300),封装500包括裸片536和在衬底502(包括金属化层503)中形成的凹槽中的无源组件520。
应当理解,前述制造过程仅作为本公开的方面中的一些方面的一般说明而被提供,并且不旨在限制本公开或所附权利要求。此外,本领域技术人员已知的制造过程中的许多细节可能已被省略或被组合在概要过程部分中,以有助于所公开的各个方面的理解,而无需详细再现每个细节和/或所有可能的过程变化。
图6图示了根据本公开的一些示例的示例性移动设备。现在参考图6,根据示例性方面配置的移动设备的框图被描绘并且通常被指定为移动设备600。在一些方面中,移动设备600可以被配置为无线通信设备。如所示的,移动设备600包括处理器602。处理器602被示为包括本领域公知的指令管线604、缓冲器处理单元(BPU)606、分支指令队列(BIQ)608和节流器610。为了清楚起见,从处理器602的该视图中省略了这些块的其他公知的细节(例如,计数器、条目、置信字段、加权和、比较器等)。处理器602可以通过链路通信耦合到存储器612,该链路可以是裸片到裸片或芯片到芯片的链路。移动设备600还包括显示器614和显示器控制器616,其中显示器控制器616耦合到处理器602和显示器614。
在一些方面,图6可以包括:耦合到处理器602的编码器/解码器(CODEC)618(例如,音频和/或语音CODEC);耦合到CODEC 618的扬声器620和麦克风622;以及耦合到无线天线626和处理器602的无线控制器电路624(其可以包括调制解调器、射频(RF)电路装置、滤波器等,其可以使用一个或多个倒装芯片设备来被实现,如本文所公开的)。
在存在上述框中的一个或多个框的特定方面中,处理器602、显示控制器616、存储器612、CODEC 618和无线控制器电路624可以被包括在系统级封装或片上系统设备(包括但不限于封装300)中,系统级封装或片上系统设备可以全部或部分地使用本文公开的技术来被实现。输入设备628(例如,物理或虚拟键盘)、电源630(例如,电池)、显示器614、输入设备628、扬声器620、麦克风622、无线天线626和电源630可以在片上系统设备外部,并且可以耦合到片上系统设备的诸如接口或控制器的组件。
应当注意,虽然图6描绘了移动设备,但是处理器602和存储器612也可以被集成到机顶盒、音乐播放器、视频播放器、娱乐单元、导航设备、个人数字助理(PDA)、固定位置数据单元、计算机、膝上型计算机、平板计算机、通信设备、移动电话或其他类似的设备中。
图7图示了根据本公开的各种示例的可以与前述集成设备或半导体设备中的任一个集成的各种电子设备。例如,移动电话设备702、膝上型计算机设备704和固定位置终端设备706各自可以被视为一般用户设备(UE)并且可以包括例如本文描述的封装300。例如,封装300可以是本文描述的集成电路、裸片、集成设备、集成设备封装、集成电路设备、设备封装、集成电路(IC)封装、层叠封装设备中的任一个。图7中图示的移动电话设备702、膝上型计算机设备704和固定位置终端设备706仅仅是示例性的。其他电子设备也可以是特征设备,包括但不限于设备(例如,电子设备)的组,设备包括移动设备、手持个人通信系统(PCS)单元、便携式数据单元(诸如个人数字助理)、使能全球定位系统(GPS)的设备、导航设备、机顶盒、音乐播放器、视频播放器、娱乐单元、固定位置数据单元(诸如仪表读取装备)、通信设备、智能电话、平板计算机、计算机、可穿戴设备、服务器、路由器、机动车交通工具(例如,自动交通工具)中实现的电子设备、物联网(IoT)设备,或存储或取回数据或计算机指令的任何其他设备,或其任何组合。
前面公开的封装、设备和功能可以被设计和配置成存储在计算机可读介质上的计算机文件(例如,RTL、GDSII、Gerber等)。一些或所有这种文件可以被提供给基于这种文件制造设备的制造处理者。所得产品可以包括半导体晶片,半导体晶片然后被切割成半导体裸片,并且被封装成倒装芯片或其他封装。然后可以在本文所述的设备中采用该封装。
应当理解,本文公开的各个方面可以被描述为本领域技术人员描述和/或认识的结构、材料和/或设备的功能等同物。例如,在一个方面,装置可以包括用于执行上述各种功能的部件。应当理解,前述方面仅作为示例被提供,并且要求保护的各个方面不限于作为示例引用的特定附图标记和/或说明。
图1-图7中所示的组件、过程、特征和/或功能中的一个或多个可以被重新设置和/或被组合成单个组件、过程、特征或功能,或者被并入在数个组件、过程、或功能中。在不脱离本公开的情况下,还可以添加附加的元素、组件、过程和/或功能。还应当注意,本公开中的图1-图7以及对应的描述不限于裸片和/或IC。在一些实施方式中,图1-图7及其对应的描述可以用于制造、产生、提供和/或生产集成设备。在一些实施方式中,设备可以包括裸片、集成设备、裸片封装、集成电路(IC)、设备封装、集成电路(IC)封装、晶片、半导体设备、层叠封装(PoP)设备和/或中介器。
如本文所使用的,术语“用户装备”(或“UE”)、“用户设备”、“用户终端”、“客户端设备”、“通信设备”、“无线设备”、“无线通信设备”、“手持式设备”、“移动设备”、“移动终端”、“移动站”、“手机”、“接入终端”、“订户设备”、“订户终端”、“订户站”、“终端”以及其变型可以互换地指代可以接收无线通信和/或导航信号的任何合适的移动或固定设备。这些术语包括但不限于音乐播放器、视频播放器、娱乐单元、导航设备、通信设备、智能电话、个人数字助理、固定位置终端、平板计算机、计算机、可穿戴设备、膝上型计算机、服务器、机动车交通工具中的机动车设备,和/或通常由人携带和/或具有通信能力(例如,无线、蜂窝、红外、短范围无线电等)的其他类型的便携式电子设备。这些术语还旨在包括与另一设备通信的设备,该另一设备可以诸如通过短距离无线、红外、有线连接或其他连接来接收无线通信和/或导航信号,无论是在该设备还是在其他设备处出现卫星信号接收、辅助数据接收,和/或与位置有关的处理。此外,这些术语旨在包括所有设备,包括无线和有线通信设备,它们能够经由无线电接入网络(RAN)与核心网络进行通信,并且UE可以通过核心网络与诸如因特网的外部网络连接,以及与其他UE连接。当然,对于UE来说,连接到核心网络和/或因特网的其他机制也是可能的,诸如通过有线接入网络、无线局域网(WLAN)(例如,基于IEEE802.11等),等等。UE可以由多种类型的设备中的任何一种来实施,包括但不限于印刷电路(PC)卡、紧凑型闪存设备、外部或内部调制解调器、无线或有线电话、智能电话、平板、追踪设备、资产标签等等。UE可以通过其向RAN发送信号的通信链路被称为上行链路信道(例如,反向流量信道、反向控制信道、接入信道等)。RAN可以通过其向UE发送信号的通信链路被称为下行链路或前向链路信道(例如,寻呼信道、控制信道、广播信道、前向流量信道等)。如本文所使用的,术语流量信道(TCH)可以指代上行链路/反向或下行链路/前向流量信道。
电子设备之间的无线通信可以是基于不同的技术,诸如码分多址(CDMA)、宽带CDMA(W-CDMA)、时分多址(TDMA)、频分多址(FDMA))、正交频分复用(OFDM)、全球移动通信系统(GSM)、第三代合作伙伴计划(3GPP)长期演进(LTE)、第五代(5G)新无线电(NR)、蓝牙(BT)、蓝牙低功耗(BLE)、IEEE 802.11(WiFi)和IEEE 802.15.4(Zigbee/Thread)或可以用于无线通信网络或数据通信网络的其他协议。蓝牙低功耗(也被称为蓝牙LE(BLE)和蓝牙智能)是一种由蓝牙特别兴趣小组设计和销售的无线个人区域网络技术,旨在维持类似通信范围的同时,显著降低功耗和成本。在2010年,随着蓝牙核心规范版本4.0的采用和蓝牙5的更新,BLE被合并到主要的蓝牙标准中。
词语“示例性”在本文中用于表示“用作示例、实例或说明”。本文描述为“示例性”的任何细节不应当被解释为优于其他示例。同样,术语“示例”不意味着所有示例都包括所讨论的特征、优势或操作模式。此外,特定特征和/或结构可以与一个或多个其他特征和/或结构组合。此外,在此描述的装置的至少一部分可以被配置成执行在此描述的方法的至少一部分。
应当注意,术语“连接”、“耦合”或其任何变型意指元件之间的任何直接或间接的连接或耦合,并且可以涵盖中间元件在两个元件之间的存在(该两个元件经由中间元件“连接”或“耦合”在一起),除非连接被明确地公开为直接连接。
本文对使用诸如“第一”、“第二”等名称的元素的任何引用不限制这些元素的数目和/或顺序。相反,这些名称被用作区分两个以上元素和/或多个元素实例的便利方法。此外,除非另有说明,元素的集合可以包括一个或多个元素。
本领域技术人员将理解,可以使用各种不同技术和技艺中的任一种来表示信息和信号。例如,贯穿上述描述可能被引用的数据、指令、命令、信息、信号、位、符号和码片可以由电压、电流、电磁波、磁场或粒子、光场或粒子、或其任何组合表示。
本申请中的任何陈述或图示都不旨在将任何组件、动作、特征、利益、优势或等效物献给公众,无论该组件、动作、特征、利益、优势或等效物是否被记载在权利要求书中。
此外,本领域技术人员应当理解,结合本文公开的示例描述的各种说明性逻辑块、模块、电路和算法动作可以被实现为电子硬件、计算机软件或两者的组合。为了清楚地说明硬件和软件的这种可互换性,各种说明性组件、块、模块、电路和动作在上面根据其功能被一般化描述。这种功能性被实现为硬件还是软件取决于特定应用和施加在整体系统上的设计约束。技术人员可以针对每个特定应用以不同方式实现所描述的功能,但是这种实现决定不应当被解释为导致偏离本公开的范围。
虽然已经结合设备描述了一些方面,但毋庸置疑,这些方面也构成了对应方法的描述,因此设备的块或组件也应当被理解为对应的方法动作,或者被理解为方法动作的特征。与之类似地,结合方法动作或作为方法动作描述的方面也构成对应设备的对应块或细节或特征的描述。一些或所有方法动作可以由硬件装置(或使用硬件装置)执行,例如,诸如微处理器、可编程计算机或电子电路。在一些示例中,一些或多个最重要的方法动作可以由这种装置执行。
在上面的详细描述中可以看出,不同的特征在示例中被组合在一起。这种公开方式不应当被理解为所要求保护的示例具有比相应权利要求中明确提及的特征更多的特征的意图。相反,本公开可以包括少于所公开的个体示例的所有特征。因此,所附权利要求应当视为被包含在描述中,其中每个权利要求本身可以作为单独示例。虽然每个权利要求本身可以作为单独示例,但应当注意,尽管权利要求中的从属权利要求可以引用具有一个或多个权利要求的具体组合,但其他示例也可以涵盖或包括所述从属权利要求与任何其他从属权利要求的主题内容的组合,或任何特征与其他从属和独立权利要求的组合。这种组合在本文被提出,除非明确表达不想要特定的组合。此外,还旨在使权利要求的特征可以被包括在任何其他独立权利要求中,即使所述权利要求不直接从属于该独立权利要求。
还应当注意,描述或权利要求中公开的方法、系统和装置可以由包括用于执行所公开方法的相应动作和/或功能的部件的设备来实现。
此外,在一些示例中,单个动作可以被细分为多个子动作或包含多个子动作。这种子动作可以被包含在单个动作的公开中,并且是单个动作的公开的一部分。
虽然前述公开示出了本公开的说明性示例,但是应当注意,在不脱离如由所附权利要求限定的本公开的范围的情况下,可以在本文中进行各种改变和修改。根据本文描述的公开的示例的方法权利要求的功能和/或动作不需要以任何特定顺序执行。此外,公知的要素将不被详细描述或可以被省略,以免混淆本文公开的方面和示例的相关细节。此外,尽管可能以单数形式描述或要求保护本公开的要素,但复数形式是所预期的,除非明确声明限制为单数。
Claims (22)
1.一种封装,包括:
衬底,具有第一区域和第二区域,所述第一区域包括数目为N的金属化层,所述第二区域包括数目为M的金属化层,其中M小于N;
无源组件,被设置在所述衬底的第一表面上的所述第二区域内;以及
裸片,被设置在所述衬底的第二表面上的所述第二区域内,所述衬底的所述第二表面与所述衬底的所述第一表面相对,所述裸片通过所述第二区域内的所述数目为M的金属化层中的至少一个金属化层电耦合到所述无源组件。
2.根据权利要求1所述的封装,其中所述第一区域具有第一厚度T1,并且所述第二区域具有小于T1的第二厚度T2。
3.根据权利要求1所述的封装,其中M=1。
4.根据权利要求1所述的封装,其中M>1。
5.根据权利要求1所述的封装,其中所述裸片使用裸片-晶片连接被电耦合到所述封装。
6.根据权利要求1所述的封装,其中所述裸片是倒装芯片封装的一部分。
7.根据权利要求1所述的封装,其中所述无源组件包括线路侧组件。
8.根据权利要求7所述的封装,其中所述线路侧组件包括线路侧电容器、电阻器、或电感器。
9.根据权利要求1所述的封装,其中所述金属化层包括铜。
10.根据权利要求1所述的封装,其中所述衬底包括预浸料(PPG)。
11.根据权利要求1所述的封装,其中至少一个金属化层包括重分布层。
12.一种用于制造封装的方法,所述方法包括:
提供衬底,所述衬底具有第一区域和第二区域,所述第一区域包括数目为N的金属化层,所述第二区域包括数目为M的金属化层,其中M小于N;
提供被设置在所述衬底的第一表面上的所述第二区域内的无源组件;以及
提供被设置在所述衬底的第二表面上的所述第二区域内的裸片,所述衬底的所述第二表面与所述衬底的所述第一表面相对,所述裸片通过所述第二区域内的所述数目为M的金属化层中的至少一个金属化层电耦合到所述无源组件。
13.根据权利要求12所述的方法,其中所述第一区域具有第一厚度T1,并且所述第二区域具有小于T1的第二厚度T2。
14.根据权利要求12所述的方法,其中M=1。
15.根据权利要求12所述的方法,其中M>1。
16.根据权利要求12所述的方法,其中所述裸片使用裸片-晶片连接被电耦合到所述封装。
17.根据权利要求12所述的方法,其中所述裸片是倒装芯片封装的一部分。
18.根据权利要求12所述的方法,其中所述无源组件包括线路侧组件。
19.根据权利要求18所述的方法,其中所述线路侧组件包括线路侧电容器、电阻器、或电感器。
20.根据权利要求12所述的方法,其中所述金属化层包括铜。
21.根据权利要求12所述的方法,其中所述衬底包括预浸料(PPG)。
22.根据权利要求12所述的方法,其中至少一个金属化层包括重分布层。
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US17/081,340 US20220130741A1 (en) | 2020-10-27 | 2020-10-27 | Package structure for passive component to die critical distance reduction |
PCT/US2021/051784 WO2022093450A1 (en) | 2020-10-27 | 2021-09-23 | Package structure for passive component to die critical distance reduction |
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TWI247371B (en) * | 2004-02-06 | 2006-01-11 | Advanced Semiconductor Eng | Semiconductor package and method for manufacturing the same |
TWI303870B (en) * | 2005-12-30 | 2008-12-01 | Advanced Semiconductor Eng | Structure and mtehod for packaging a chip |
US20080128890A1 (en) * | 2006-11-30 | 2008-06-05 | Advanced Semiconductor Engineering, Inc. | Chip package and fabricating process thereof |
US20100073894A1 (en) * | 2008-09-22 | 2010-03-25 | Russell Mortensen | Coreless substrate, method of manufacturing same, and package for microelectronic device incorporating same |
US9305853B2 (en) * | 2013-08-30 | 2016-04-05 | Apple Inc. | Ultra fine pitch PoP coreless package |
US9660017B2 (en) * | 2015-01-20 | 2017-05-23 | Mediatek Inc. | Microelectronic package with surface mounted passive element |
KR101666757B1 (ko) * | 2015-07-13 | 2016-10-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
US10141288B2 (en) * | 2015-07-31 | 2018-11-27 | Taiwan Semiconductor Manufacturing Company, Ltd. | Surface mount device/integrated passive device on package or device structure and methods of forming |
US9601461B2 (en) * | 2015-08-12 | 2017-03-21 | Semtech Corporation | Semiconductor device and method of forming inverted pyramid cavity semiconductor package |
US11355427B2 (en) * | 2016-07-01 | 2022-06-07 | Intel Corporation | Device, method and system for providing recessed interconnect structures of a substrate |
JP6660850B2 (ja) * | 2016-08-05 | 2020-03-11 | 新光電気工業株式会社 | 電子部品内蔵基板及びその製造方法と電子部品装置 |
US10818635B2 (en) * | 2018-04-23 | 2020-10-27 | Deca Technologies Inc. | Fully molded semiconductor package for power devices and method of making the same |
US10879183B2 (en) * | 2018-06-22 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and method of manufacture |
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