CN116318340A - Satellite-borne multichannel multi-rate high-speed data interface system based on request link - Google Patents

Satellite-borne multichannel multi-rate high-speed data interface system based on request link Download PDF

Info

Publication number
CN116318340A
CN116318340A CN202310154263.7A CN202310154263A CN116318340A CN 116318340 A CN116318340 A CN 116318340A CN 202310154263 A CN202310154263 A CN 202310154263A CN 116318340 A CN116318340 A CN 116318340A
Authority
CN
China
Prior art keywords
fifo buffer
level
full
data
level fifo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202310154263.7A
Other languages
Chinese (zh)
Inventor
华璐
王瑞
李福�
张伟
王鸣涛
胡西阁
李召
张丹丹
王宇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Xian Institute of Space Radio Technology
Original Assignee
Xian Institute of Space Radio Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Xian Institute of Space Radio Technology filed Critical Xian Institute of Space Radio Technology
Priority to CN202310154263.7A priority Critical patent/CN116318340A/en
Publication of CN116318340A publication Critical patent/CN116318340A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/185—Space-based or airborne stations; Stations for satellite systems
    • H04B7/18578—Satellite systems for providing broadband data service to individual earth stations
    • H04B7/18586—Arrangements for data transporting, e.g. for an end to end data transport or check
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/065—Partitioned buffers, e.g. allowing multiple independent queues, bidirectional FIFO's
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3018—Input queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/30—Peripheral units, e.g. input or output ports
    • H04L49/3027—Output queuing
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The application relates to a request link-based satellite-borne multichannel multi-rate high-speed data interface system, which comprises: the first-level FIFO buffer memory is used for transmitting data to the second-level FIFO buffer memories in a time division mode, each time slot corresponds to one second-level FIFO buffer memory, and whether to write data to each second-level FIFO buffer memory is determined according to the full state of each second-level FIFO buffer memory in each time slot. According to the method and the device, under a request link, two-stage FIFO caches are used for data caching, and the mode that all second-stage FIFO caches are full is detected in a time-sharing mode through the state detection module, so that the functions of channel forwarding, baseband processing, digital-to-analog conversion and the like of single-channel input data are realized, and the integration level of the satellite-borne data transmission system is improved.

Description

Satellite-borne multichannel multi-rate high-speed data interface system based on request link
Technical Field
The application relates to the technical field of satellite data processing and transmission, in particular to a satellite-borne multichannel multi-rate high-speed data interface system based on a request link.
Background
The satellite-borne baseband data interface typically employs a high-speed serial interface: for example, CXP, optical fiber interface, etc., the input rate of single channel can reach more than 10Gbps, and the wireless transmission channel is constrained by conditions such as link, bandwidth, etc., and single channel can not transmit such high rate, and multiple wireless channels are required to transmit in parallel. The traditional design is that each channel corresponds to different data transmission single machines, so each channel is provided with an independent software and hardware data input and output interface, a baseband data processing module, a digital-to-analog conversion module and the like.
With the development of high-speed data transmission technology, satellites gradually tend to be miniaturized and integrated, and functions such as baseband data processing, data channel distribution, digital-analog conversion and the like need to be realized in a single machine. Because the back-end high-speed DA device requires a fixed phase and frequency relationship between the data input to the high-speed DA device and the sampling clock, the frequency division clock of the high-speed DA device is required to be used as a main clock for data processing. In order to ensure the reliability and stability of multi-channel data transmission, the corresponding DA devices of each channel work independently, and different crystal oscillators can be used for generating DA sampling clocks to sample baseband data.
Assuming that the input data is in the clk clock domain, the lane 1 data clock is in the clk_td1 clock domain, the lane 2 data clock is in the clk_td2 clock domain, and so on; thus, the data channel distribution module involves multiple clock domain relationships, with cross-clock domain data processing. In the prior art, a data processing method of a complementary blank frame is adopted, when the system is designed, the input rate is smaller than the sum of all channel rates, the data is distributed to each channel in a parity framing mode, and under the condition of insufficient rate, the blank frame is used for ensuring that the data link of each channel is uninterrupted. And each channel is always downloaded at the same data rate, so that the channels cannot work completely independently.
Disclosure of Invention
To overcome at least one of the deficiencies in the prior art, embodiments of the present application provide a request link based on-board multichannel multi-rate high speed data interface system.
In a first aspect, there is provided a request link based on-board multichannel multi-rate high speed data interface system, comprising: the first-level FIFO buffer memory is used for transmitting data to the second-level FIFO buffer memories in a time division mode, each time slot corresponds to one second-level FIFO buffer memory, and whether to write data to each second-level FIFO buffer memory is determined according to the full state of each second-level FIFO buffer memory in each time slot.
In one embodiment, the system further comprises a state detection module and a channel selection module, wherein the state detection module is used for acquiring the full state of each second-level FIFO buffer, and the channel selection module is used for writing the read data into the second-level FIFO buffer by the first-level FIFO buffer when the full state of the second-level FIFO buffer is at a low level.
In one embodiment, when n is not less than 1 and not more than m-1, m is the total number of the second-level FIFO buffers, and n is the sequence number of the second-level FIFO buffers; the state detection module judges the full mark prog_full_n of the nth second-level FIFO buffer FIFO_n, if the full mark prog_full_n is low level, the first-level FIFO buffer reading enabling is effective M clock cycles, and the channel selection module writes the read data into the nth second-level FIFO buffer FIFO_n by the first-level FIFO buffer; after Nn reading clock cycles, the state detection module judges the full mark prog_full_n+1 of the (n+1) th second-level FIFO buffer FIFO_n+1;
if the full mark prog_full_n is high level, the first-level FIFO buffer memory read enable is invalid for Nn clock cycles, and after Nn read clock cycles, the state detection module judges the full mark prog_full_n+1 of the n+1th second-level FIFO buffer memory FIFO_n+1;
when n=m, the state detection module judges the full flag prog_full_n of the n second-level FIFO buffer FIFO_n, if the full flag prog_full_n is low, the first-level FIFO buffer is enabled to be effective for M clock cycles, and the channel selection module writes the read data into the n second-level FIFO buffer FIFO_n by the first-level FIFO buffer; after Nn reading clock cycles, the state detection module judges the full mark prog_full_1 of the 1 st second-level FIFO buffer FIFO_1;
if the full flag prog_full_n is high, the first-level FIFO buffer read enable is invalid for Nn clock cycles, and after Nn read clock cycles, the state detection module determines that the full flag prog_full_1 of the 1 st second-level FIFO buffer fifo_1 is to be processed.
In one embodiment, the decision threshold to be full flag and the buffer depth of each second level FIFO buffer satisfy the following relationship:
the decision threshold of the full flag should be at least M data spaces from the buffer depth, where M is the number of bytes of the data frame.
In one embodiment, the first-level FIFO buffer reads data at a rate greater than the sum of the rates at which the respective second-level FIFO buffers output data.
In one embodiment, the system further comprises a data request module, the data request module judges and processes the full mark of the first-level FIFO buffer memory, and if the full mark of the first-level FIFO buffer memory is low level, the data request module sends a request number signal to the front-end equipment, and valid data starts to be downloaded; if the full flag of the first-level FIFO buffer is high, the data request module stops sending the request number signal to the front-end device, and the valid data will stop being downloaded.
In one embodiment, the head-end equipment, upon receiving the request element signal, responds with a maximum effective data rate greater than the maximum line rate between the first level FIFO buffer and the second level FIFO buffer.
Compared with the prior art, the application has the following beneficial effects:
(1) According to the method and the device, under a request link, two-stage FIFO caches are used for data caching, and the mode that all second-stage FIFO caches are full is detected in a time-sharing mode through the state detection module, so that the functions of channel forwarding, baseband processing, digital-to-analog conversion and the like of single-channel input data are realized, and the integration level of the satellite-borne data transmission system is improved.
(2) According to the method and the device, under a request link, the mode that the state detection module detects the full mark of each second-level FIFO buffer memory in a time-sharing mode is adopted, so that the rate of each channel is irrelevant, the configuration can be independently carried out, and the use flexibility of the satellite-borne data transmission system is improved.
(3) According to the method and the device, the insertion of the empty frame data is avoided in the mode of requesting the number of elements, and the transmission efficiency of the effective data is improved.
Drawings
The present application may be better understood by reference to the following description taken in conjunction with the accompanying drawings, which are incorporated in and form a part of this specification, together with the following detailed description. In the drawings:
fig. 1 shows a block diagram of a request link based on-board multichannel multi-rate high speed digital transmission interface system according to an embodiment of the present application.
Detailed Description
Exemplary embodiments of the present application will be described hereinafter with reference to the accompanying drawings. In the interest of clarity and conciseness, not all features of an actual embodiment are described in the specification. It will of course be appreciated that in the development of any such actual embodiment, numerous implementation-specific decisions may be made to achieve the developers' specific goals, and that these decisions may vary from one implementation to another.
It should be noted that, in order to avoid obscuring the present application with unnecessary details, only the device structures closely related to the solution according to the present application are shown in the drawings, and other details not greatly related to the present application are omitted.
It is to be understood that the present application is not limited to the described embodiments due to the following description with reference to the drawings. In this context, embodiments may be combined with each other, features replaced or borrowed between different embodiments, one or more features omitted in one embodiment, where possible.
In order to improve the integration level of a single machine, the input data of a single interface needs to be reasonably distributed to each channel, and meanwhile, uninterrupted transmission and transmission efficiency are ensured. Fig. 1 shows a request link based on-board multichannel multi-rate high-speed data interface system, where the system performs two-level FIFO buffers on input data, the first-level FIFO buffer corresponds to an input interface, the plurality of second-level FIFO buffers corresponds to a plurality of channels, the first-level FIFO buffer transmits data to the plurality of second-level FIFO buffers in a time division manner, each time slot corresponds to one second-level FIFO buffer, and whether to write data to each second-level FIFO buffer is determined according to the full state of each second-level FIFO buffer in each time slot.
In one embodiment, the system further comprises a state detection module and a channel selection module, wherein the state detection module is used for acquiring the full state of each second-level FIFO buffer, and the channel selection module is used for writing the read data into the second-level FIFO buffer by the first-level FIFO buffer when the full state of the second-level FIFO buffer is at a low level.
Specifically, the state detection module judges the full flag prog_full_1 of the 1 st second-level FIFO buffer fifo_1, if the full flag prog_full_1 is low, the first-level FIFO buffer read enable is valid for M clock cycles, and the channel selection module writes the read data into the 1 st second-level FIFO buffer fifo_1 by the first-level FIFO buffer; after N1 reading clock cycles, the state detection module judges the full mark prog_full_2 of the 2 nd second-level FIFO buffer FIFO_2; if the full mark prog_full_1 is high level, the first-level FIFO buffer memory read enable is invalid for N1 clock cycles, and after N1 read clock cycles, the state detection module judges the full mark prog_full_2 of the 2 nd second-level FIFO buffer memory FIFO_2;
if the full flag prog_full_2 of the 2 nd second-level FIFO buffer fifo_2 is low, the first-level FIFO buffer read enable is valid for M clock cycles, and the channel selection module writes the read data into the 2 nd second-level FIFO buffer fifo_2 by the first-level FIFO buffer; after N2 reading clock cycles, the state detection module judges the full mark prog_full_3 of the 3 rd second-level FIFO buffer FIFO_3; if the full mark prog_full_2 is high level, the first-level FIFO buffer memory read enable is invalid for N2 clock cycles, and after N2 read clock cycles, the state detection module judges the full mark prog_full_3 of the 3 rd second-level FIFO buffer memory FIFO_3; and so on until the mth second-level FIFO buffer memory FIFO_m is processed, wherein m is the total number of the second-level FIFO buffers.
The state detection module judges the full mark prog_full_m of the mth second-level FIFO buffer memory FIFO_m, if the full mark prog_full_m is low level, the first-level FIFO buffer memory read enable is effective for M clock cycles, and the channel selection module writes the read data into the mth second-level FIFO buffer memory FIFO_m by the first-level FIFO buffer memory; after Nm read clock cycles, the state detection module judges the full mark prog_full_1 of the 1 st second-level FIFO buffer FIFO_1;
if the full flag prog_full_m is high, the first-level FIFO buffer read enable is invalid for Nm clock cycles, and after Nm read clock cycles, the state detection module determines that the full flag prog_full_1 of the 1 st second-level FIFO buffer fifo_1 is to be processed.
In this embodiment, the second-level FIFO buffer read enable is always active, and the FIFO read clock is the baseband data processing clock corresponding to each channel, and the FIFO read clock frequencies may be different. Furthermore, N1: n2: .. Nm=clk_td1:clk_td2: .. clk_tdm; m is the number of bytes of the data frame, N1, N2..Nm.gtoreq.M, wherein clk_td1, clk_td2..clk_tdm is the read clock of M second level FIFO buffers.
In one embodiment, the decision threshold to be full flag and the buffer depth of each second level FIFO buffer satisfy the following relationship: the decision threshold of the full flag should be at least M data spaces from the buffer depth, where M is the number of bytes of the data frame. In this embodiment, in the data transmission process, after the transmission of the request element signal is stopped, the valid data existing on the link will not overflow the first FIFO buffer; in the data transmission process, after the request number signal is started to be sent, the link delay from the valid data sending end to the first-stage FIFO buffer memory can not lead the first-stage FIFO buffer memory to be read empty.
In one embodiment, the first-level FIFO buffer reads data at a rate greater than the sum of the rates at which the respective second-level FIFO buffers output data. Since the first-level FIFO buffer and the second-level FIFO buffer are equal in read bit width, clock_local > clk_td1+clk_td2+ + clk_tdm. Where clock local is the read clock of the first level FIFO buffer.
In one embodiment, the system further comprises a data request module, the data request module judges and processes the full flag of the first-level FIFO buffer, and if the full flag of the first-level FIFO buffer is low level, the data request module sends a request number signal to front-end equipment (satellite-borne data processor), and valid data starts to be downloaded; if the full flag of the first-level FIFO buffer is high, the data request module stops sending the request number signal to the front-end device, and the valid data will stop being downloaded.
Further, after receiving the request element signal, the front-end device responds to a maximum effective data rate greater than a maximum line rate between the first-level FIFO buffer and the second-level FIFO buffer, i.e., clk_local_datain_bit_width > clk_local_dataout_bit_width, where datain represents input data of the first-level FIFO buffer and dataout represents output data of the first-level FIFO buffer. Where clk is the write clock of the first level FIFO buffer.
In summary, the satellite-borne multichannel multi-rate high-speed digital transmission interface system based on the request link has the following technical effects:
(1) According to the method and the device, under a request link, two-stage FIFO caches are used for data caching, and the mode that all second-stage FIFO caches are full is detected in a time-sharing mode through the state detection module, so that the functions of channel forwarding, baseband processing, digital-to-analog conversion and the like of single-channel input data are realized, and the integration level of the satellite-borne data transmission system is improved.
(2) According to the method and the device, under a request link, the mode that the state detection module detects the full mark of each second-level FIFO buffer memory in a time-sharing mode is adopted, so that the rate of each channel is irrelevant, the configuration can be independently carried out, and the use flexibility of the satellite-borne data transmission system is improved.
(3) According to the method and the device, the insertion of the empty frame data is avoided in the mode of requesting the number of elements, and the transmission efficiency of the effective data is improved.
The foregoing is merely various embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (7)

1. A request link based on-board multichannel multi-rate high speed data interface system, comprising: the system comprises a first-level FIFO buffer memory and a plurality of second-level FIFO buffer memories, wherein the first-level FIFO buffer memory transmits data to the second-level FIFO buffer memories in a time division mode, each time slot corresponds to one second-level FIFO buffer memory, and whether to write data to each second-level FIFO buffer memory is determined in each time slot according to the full state of each second-level FIFO buffer memory.
2. The system of claim 1, further comprising a status detection module for obtaining a full state of each of the second-level FIFO buffers, and a channel selection module for writing read data into the second-level FIFO buffer by the first-level FIFO buffer when the full state of the second-level FIFO buffer is low.
3. The system of claim 2, wherein when 1.ltoreq.n.ltoreq.m-1, m being the total number of said second level FIFO buffers, n being the sequence number of said second level FIFO buffers; the state detection module judges and processes a full mark prog_full_n of an nth second-level FIFO buffer FIFO_n, if the full mark prog_full_n is low level, a first-level FIFO buffer reading enabling is enabled to be effective for M clock cycles, and the channel selection module writes read data into the nth second-level FIFO buffer FIFO_n by the first-level FIFO buffer; after Nn reading clock cycles, the state detection module judges and processes a full mark prog_full_n+1 of an n+1th second-level FIFO buffer FIFO_n+1;
if the full flag prog_full_n is high level, the first-level FIFO buffer read enable is invalid for Nn clock cycles, and after Nn read clock cycles, the state detection module judges the full flag prog_full_n+1 of the n+1th second-level FIFO buffer fifo_n+1;
when n=m, the state detection module judges the full flag prog_full_n of the n second-level FIFO buffer fifo_n, if the full flag prog_full_n is low, the first-level FIFO buffer read enable is valid for M clock cycles, and the channel selection module writes the read data into the n second-level FIFO buffer fifo_n by the first-level FIFO buffer; after Nn reading clock cycles, the state detection module judges the full mark prog_full_1 of the 1 st second-level FIFO buffer FIFO_1;
if the full flag prog_full_n is high, the first-level FIFO buffer read enable is invalid for Nn clock cycles, and after Nn read clock cycles, the state detection module determines the full flag prog_full_1 of the 1 st second-level FIFO buffer fifo_1.
4. A system as claimed in claim 3, wherein the decision threshold for the full flag of each of said second level FIFO buffers is in relation to the buffer depth as follows:
the decision threshold of the full flag should be at least M data spaces away from the buffer depth, where M is the number of bytes of the data frame.
5. A system as claimed in claim 3, wherein the rate at which said first level FIFO buffer reads data is greater than the sum of the rates at which each of said second level FIFO buffers outputs data.
6. The system of claim 1, further comprising a data request module, wherein the data request module determines a full flag of the first FIFO buffer, and if the full flag of the first FIFO buffer is at a low level, the data request module sends a request number signal to a front-end device, and valid data starts to be downloaded; if the full flag of the first stage FIFO buffer is at high level, the data request module stops sending the request number signal to the front-end device, and the valid data will stop downloading.
7. The system of claim 6, wherein the head-end equipment, upon receiving the request element signal, responds with a maximum effective data rate greater than a maximum line rate between the first-level FIFO buffer and the second-level FIFO buffer.
CN202310154263.7A 2023-02-22 2023-02-22 Satellite-borne multichannel multi-rate high-speed data interface system based on request link Pending CN116318340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310154263.7A CN116318340A (en) 2023-02-22 2023-02-22 Satellite-borne multichannel multi-rate high-speed data interface system based on request link

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310154263.7A CN116318340A (en) 2023-02-22 2023-02-22 Satellite-borne multichannel multi-rate high-speed data interface system based on request link

Publications (1)

Publication Number Publication Date
CN116318340A true CN116318340A (en) 2023-06-23

Family

ID=86831680

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310154263.7A Pending CN116318340A (en) 2023-02-22 2023-02-22 Satellite-borne multichannel multi-rate high-speed data interface system based on request link

Country Status (1)

Country Link
CN (1) CN116318340A (en)

Similar Documents

Publication Publication Date Title
US20240004419A1 (en) Computer Architecture Having Selectable Parallel and Serial Communication Channels Between Processors and Memory
KR101840620B1 (en) Low-power mode signal bridge for optical media
US8090263B2 (en) System and method for expanding PCIe compliant signals over a fiber optic medium with no latency
JP5232019B2 (en) Apparatus, system, and method for multiple processor cores
US5963609A (en) Apparatus and method for serial data communication between plurality of chips in a chip set
US20080279224A1 (en) Alignment and Deskew For Multiple Lanes of Serical Interconnect
US5974058A (en) System and method for multiplexing serial links
US6886062B2 (en) Method and apparatus for improving time constraints and extending limited length cables in a multiple-speed bus
KR101588346B1 (en) On-package input/output architecture
CN108462620B (en) Gilbert-level SpaceWire bus system
CN104991883A (en) Sending and receiving apparatuses with chip interconnection and sending and receiving method and system
CN116795172B (en) Cross-clock domain processing method, medium and device for high-speed digital transmission
CN116318340A (en) Satellite-borne multichannel multi-rate high-speed data interface system based on request link
US6946873B1 (en) Method and system for recovering and aligning synchronous data of multiple phase-misaligned groups of bits into a single synchronous wide bus
US7082484B2 (en) Architecture for advanced serial link between two cards
CN111930176B (en) Multi-path LVDS data processing device and method
JP5244362B2 (en) High speed network system and related equipment
CN112311458B (en) Signal transmission method, device, equipment and system
US7194651B2 (en) Distributed link module architecture
US7321593B1 (en) Fibre channel SERDES with elastic transmitter FIFO
US7899955B2 (en) Asynchronous data buffer
CN114003543B (en) High-speed serial bus clock compensation method and system
RU2700560C1 (en) Gigaspacewire communication interface device
KR100416799B1 (en) UTOPIA interfacing method between two slave mode devices
JP2002223208A (en) Method and system for multi-channel data transmission

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination