CN116318113A

CN116318113A - Photoelectric isolation driver

Info

Publication number: CN116318113A
Application number: CN202310208738.6A
Authority: CN
Inventors: 陈益群; 林清俤; 邓维平; 林泽佑; 施云生
Original assignee: Ningbo Qunxin Microelectronics Co ltd
Current assignee: Ningbo Qunxin Microelectronics Co ltd
Priority date: 2023-02-28
Filing date: 2023-02-28
Publication date: 2023-06-23

Abstract

The invention discloses a photoelectric isolation driver, which comprises: the optical transmitter comprises an optical transmitting module, an optical receiving module, a signal processing module and a push-pull output power module; the light emitting module is used for generating a light signal according to an external input voltage signal; the light receiving module comprises at least one PIN junction photodiode and is used for receiving the light signal and generating a current signal; the signal processing module is used for outputting a driving signal according to the current signal; the push-pull output power module is of a complementary output power structure and is used for outputting a voltage signal according to the driving signal. By utilizing the scheme of the invention, the transmission rate and the output current can be improved, so that the requirements of large current and high transmission rate can be met.

Description

Photoelectric isolation driver

Technical Field

The invention relates to the field of circuits, in particular to a photoelectric isolation driver.

Background

The photoelectric isolator is a device for transmitting electric signals by taking light as a medium, namely, the electric signals at an input end are coupled to an output end by taking light as a medium, so that 'electric-optical-electric' control is realized. A photo-isolation driver is one type of photo-isolator that utilizes the transmission and conversion of photo-electricity to achieve complete isolation between input and output electrically while amplifying low voltage or low current signals from a microcontroller or other source to provide drive voltages and currents to high power devices such as transistors, IGBTs (Insulated Gate Bipolar Transistor, insulated gate bipolar transistors), MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-Oxide semiconductor field effect transistors). The photoelectric isolation driver is widely applied to high-power motor control, industrial drivers, solar power sources and inverters, switch modes, uninterruptible power sources and the like.

The structure of a conventional photovoltaic isolation driver is shown in fig. 1, and the photovoltaic isolation driver 100 includes: a light emitting diode 11, a light receiving module 12, a signal processing module 13, and a push-pull output power module 14. The push-pull output power module 14 includes two MOS transistors, i.e., an LDPMOS transistor and an LDNMOS transistor in fig. 1.

The optoelectric isolation driver 100 shown in fig. 1 generally includes the light receiving module 12, the signal processing module 13 and the push-pull output power module 14 on a single chip, and for this purpose, the push-pull output power module 14 can use only an integrated LDMOS (laterally diffused metal-oxide semiconductor) tube, and the light receiving module 12 can use only an integrated PN junction photodiode.

The on-resistance of the LDMOS tube is large, and the power consumption is large when the large current is output, generally from hundreds of mΩ to hundreds of Ω, so that the maximum output current can be limited below 5A, and the requirement of the large current output can not be met.

In the whole photoelectric isolation driver, the transmission delay time of the light receiving module accounts for a main proportion. The existing light receiving module adopts an integrated PN junction photodiode, the photoelectric sensitivity is low, a large chip area is required to meet the receiving current requirement, junction capacitance is large, the transmission rate of the whole photoelectric isolation driver is low, the transmission delay time is more than hundreds ns order of magnitude, and the high-speed transmission requirement cannot be met.

Disclosure of Invention

The embodiment of the invention provides a photoelectric isolation driver, which is used for improving the transmission rate and the output current so as to meet the requirements of high current and high transmission rate.

Therefore, the embodiment of the invention provides the following technical scheme:

an embodiment of the present invention provides a photoelectric isolation driver, including: the optical transmitter comprises an optical transmitting module, an optical receiving module, a signal processing module and a push-pull output power module;

the light emitting module is used for generating light signals according to external input voltage signals;

the light receiving module comprises at least one PIN junction photodiode and is used for receiving the light signal and generating a current signal;

the signal processing module is used for outputting a driving signal according to the current signal;

the push-pull output power module is of a complementary output power structure and is used for outputting a voltage signal according to the driving signal.

Optionally, the push-pull output power module comprises an upper tube and a lower tube, wherein the upper tube and the lower tube are high-power MOS tubes; the connection point of the upper pipe and the lower pipe is used as the output end of the photoelectric isolation driver; when the upper pipe works, the lower pipe stops working, and the output end outputs high level; when the lower pipe works, the upper pipe stops working, and the output end outputs a low level.

Optionally, the upper tube includes a first PMOS tube and a first NMOS tube connected in parallel, and the lower tube includes a second NMOS tube.

Optionally, the first PMOS transistor, the first NMOS transistor, and the second NMOS transistor are three independent chips and are driven by different driving signals.

Optionally, the first PMOS transistor is any one of the following: VDPMOS tube, trench_PMOS tube.

Optionally, the first NMOS transistor and the second NMOS transistor are any one of the following: VDNMOS tube, trench_NMOS tube, SGT_NMOS tube.

Optionally, the signal processing module includes: the device comprises a current amplifier, a voltage comparator, a cathode driving circuit, a bias circuit, an undervoltage locking circuit and an output logic driving circuit;

the cathode driving circuit is connected with the cathode of the PIN junction photodiode and is used for generating a cathode driving voltage of the PIN junction photodiode;

the input end of the current amplifier is connected with the anode of the PIN junction photodiode, and the output end of the current amplifier is connected with the positive input end of the voltage comparator;

the bias circuit is connected with the negative input end of the voltage comparator and is used for generating reference voltage;

the two input ends of the output logic driving circuit are respectively connected with the undervoltage locking circuit and the output end of the voltage comparator, and the three output ends of the output logic driving circuit are respectively connected with the first PMOS tube, the first NMOS tube and the second NMOS tube and are used for outputting the driving signals according to the output signals of the undervoltage locking circuit and the voltage comparator.

Optionally, the cathode driving circuit is a low dropout linear voltage regulator.

Optionally, the output logic driving circuit includes: a signal conversion unit and a driving unit;

the signal conversion unit is used for generating an intermediate signal according to the output signal of the undervoltage locking circuit and the output signal of the voltage comparator;

the driving unit is used for generating the driving signal according to the intermediate signal.

Optionally, the driving unit includes:

the first driving signal generation unit is used for generating a first driving signal for driving the first PMOS tube according to the driving signal;

the second driving signal generation unit is used for generating a second driving signal for driving the first NMOS tube according to the driving signal;

and the third driving signal generating unit is used for generating a third driving signal for driving the second NMOS tube according to the driving signal.

Optionally, the structures of the first driving signal generating unit, the second driving signal generating unit and the third driving signal generating unit are the same, and each driving signal generating unit is composed of a PMOS tube and an NMOS tube, the grid electrode of the PMOS tube is connected with the grid electrode of the NMOS tube, a corresponding intermediate signal is input, and the drain electrode of the PMOS tube is connected with the drain electrode of the NMOS tube and is used as an output end to output a corresponding driving signal.

Alternatively, the three driving signal generating units employ different levels of operating power.

Optionally, an ITO film is deposited on the photosensitive area above the P+ layer of the PIN junction photodiode.

The photoelectric isolation driver provided by the embodiment of the invention adopts the PIN junction photodiode, and has the advantages of small junction capacitance, short carrier transit time, high photoelectric sensitivity and the like, so that the transmission rate of the whole photoelectric isolation driver is greatly improved; moreover, the push-pull output power module adopts a complementary output power structure, so that the requirement of high current can be met.

Drawings

FIG. 1 is a schematic diagram of a conventional photovoltaic isolation driver of the prior art;

FIG. 2 is a schematic diagram of a photovoltaic isolation driver according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a specific structure of an optoelectronic isolation driver according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a PIN junction photodiode according to an embodiment of the present invention;

FIG. 5 is a schematic diagram of an output logic driving circuit according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a push-pull output power module and a driving unit thereof according to an embodiment of the invention.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 2 is a schematic structural diagram of a photovoltaic isolation driver according to an embodiment of the present invention.

The photo-isolation driver 200 includes: an optical transmitting module 201, an optical receiving module 202, a signal processing module 203, and a push-pull output power module 204. Wherein:

the light emitting module 201 is configured to generate an optical signal according to an external input voltage signal;

the light receiving module 202 includes at least one PIN junction photodiode for receiving the light signal and generating a current signal;

the signal processing module 203 is configured to output a driving signal according to the current signal;

the push-pull output power module 204 is a complementary output power structure for outputting a voltage signal according to the driving signal.

Fig. 3 is a schematic diagram of a specific structure of a photovoltaic isolation driver according to an embodiment of the present invention.

In this embodiment, the light emitting module 201 is composed of at least one light emitting diode, two ends of the light emitting diode are connected to the external signal input terminal, the anode is connected to the positive input signal terminal, and the cathode is connected to the negative input signal terminal.

The light receiving module 202 is composed of at least one PIN junction photodiode. In comparison with a common PN junction photodiode, a PIN junction photodiode is formed by doping a layer of near-intrinsic semiconductor with very low concentration in the middle of a PN junction, which is called an I layer. The I layer is thicker, occupying almost the entire depletion region, and most of the incident light is absorbed in the I layer and generates a large number of electron-hole pairs. The P+ type semiconductor and the N+ type semiconductor with high doping concentration are arranged on two sides of the I layer, the P+ layer and the N+ layer are thin, and the proportion of absorbed incident light is small. The introduction of the I layer increases the width of the depletion layer, which is favorable for shortening the diffusion process of carriers and reducing the influence of diffusion motion, so that drift components in light-generated current are dominant, and the response speed can be greatly improved. The widening of the depletion layer can obviously reduce junction capacitance, shorten transition time and improve photoelectric sensitivity, thereby effectively improving transmission rate.

Further, as shown in fig. 4, in a non-limiting embodiment, an ITO (tin doped indium oxide, a transparent conductive film) film may be further deposited on the photosensitive region above the p+ layer of the PIN junction photodiode, which may greatly improve the light absorption rate and improve the photoelectric sensitivity.

With continued reference to fig. 3, in this embodiment, the push-pull output power module 204 includes an upper tube and a lower tube, which are both high-power MOS tubes. The connection point of the upper tube and the lower tube is used as an output end of the photoelectric isolation driver 200; when the upper pipe works, the lower pipe stops working, and the output end outputs high level; when the lower pipe works, the upper pipe stops working, and the output end outputs a low level.

As shown in fig. 3, the upper tube includes a first PMOS tube PM1 and a first NMOS tube NM1 connected in parallel, and the lower tube includes a second NMOS tube NM2. The three MOS tubes respectively adopt independent high-power MOS tubes.

Specifically, the source of the first PMOS tube PM1 and the drain of the first NMOS tube NM1 are connected to the power supply VCC, the drain of the first PMOS tube PM1 is connected to the source of the first NMOS tube NM1, and the connection node is used as the output end of the optoelectronic isolation driver 200;

the drain electrode of the second NMOS tube NM2 is connected with the drain electrode of the first PMOS tube PM1, and the source electrode of the second NMOS tube NM2 is grounded.

In this embodiment, the first PMOS transistor PM1, the first NMOS transistor NM1, and the second NMOS transistor NM2 are driven by different power supplies, that is, the gates of the three MOS transistors are connected to different output terminals of the signal processing module 203, respectively. For convenience of description, gate driving voltages of the first PMOS transistor PM1, the first NMOS transistor NM1, and the second NMOS transistor NM2 are respectively denoted as Vp, vn1, vn2.

When the output current is smaller, the first PMOS tube PM1 is the drain output, the output voltage Vo is pulled to VCC, and as the first NMOS tube NM1 is the source output, a lining bias effect exists, if VCC-Vo is smaller than the starting voltage VthN of the first NMOS tube NM1, the first NMOS tube NM1 is cut off; when the output current is larger, the output impedance of the first PMOS tube PM1 increases in proportion to the output current due to the poor large current characteristic of the first PMOS tube PM1, and if VCC-Vo is made to be greater than the turn-on voltage VthN of the first NMOS tube NM1, the first NMOS tube NM1 is turned on. The first NMOS tube NM1 has the advantage of strong large current output capability, so that the defect of poor large current capability of the first PMOS tube PM1 is overcome.

In practical application, in order to improve the high current output capability, the first PMOS tube PM1 may be a VDPMOS tube with a low-turn-on voltage thin gate oxide layer thickness or a tree_pmos tube; the first NMOS transistor NM1 may be a VDNMOS transistor, a tree_nmos transistor, or an sgt_nmos transistor with a low turn-on voltage and a thin gate oxide layer thickness; the second NMOS transistor NM2 may be a VDNMOS transistor, a tree_nmos transistor, or an sgt_nmos transistor with a low on-voltage thin gate oxide thickness.

The following describes the specific structure of the signal processing module 203 in the embodiment of the present invention with continued reference to fig. 3.

Referring to fig. 3, the signal processing module 203 in this embodiment includes: a current amplifier TIA, a voltage comparator COMP, a cathode drive circuit LDO, a BIAS circuit BIAS, an under-voltage lockout circuit UVLO, and an output logic drive circuit DRI. Wherein:

the cathode driving circuit LDO is connected with the cathode of the PIN junction photodiode and is used for generating cathode driving voltage of the PIN junction photodiode. The cathode driving circuit LDO can be a low dropout linear voltage regulator.

The input end of the current amplifier TIA is connected with the anode of the PIN junction photodiode, the output end of the current amplifier TIA is connected with the positive input end of the voltage comparator COMP, and the amplified voltage Vd is output to the voltage comparator COMP.

The BIAS circuit BIAS is connected to the negative input end of the voltage comparator COMP and is used for generating a reference voltage Vref. When the output voltage Vd of the current amplifier TIA is greater than the reference voltage Vref, the output signal Vs of the voltage comparator COMP is high level; otherwise the output signal Vs is low.

Two input ends of the output logic driving circuit DRI are respectively connected with the output ends of the undervoltage locking circuit UVLO and the voltage comparator COMP, and three output ends of the output logic driving circuit DRI are respectively connected with the first PMOS tube PM1, the first NMOS tube NM1 and the second NMOS tube NM2, and are used for outputting driving voltage signals Vp, vn1 and Vn2 to three MOS tubes according to the output signal Vr of the undervoltage locking circuit UVLO and the output signal Vs of the voltage comparator COMP.

The state transition table of the output logic driving circuit DRI is shown in table 1 below.

TABLE 1

In order to implement the control logic, a specific structure of the output logic driving circuit DRI is shown in fig. 5, and includes: a signal conversion unit 501 and a driving unit 502.

Wherein the signal conversion unit 501 is configured to generate intermediate signals, that is, a first intermediate signal S1, a second intermediate signal S2, and a third intermediate signal S3 in table 1, according to an output signal Vr (corresponding to R in table 1) of the undervoltage lock circuit UVLO and an output signal Vs (corresponding to S in table 1) of the voltage comparator;

the driving unit 502 is configured to generate driving signals of three MOS transistors in the back-end push-pull output power module 204 by using the intermediate signal, that is, the driving signal Vp of the first PMOS transistor PM1, the driving signal Vn1 of the first NMOS transistor NM1, and the driving signal Vn2 of the second NMOS transistor NM2.

In practical applications, the signal conversion unit 501 may be implemented by using corresponding logic devices according to the signal logic relationship in table 1, and the specific structure thereof is not limited in the embodiment of the present invention.

Fig. 6 shows a specific structural example of the above-described driving unit 502.

In this example, the driving unit 502 includes: a first driving signal generating unit, a second driving signal generating unit, and a third driving signal generating unit for generating the three driving signals Vp, vn1, vn2, respectively.

The three driving signal generating units may have the same structure, i.e., one PMOS transistor and one NMOS transistor, such as P1 and N1, P2 and N2, and P3 and N3 in fig. 6. The grid electrode of the PMOS tube in each driving signal generating unit is connected with the grid electrode of the NMOS tube, corresponding intermediate signals S1, S2 and S3 are input, and the drain electrode of the PMOS tube is connected with the drain electrode of the NMOS tube and used as an output end to output corresponding driving signals. The source electrode of the PMOS transistor and the source electrode of the NMOS transistor are respectively applied with power supplies of different levels, and the three driving signal generating units adopt working power supplies of different levels, as shown in fig. 6:

the power supply ranges of P1 and N1 in the first driving signal generating unit are set from VCC-5V to VCC, so that the gate-source voltage Vgs of the first PMOS tube PM1 in the push-pull output power module 204 is ensured to be less than or equal to 5V, and the safety of the work of the first PMOS tube PM1 is ensured.

The power ranges of P2 and N2 in the second driving signal generating unit are set from Vo to vo+5v, so that the gate-source voltage Vgs of the first NMOS transistor NM1 in the push-pull output power module 204 is ensured to be less than or equal to 5V, and the safety of the operation of the first NMOS transistor NM1 is ensured.

The power supply ranges of P3 and N3 in the third driving signal generating unit are set at 5V to 0V.

The photoelectric isolation driver provided by the embodiment of the invention adopts the PIN junction photodiode, and has the advantages of small junction capacitance, short transit time, high photoelectric sensitivity and the like, so that the transmission rate of the whole photoelectric isolation driver is greatly improved, and the transmission delay time is reduced to be within 10 ns. The push-pull output power module adopts a complementary output power structure, so that the requirement of high current can be met.

Further, the push-pull output power module upper tube adopts an independent high-power PMOS tube connected in parallel with an independent high-power NMOS tube, and the lower tube adopts an independent high-power NMOS tube; the on-resistance is small in the range of several mΩ to several tens of mΩ, the power consumption is small when large current is output, and the maximum output current can cover the range of 1A to 30A.

The photoelectric isolation driver provided by the embodiment of the invention can design the light emitting module, the light receiving module, the signal processing module and the push-pull output power module in different chips by adopting a multi-chip assembly technology, and can be realized in one circuit, so that the packaging cost can be greatly reduced.

It should be understood that the term "and/or" is merely an association relationship describing the associated object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, the character "/" indicates that the front and rear associated objects are an "or" relationship.

The term "plurality" as used in the embodiments of the present invention means two or more.

The first, second, etc. descriptions in the embodiments of the present invention are only used for illustrating and distinguishing the description objects, and no order is used, nor is the number of the devices in the embodiments of the present invention limited, and no limitation on the embodiments of the present invention should be construed.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims

1. A photovoltaic isolation driver comprising: the optical transmitter comprises an optical transmitting module, an optical receiving module, a signal processing module and a push-pull output power module; the method is characterized in that:

2. The optoelectronic isolation driver of claim 1, wherein the push-pull output power module comprises an upper tube and a lower tube, both of which are high power MOS tubes; the connection point of the upper pipe and the lower pipe is used as the output end of the photoelectric isolation driver; when the upper pipe works, the lower pipe stops working, and the output end outputs high level; when the lower pipe works, the upper pipe stops working, and the output end outputs a low level.

3. The optoelectric isolation driver of claim 2 wherein the upper tube comprises a first PMOS tube and a first NMOS tube connected in parallel and the lower tube comprises a second NMOS tube.

4. The optoelectric isolation driver of claim 3 wherein the first PMOS transistor, the first NMOS transistor, and the second NMOS transistor are three independent chips and are driven by respective different drive signals.

5. A photovoltaic isolation driver according to claim 3, wherein the first PMOS transistor is any one of: VDPMOS tube, trench_PMOS tube.

6. The optoelectric isolation driver of claim 3 wherein the first and second NMOS transistors are any one of: VDNMOS tube, trench_NMOS tube, SGT_NMOS tube.

7. The optoelectric isolation driver of claim 4 wherein the signal processing module comprises: the device comprises a current amplifier, a voltage comparator, a cathode driving circuit, a bias circuit, an undervoltage locking circuit and an output logic driving circuit;

8. The optoelectric isolation driver of claim 7 wherein the cathode drive circuit is a low dropout linear regulator.

9. The optoelectric isolation driver of claim 7 wherein the output logic drive circuit comprises: a signal conversion unit and a driving unit;

10. The optoelectric isolation driver of claim 9 wherein the drive unit comprises:

11. The optoelectronic isolation driver of claim 10, wherein the first driving signal generating unit, the second driving signal generating unit, and the third driving signal generating unit have the same structure and are each composed of a PMOS transistor and an NMOS transistor, the gate of the PMOS transistor is connected to the gate of the NMOS transistor, a corresponding intermediate signal is input, and the drain of the PMOS transistor is connected to the drain of the NMOS transistor and outputs a corresponding driving signal as an output terminal.

12. The optoelectric isolation driver of claim 11 wherein the three drive signal generating units employ different levels of operating power.

13. The optoelectric isolation driver of any one of claims 1 to 12 wherein an ITO film is deposited over the p+ layer of the PIN junction photodiode.