CN116316515A - Control circuit for preventing current from flowing reversely - Google Patents

Control circuit for preventing current from flowing reversely Download PDF

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Publication number
CN116316515A
CN116316515A CN202310321340.3A CN202310321340A CN116316515A CN 116316515 A CN116316515 A CN 116316515A CN 202310321340 A CN202310321340 A CN 202310321340A CN 116316515 A CN116316515 A CN 116316515A
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China
Prior art keywords
electrically connected
voltage
field effect
module
effect transistor
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CN202310321340.3A
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Inventor
肖慕尧
陈阳
童斌
张学达
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Chongqing Changan New Energy Automobile Technology Co Ltd
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Chongqing Changan New Energy Automobile Technology Co Ltd
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Priority to CN202310321340.3A priority Critical patent/CN116316515A/en
Publication of CN116316515A publication Critical patent/CN116316515A/en
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H11/00—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result
    • H02H11/002—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of inverted polarity or connection; with switching for obtaining correct connection
    • H02H11/003—Emergency protective circuit arrangements for preventing the switching-on in case an undesired electric working condition might result in case of inverted polarity or connection; with switching for obtaining correct connection using a field effect transistor as protecting element in one of the supply lines
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
    • Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

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Abstract

The invention provides a control circuit for preventing current reverse irrigation, which comprises: the field effect transistor module is electrically connected with the input voltage end of the current signal; the positive input end of the first comparison module is electrically connected with the input voltage end, the negative input end of the first comparison module is electrically connected with the drain electrode of the field effect transistor module, and the output end of the first comparison module is electrically connected with the grid electrode of the field effect transistor module and is used for starting the field effect transistor module; the positive input end of the differential module is electrically connected with the input voltage end, the negative input end of the differential module is electrically connected with the drain electrode of the field effect transistor module, and the output end of the differential module is electrically connected with the grid electrode of the field effect transistor module and is used for adjusting the grid source voltage of the field effect transistor module; and the negative input end of the second comparison module is electrically connected with the input voltage end, the positive input end of the second comparison module is electrically connected with the drain electrode of the field effect transistor module, and the output end of the second comparison module is electrically connected with the grid electrode of the field effect transistor module and is used for turning off the field effect transistor module. The invention can prevent current reverse current and provide stable output voltage for the back-end load.

Description

Control circuit for preventing current from flowing reversely
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a control circuit for preventing current reverse-filling.
Background
The anti-reverse-filling circuit is used for preventing the power supply from being damaged by reverse-filling of the current at the output end. The anti-reverse-filling circuit generally adopts voltage control of the gate-source voltage of the metal oxide semiconductor field effect transistor so that the metal oxide semiconductor field effect transistor is disconnected under the condition that the circuit is reversely connected or current reverse-filling exists.
In the prior art, when the mosfet is turned on in the forward direction, if the load resistance changes, the bus current will change. When the gate-source voltage of the metal oxide semiconductor field effect transistor is constant, and the on-resistance is unchanged, the on-voltage drop voltage on the metal oxide semiconductor field effect transistor can change, so that the back-end voltage is unstable.
Disclosure of Invention
One of the purposes of the present invention is to provide a control circuit for preventing reverse current flowing, which can be used for solving the problem of unstable back-end voltage caused by large load change of the circuit.
To achieve the above and other related objects, the present invention provides a control circuit for preventing current reverse charging, comprising:
the field effect transistor module is electrically connected with the input voltage end of the current signal;
the positive input end of the first comparison module is electrically connected with the input voltage end, the negative input end of the first comparison module is electrically connected with the drain electrode of the field effect transistor module, and the output end of the first comparison module is electrically connected with the grid electrode of the field effect transistor module and is used for starting the field effect transistor module;
the positive input end of the differential module is electrically connected with the input voltage end, the negative input end of the differential module is electrically connected with the drain electrode of the field effect transistor module, and the output end of the differential module is electrically connected with the grid electrode of the field effect transistor module and is used for adjusting the grid source voltage of the field effect transistor module; and
and the negative input end of the second comparison module is electrically connected with the input voltage end, the positive input end of the second comparison module is electrically connected with the drain electrode of the field effect transistor module, and the output end of the second comparison module is electrically connected with the grid electrode of the field effect transistor module and is used for turning off the field effect transistor module.
In an embodiment of the present invention, the first comparing module includes:
the positive input end of the first comparison unit is electrically connected with the input voltage end, and the negative input end of the first comparison unit is electrically connected with the drain electrode of the field effect transistor module; and
the source electrode of the first field effect tube is electrically connected with the gate-source voltage end, the drain electrode of the first field effect tube is electrically connected with the grid electrode of the field effect tube module, and the grid electrode of the first field effect tube is electrically connected with the output end of the first comparison unit;
when the voltage difference between the input voltage end and the drain electrode of the field effect transistor module is located in a preset first voltage interval, the first comparison unit outputs a low level to start the first field effect transistor.
In an embodiment of the present invention, the first comparing unit includes:
the first adder is electrically connected with a preset first voltage end and is electrically connected with the drain electrode of the field effect transistor module by the addition end, and the first adder is used for generating an upper limit voltage;
the positive input end of the first comparator is electrically connected with the input voltage end, and the negative input end of the first comparator is electrically connected with the output end of the first adder; and
and the input end of the inverter is electrically connected with the output end of the first comparator, and the output end of the inverter is electrically connected with the grid electrode of the first field effect transistor.
In an embodiment of the present invention, the differential module includes:
the positive input end of the differential unit is electrically connected with the input voltage end, and the negative input end of the differential unit is electrically connected with the drain electrode of the field effect tube module; and
and the negative input end of the feedback unit is electrically connected with the output end of the differential unit, and the output end of the feedback unit is electrically connected with the grid electrode of the field effect transistor module.
When the voltage difference between the input voltage end and the drain electrode of the field effect transistor module is located in a preset second voltage interval, the differential unit adjusts the gate-source voltage of the field effect transistor module.
In an embodiment of the present invention, the differential unit includes:
the adder is electrically connected with a preset second voltage end and is electrically connected with the drain electrode of the field effect transistor module, and the second adder is used for generating differential voltage; and
and the positive input end of the differential amplifier is electrically connected with the input voltage end, the negative input end of the differential amplifier is electrically connected with the output end of the second adder, and the differential amplifier is used for amplifying the difference value between the input voltage end and the differential voltage.
In an embodiment of the present invention, when the voltage difference between the input voltage terminal and the drain of the fet module is located in the second voltage range, the gate voltage U of the fet module D The following formula is satisfied:
U D ＝U′ D +M×(V BAT -U M )
wherein U 'is' D Representing the historical grid voltage value of the field effect transistor module, M representing the amplification factor of the differential amplifier, V BAT Representing the voltage value of the input voltage terminal, U M Representing the differential voltage.
In an embodiment of the invention, when the voltage value of the input voltage terminal is greater than the differential voltage, the gate voltage of the fet module increases linearly.
In an embodiment of the invention, when the voltage value of the input voltage terminal is less than or equal to the differential voltage, the gate voltage of the fet module is linearly reduced.
In an embodiment of the present invention, the second comparing module includes:
the negative input end of the second comparison unit is electrically connected with the input voltage end, and the positive input end of the second comparison unit is electrically connected with the drain electrode of the field effect transistor module; and
the source electrode of the second field effect tube is electrically connected with the input voltage end, the drain electrode of the second field effect tube is electrically connected with the grid electrode of the field effect tube module, and the grid electrode of the second field effect tube is electrically connected with the output end of the second comparison unit;
when the voltage difference between the input voltage end and the drain electrode of the field effect transistor module is in a preset third voltage interval, the second comparison unit outputs a high level for starting the second field effect transistor.
In an embodiment of the present invention, the second comparing unit includes:
the adder is electrically connected with a preset third voltage end and is electrically connected with the drain electrode of the field effect transistor module, and the third adder is used for generating a lower limit voltage;
a second comparator, the negative input end of which is electrically connected with the input voltage end, and the positive input end of which is electrically connected with the output end of the third adder; and
the reset end of the trigger is electrically connected with the output end of the second comparator, the set end of the trigger is electrically connected with the output end of the first comparison unit, and the negative output end of the trigger is electrically connected with the grid electrode of the second field effect tube.
As described above, the control circuit for preventing current reverse-filling provided by the invention has the following beneficial effects:
(1) According to the invention, the on and off of the circuit can be controlled according to the voltage difference between the input voltage and the output voltage so as to prevent current reverse filling;
(2) The invention can adjust the conduction voltage drop voltage of the field effect transistor according to the change of the rear load resistance, and ensure the stability of the rear voltage.
Drawings
FIG. 1 is a schematic diagram of a control circuit for preventing reverse current flowing in an embodiment of the invention;
FIG. 2 is a schematic circuit diagram of a first comparing module according to an embodiment of the invention;
FIG. 3 is a schematic circuit diagram of a differential module according to an embodiment of the invention;
fig. 4 is a circuit diagram of a second comparing module according to an embodiment of the invention.
Description of element reference numerals
100. A field effect transistor module;
200. a first comparison module; 210. a first comparing unit; 211. a first adder; 212. a first comparator; 213. an inverter; 220. a first field effect transistor;
300. a differential module; 310. a differential unit; 311. a second adder; 312. a differential amplifier; 320. a feedback unit;
400. a second comparison module; 410. a second comparing unit; 411. a third adder; 412. a second comparator; 413. a trigger; 420. and a second field effect transistor.
Detailed Description
Further advantages and effects of the present invention will become readily apparent to those skilled in the art from the disclosure herein, by referring to the accompanying drawings and the preferred embodiments. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be understood that the preferred embodiments are presented by way of illustration only and not by way of limitation.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
Referring to fig. 1 to 4, the present invention provides a control circuit for preventing reverse current injection, which can be applied to the technical field of electronic circuits, and particularly can be applied to circuits with large back-end load variation and high requirement on input voltage stability. The invention can control the on and off of the circuit according to the voltage difference between the input voltage and the output voltage so as to prevent the current from flowing backwards. The following will describe in detail specific examples.
Referring to fig. 1, in one embodiment of the present invention, a control circuit for preventing current reverse charging may include: the field effect transistor module 100, the first comparison module 200, the difference module 300 and the second comparison module 400. Wherein the FET module 100 may be an insulated gate enhancementA strong NMOS (N-Metal-Oxide-Semiconductor) tube. The source of the fet module 100 may be electrically connected to the input voltage terminal, and the drain thereof may be the voltage output terminal of the control circuit. The input voltage at the input voltage terminal can be denoted as V BAT The drain voltage of the FET module 100 is the output voltage, which can be denoted as V OUT . The positive input end of the first comparison module 200 may be electrically connected to the input voltage end, the negative input end thereof may be electrically connected to the drain electrode of the fet module 100, and the output end thereof may be electrically connected to the gate electrode of the fet module 100. The first comparison module 200 may be used to turn on the fet module 100 while reducing the on-resistance of the fet module 100. The positive input of the differential module 300 may be electrically connected to the input voltage, the negative input thereof may be electrically connected to the drain of the fet module 100, and the output thereof may be electrically connected to the gate of the fet module. The differential module 300 can be used to adjust the gate-source voltage of the fet module 100 to ensure that the on-voltage drop voltage of the fet module 100 is stable. The second comparison module 400 may be used to turn off the fet module 100 to prevent current reverse-filling of the circuit. The negative input terminal of the second comparison module 400 may be electrically connected to the input voltage terminal, the positive input terminal thereof may be electrically connected to the drain electrode of the fet module 100, and the output terminal thereof may be electrically connected to the gate electrode of the fet module 100.
Referring to fig. 2, in an embodiment of the invention, the first comparing module 200 may include a first comparing unit 210 and a first fet 220. Wherein the positive input end of the first comparing unit 210 can be electrically connected to the input voltage end V BA The negative input terminal may be electrically connected to the drain of the fet module 100. The first FET 220 may be a PMOS (positive channel Metal Oxide Semiconductor, P-channel metal oxide semiconductor field effect transistor) transistor, a source thereof may be electrically connected to a gate-source voltage terminal, and a voltage of the gate-source voltage terminal may be a maximum gate-source voltage U MAX The drain may be electrically connected to the gate of the fet module 100. The output terminal of the first comparing unit 210 may be electrically connected to the gate of the first fet 100. In the present embodiment, when the input voltage V BAT And output voltage V OUT When the voltage difference of the first comparison unit 2 is within the preset first voltage range10 can output a low level to turn on the first fet 220, i.e. the source and drain of the first fet 220 are turned on, and the first comparison module 200 outputs the maximum gate-source voltage U to the gate of the fet module 100 MAX . At this time, the fet module 100 is turned on, and the circuit between the source and the drain of the fet module 100 is turned on.
Referring to fig. 2, in an embodiment of the invention, the first comparing unit 210 may include a first adder 211, a first comparator 212 and an inverter 213. The adder end of the first adder 211 may be electrically connected to a predetermined first voltage end, and the adder end may be electrically connected to the drain of the fet module 100. The first adder 211 may be used to generate the upper limit voltage U H . In this embodiment, the voltage of the preset first voltage terminal may be 50mV, so that the upper limit voltage U is known H Output voltage V OUT +50mV. The positive input terminal of the first comparator 212 may be electrically connected to the input voltage terminal, and the negative input terminal thereof may be electrically connected to the output terminal of the first adder 211, i.e. the upper limit voltage U H . The first comparator 212 can compare the input voltage V BAT And upper limit voltage U H The method comprises the steps of carrying out a first treatment on the surface of the When the input voltage V BAT Greater than upper limit voltage U H The first comparator 212 may output a high level; when the input voltage V BAT Less than upper limit voltage U H The first comparator 212 may output a low level. An input terminal of the inverter 213 may be electrically connected to an output terminal of the first comparator 212, and an output terminal thereof may be electrically connected to a gate of the first fet 220. The inverter 213 may be used to phase-invert the output voltage of the first comparator 212 by 180 degrees. In the present embodiment, when the input voltage V BAT And output voltage V OUT Is within a preset first voltage range, i.e. the input voltage V BAT Greater than upper limit voltage U H When the output of the first comparator 212 is high; then, the phase of the inverter 213 is inverted to output a low level to the gate of the first fet 220, so that the first fet 220 is turned on.
Referring to fig. 3, in one embodiment of the present invention, the differential module 300 may include a differential unit 310 and a feedback unit 320. Wherein the positive input terminal of the differential unit 310 can be electrically connected to the input powerPress end V BAT The negative input terminal may be electrically connected to the drain of the fet module 100. The negative input terminal of the feedback unit 320 may be electrically connected to the output terminal of the differential unit 310, and the output terminal thereof may be electrically connected to the gate of the fet module 100. In the present embodiment, when the input voltage V BAT And output voltage V OUT When the difference between the first voltage interval and the second voltage interval is within the second voltage interval, the differential unit 310 may adjust the gate-source voltage of the fet module 100, so as to maintain the on-voltage drop of the fet module 100 stable.
Referring to fig. 3, in one embodiment of the present invention, the differential unit 310 may include a second adder 311 and a differential amplifier 312. The adder end of the second adder 311 may be electrically connected to a predetermined second voltage end, and the adder end may be electrically connected to the drain of the fet module 100. The second adder 311 can be used to generate the differential voltage U M . In this embodiment, the voltage of the preset second voltage terminal may be 20Mv. From this, it can be seen that the differential voltage U M Output voltage V OUT +20mV. The positive input of the differential amplifier 312 may be electrically connected to the input voltage terminal V BAT The negative input of which may be electrically connected to the output of the second adder 211. Differential amplifier 312 may be used to amplify the input voltage V BAT And differential voltage U M Is a voltage difference of (a). In the present embodiment, when the input voltage V BAT Greater than differential voltage U M When the gate-source voltage of the fet module 100 will increase linearly; when the input voltage V BAT Less than differential voltage U M The gate-source voltage of the fet module will decrease linearly when this occurs.
Referring to fig. 4, in an embodiment of the invention, the second comparing module 400 may include a second comparing unit 410 and a second fet 420. The negative input terminal of the second comparing unit 410 may be electrically connected to the input voltage terminal, and the positive input terminal thereof may be electrically connected to the drain of the fet module 100. The source of the second fet 420 may be electrically connected to the input voltage terminal, the drain thereof may be electrically connected to the drain of the fet module 100, and the gate thereof may be electrically connected to the output terminal of the second comparing unit 410. In the present embodiment, when the input voltage V BAT And output voltage V OUT Is within a preset third voltage rangeWhen the second comparing unit 410 outputs a high level, the second fet 420 is controlled to turn on. At this time, the gate of the FET module 100 may be connected to the input voltage V BAT The method comprises the steps of carrying out a first treatment on the surface of the Therefore, the field effect transistor module 100 can be turned off, and current reverse filling can be prevented.
Referring to fig. 4, in an embodiment of the present invention, the second comparing unit 410 may include a third adder 411, a second comparator 412 and a flip-flop 413. The adder end of the third adder 411 may be electrically connected to a predetermined third voltage end, and the added end thereof may be electrically connected to the drain of the fet module 100. The third adder 411 can be used to generate the lower limit voltage U L . In this embodiment, the voltage at the preset third voltage terminal is-11 mV, so that the lower limit voltage U is known L Output voltage V OUT -11mV. The negative input end of the second comparator 412 may be electrically connected to the input voltage end, and the positive input end thereof may be electrically connected to the output end of the third adder 411, i.e. the lower limit voltage U L . The second comparator 412 can compare the input voltage V BAT And lower limit voltage U L . The flip-flop 414 may be an SR flip-flop, the reset terminal thereof may be electrically connected to the output terminal of the second comparator 412, the set terminal thereof may be electrically connected to the output terminal of the first comparator 210, and the negative output terminal thereof may be electrically connected to the gate of the second fet 420. In the present embodiment, when the input voltage V BAT And output voltage V OUT Is within a preset third voltage range, i.e. the input voltage V BAT Less than the lower limit voltage U L When there is a risk that current reverse current sinking occurs. At this time, the output of the second comparator 412 is high, and the output of the first comparator 212 is low; therefore, the set terminal of the SR flip-flop is input low, the reset terminal is input high, and the negative output terminal outputs low. At this time, the first fet 220 is turned off; the second fet 420 is turned on; the gate of the FET module 100 may be connected to the input voltage V BAT Thus, the gate-source voltage of the fet module 100 is 0, and the fet module 100 is turned off to prevent current reverse-filling.
TABLE 1 schematic table of preset voltage difference intervals
Figure SMS_1
Referring to Table 1, in one embodiment of the present invention, the input voltage V BAT And output voltage V OUT The voltage difference of (2) can be divided into 3 preset voltage difference sections, namely a first voltage section, a second voltage section and a third voltage section.
Referring to fig. 1 to 4, in one embodiment of the present invention, the first voltage interval is a maximum gate-source voltage interval. When the input voltage V BAT And output voltage V OUT When the voltage difference of (2) is within the first voltage interval, i.e. the input voltage V BAT -output voltage V OUT And the conducting voltage drop voltage of the field effect transistor module is more than 50mV. At this time, the input voltage V BAT Upper limit voltage U H Lower limit voltage U L . The first comparator 212 outputs a high level, and the inverter 213 outputs a low level, so that the first fet 220 is turned on; the second comparator 412 outputs a low level and the SR flip-flop outputs a high level, so that the second fet 420 is turned off. It can be seen that the gate of the first field effect device 100 can be connected to the maximum gate-source voltage U MAX A reduction in the on-resistance of the first field effect device 100 can be achieved.
Referring to fig. 1 to 4, in one embodiment of the present invention, the second voltage interval includes a linear adjustment region and a stabilization region. When the input voltage V BAT And output voltage V OUT When the voltage difference of (2) is within the second voltage range, i.e., -11mV < input voltage V BAT -output voltage V OUT < 50mV. At this time, the upper limit voltage U H > input voltage V BAT Lower limit voltage U L . The first comparator 212 outputs a low level, and the inverter 213 outputs a high level, so that the first fet 220 is turned off; the second comparator 412 outputs a low level and the SR flip-flop outputs a high level, so that the second fet 420 is turned off. In the present embodiment, the gate voltage U of the first field effect device 100 D The following formula may be satisfied:
U D ＝U′ D +M×(V BAT -U M )
wherein the method comprises the steps of，U′ D Represents the historical gate voltage of the fet module 100, i.e., the gate voltage of the fet module 100 at the previous time, and M represents the amplification factor of the differential amplifier.
Further analysis, when V BAT ＞U M When, i.e. V BAT -V OUT At > 20mV, gate voltage U D Gradually linearly increasing; when V is BAT ≤U M When, i.e. V BAT -V OUT When less than or equal to 20mV, the grid voltage U D Gradually linearly decreasing; thereby realizing the maintenance of the on-voltage drop voltage of the fet module 100 at 20mV.
Referring to fig. 1 to 4, in an embodiment of the invention, the third voltage interval is an off-region. When the input voltage V BAT And output voltage V OUT When the voltage difference of (2) is within the third voltage range, i.e. the input voltage V BAT -output voltage V OUT When the voltage drop voltage of the field effect transistor module is 11mV in the reverse direction, the circuit has reverse current. At this time, the upper limit voltage U H Lower limit voltage U L > input voltage V BAT . The first comparator 212 outputs a level, and the inverter 213 outputs a high level, so that the first fet 220 is turned off; the second comparator 412 outputs a high level and the SR flip-flop outputs a low level, so that the second fet 420 is turned on. It can be seen that the gate of the first field effect device 100 can be connected to the input voltage V BAT . Therefore, the gate-source voltage of the first field-effect device 100 is 0, so that the first field-effect device 100 is turned off, and current reverse-filling is prevented.
In summary, the present invention provides a control circuit for preventing reverse current flowing, which can be applied to the technical field of electronic circuits. According to the invention, the on and off of the circuit can be controlled according to the voltage difference between the input voltage and the output voltage so as to prevent current reverse filling; in addition, the invention can also adjust the conduction voltage drop voltage of the field effect transistor according to the change of the rear load resistance, thereby ensuring the stability of the rear voltage. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The structures have been described herein in general terms as being helpful in understanding the details of the invention. Furthermore, various specific details have been set forth in order to provide a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that an embodiment of the invention can be practiced without one or more of the specific details, or with other apparatus, systems, assemblies, methods, components, materials, parts, and/or the like. In other instances, well-known structures, materials, and/or operations are not specifically shown or described in detail to avoid obscuring aspects of embodiments of the invention.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. A control circuit for preventing reverse current flow, comprising:
the field effect transistor module is electrically connected with the input voltage end of the current signal;
the positive input end of the first comparison module is electrically connected with the input voltage end, the negative input end of the first comparison module is electrically connected with the drain electrode of the field effect transistor module, and the output end of the first comparison module is electrically connected with the grid electrode of the field effect transistor module and is used for starting the field effect transistor module;
the positive input end of the differential module is electrically connected with the input voltage end, the negative input end of the differential module is electrically connected with the drain electrode of the field effect transistor module, and the output end of the differential module is electrically connected with the grid electrode of the field effect transistor module and is used for adjusting the grid source voltage of the field effect transistor module; and
and the negative input end of the second comparison module is electrically connected with the input voltage end, the positive input end of the second comparison module is electrically connected with the drain electrode of the field effect transistor module, and the output end of the second comparison module is electrically connected with the grid electrode of the field effect transistor module and is used for turning off the field effect transistor module.
2. The anti-current back-filling control circuit of claim 1, wherein the first comparison module comprises:
the positive input end of the first comparison unit is electrically connected with the input voltage end, and the negative input end of the first comparison unit is electrically connected with the drain electrode of the field effect transistor module; and
the source electrode of the first field effect tube is electrically connected with the gate-source voltage end, the drain electrode of the first field effect tube is electrically connected with the grid electrode of the field effect tube module, and the grid electrode of the first field effect tube is electrically connected with the output end of the first comparison unit;
when the voltage difference between the input voltage end and the drain electrode of the field effect transistor module is located in a preset first voltage interval, the first comparison unit outputs a low level to start the first field effect transistor.
3. The current anti-reverse-filling control circuit according to claim 2, wherein the first comparing unit includes:
the first adder is electrically connected with a preset first voltage end and is electrically connected with the drain electrode of the field effect transistor module by the addition end, and the first adder is used for generating an upper limit voltage;
the positive input end of the first comparator is electrically connected with the input voltage end, and the negative input end of the first comparator is electrically connected with the output end of the first adder; and
and the input end of the inverter is electrically connected with the output end of the first comparator, and the output end of the inverter is electrically connected with the grid electrode of the first field effect transistor.
4. The anti-current anti-reverse-fill control circuit of claim 1, wherein the differential module comprises:
the positive input end of the differential unit is electrically connected with the input voltage end, and the negative input end of the differential unit is electrically connected with the drain electrode of the field effect tube module; and
and the negative input end of the feedback unit is electrically connected with the output end of the differential unit, and the output end of the feedback unit is electrically connected with the grid electrode of the field effect transistor module.
When the voltage difference between the input voltage end and the drain electrode of the field effect transistor module is located in a preset second voltage interval, the differential unit adjusts the gate-source voltage of the field effect transistor module.
5. The current anti-reverse-filling control circuit according to claim 4, wherein the differential unit comprises:
the adder is electrically connected with a preset second voltage end and is electrically connected with the drain electrode of the field effect transistor module, and the second adder is used for generating differential voltage; and
and the positive input end of the differential amplifier is electrically connected with the input voltage end, the negative input end of the differential amplifier is electrically connected with the output end of the second adder, and the differential amplifier is used for amplifying the difference value between the input voltage end and the differential voltage.
6. The control circuit of claim 5, wherein the gate voltage U of the FET module when the voltage difference between the input voltage terminal and the drain of the FET module is within the second voltage range D The following formula is satisfied:
U D ＝U′ D +M×(V BAT -U M )
wherein U 'is' D Representing the historical grid voltage value of the field effect transistor module, M representing the amplification factor of the differential amplifier, V BAT Representing the voltage value of the input voltage terminal, U M Representing the differential voltage.
7. The anti-current back-filling control circuit according to claim 5, wherein the gate voltage of the fet module increases linearly when the voltage value of the input voltage terminal is greater than the differential voltage.
8. The anti-current foldback control circuit of claim 5, wherein the gate voltage of the fet module decreases linearly when the voltage value at the input voltage terminal is less than or equal to the differential voltage.
9. The anti-current back-filling control circuit of claim 2, wherein the second comparison module comprises:
the negative input end of the second comparison unit is electrically connected with the input voltage end, and the positive input end of the second comparison unit is electrically connected with the drain electrode of the field effect transistor module; and
the source electrode of the second field effect tube is electrically connected with the input voltage end, the drain electrode of the second field effect tube is electrically connected with the grid electrode of the field effect tube module, and the grid electrode of the second field effect tube is electrically connected with the output end of the second comparison unit;
when the voltage difference between the input voltage end and the drain electrode of the field effect transistor module is in a preset third voltage interval, the second comparison unit outputs a high level for starting the second field effect transistor.
10. The current anti-reverse-filling control circuit according to claim 9, wherein the second comparing unit comprises:
the adder is electrically connected with a preset third voltage end and is electrically connected with the drain electrode of the field effect transistor module, and the third adder is used for generating a lower limit voltage;
a second comparator, the negative input end of which is electrically connected with the input voltage end, and the positive input end of which is electrically connected with the output end of the third adder; and
the reset end of the trigger is electrically connected with the output end of the second comparator, the set end of the trigger is electrically connected with the output end of the first comparison unit, and the negative output end of the trigger is electrically connected with the grid electrode of the second field effect tube.
CN202310321340.3A 2023-03-29 2023-03-29 Control circuit for preventing current from flowing reversely Pending CN116316515A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202310321340.3A CN116316515A (en) 2023-03-29 2023-03-29 Control circuit for preventing current from flowing reversely

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310321340.3A CN116316515A (en) 2023-03-29 2023-03-29 Control circuit for preventing current from flowing reversely

Publications (1)

Publication Number Publication Date
CN116316515A true CN116316515A (en) 2023-06-23

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Family Applications (1)

Application Number Title Priority Date Filing Date
CN202310321340.3A Pending CN116316515A (en) 2023-03-29 2023-03-29 Control circuit for preventing current from flowing reversely

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