CN116314338A - Semiconductor structure and preparation method thereof - Google Patents
Semiconductor structure and preparation method thereof Download PDFInfo
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- CN116314338A CN116314338A CN202310558950.5A CN202310558950A CN116314338A CN 116314338 A CN116314338 A CN 116314338A CN 202310558950 A CN202310558950 A CN 202310558950A CN 116314338 A CN116314338 A CN 116314338A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 58
- 238000002360 preparation method Methods 0.000 title abstract description 8
- 238000005468 ion implantation Methods 0.000 claims abstract description 342
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 150000002500 ions Chemical class 0.000 claims description 28
- 238000000034 method Methods 0.000 claims description 19
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Abstract
The invention relates to the technical field of semiconductors, and provides a semiconductor structure and a preparation method thereof. A semiconductor structure includes a drain; an N+ type substrate layer, a first P type base region, a second P type base region and a third P type base region; a first p+ ion implantation region, a third p+ ion implantation region, a fourth p+ ion implantation region; the first N+ ion implantation region is connected with the first P-type base region and the second P-type base region; the first N+ ion implantation region is used as a part of a conductive channel of the semiconductor structure; a second P+ ion implantation region; the third P+ ion implantation region is arranged between the second N+ ion implantation region and the first N+ ion implantation region; a third n+ ion implantation region; a first gate region; a second gate region; and a source electrode. The invention has the characteristics of improving the avalanche current path, reducing the performance degradation of the body diode and improving the high reliability of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a semiconductor structure and a preparation method thereof.
Background
Silicon carbide material is used as a wide forbidden band semiconductor material, has more excellent characteristics than silicon material, and has a forbidden band width of 3 times that of silicon, a critical breakdown electric field of 10 times that of silicon and a thermal conductivity of 4 times that of silicon. The power device made of the silicon carbide material has higher working frequency, smaller loss and higher working temperature and power density than the silicon device, and is suitable for being applied to power electronic devices with high voltage, high power, high temperature and radiation resistance.
In recent years, silicon carbide metal oxide field effect transistors (SiC MOSFETs) have been pushed to the power device market. SiC MOSFETs have higher operating temperatures, lower switching losses, and higher switching frequencies than conventional silicon-on-insulator bipolar field effect transistors (Si IGBTs) with the same voltage withstand capability. Although SiC MOSFETs are excellent in performance, the performance degradation of body diodes in repeated avalanche states is serious inside SiC MOSFET devices due to material defects, dislocations, and the like, reducing device reliability. Meanwhile, the degradation of the performance of the body diode leads to the difference of the performance stability of the device, and the risk of an application system is greatly increased. How to solve the performance degradation problem of the SiC MOSFET in an avalanche state, and improve the stability of the device becomes a technical problem to be solved urgently.
Disclosure of Invention
In order to solve at least one technical problem in the background art, the invention provides a semiconductor structure, wherein the difference of pinch-off capability of a JFET and a MOSFET channel is utilized to change an avalanche current path of a device by integrating a depletion type JFET structure beside a SiC MOSFET, so that the avalanche resistance and the device reliability of the SiC MOSFET device are improved.
According to a first aspect of the present invention, there is provided a semiconductor structure, the structure comprising:
A drain electrode;
an N+ type substrate layer in ohmic contact with the drain electrode;
the N-type epitaxial layer is positioned on the N+ type substrate layer, and a first P type base region, a second P type base region and a third P type base region which are distributed at intervals are sequentially formed on one side of the N+ type substrate layer;
the first P+ ion implantation region, the third P+ ion implantation region and the fourth P+ ion implantation region respectively cover partial top surfaces of the first P-type base region, the second P-type base region and the third P-type base region;
the first N+ ion implantation region is connected with the first P-type base region and the second P-type base region and covers partial top surfaces of the first P-type base region and the second P-type base region; the first N+ ion implantation region is used as a part of a conductive channel of the semiconductor structure;
a second P+ ion implantation region covering a part of the top surface of the first N+ ion implantation region;
the second N+ ion implantation region covers the top surface of the second P-type base region part, and the third P+ ion implantation region is arranged between the second N+ ion implantation region and the first N+ ion implantation region;
the third N+ ion implantation region covers the third P-type base region and is positioned at one side of the fourth P+ ion implantation region close to the second P-type base region;
the first grid region is positioned above the first N+ ion implantation region and covers the top surface of the second P+ ion implantation region;
A second gate region crossing over the second P-type base region and the third P-type base region;
and the source electrode is positioned above the N-type epitaxial layer and covers the first gate electrode region and the second gate electrode region.
Further, the bottom surface of the first n+ ion implantation region is lower than the bottom surfaces of the first p+ ion implantation region, the second p+ ion implantation region and the third p+ ion implantation region, respectively;
the bottom surface of the second N+ ion implantation region is lower than the bottom surface of the third P+ ion implantation region;
and the bottom surface of the third N+ ion implantation region is lower than the bottom surface of the fourth P+ ion implantation region.
Further, the first P+ ion implantation region, the second P+ ion implantation region, the third P+ ion implantation region and the fourth P+ ion implantation region are all flush with the top surface of the N-type epitaxial layer;
the first N+ ion implantation region, the second N+ ion implantation region, the third N+ ion implantation region and the fourth P+ ion implantation region are all flush with the top surface of the N-type epitaxial layer.
Further, the first n+ ion implantation region has a U-shaped structure, and the second n+ ion implantation region and the third n+ ion implantation region are both square structures.
Furthermore, the doping medium of the first, second and third P-type base regions are P-type ions with the same doping concentration, and the doping concentration range of the P-type ions is 1e16-5e18cm -3 。
Furthermore, the doping mediums of the first P+ ion implantation region, the second P+ ion implantation region, the third P+ ion implantation region and the fourth P+ ion implantation region are all P-type ions with the same doping concentration, and the doping concentration range of the P-type ions is 6e18-5e19cm -3 。
Further, the doping mediums of the first N+ ion implantation region, the second N+ ion implantation region and the third N+ ion implantation region are N-type ions with the same doping concentration, and the doping concentration range of the N-type ions is 1e17-1e19cm -3 。
Further, the first gate region comprises a first gate and a first insulating medium layer;
the first grid electrode covers part of the top surface of the second P+ ion implantation region;
and the first insulating medium layer wraps the periphery of the first grid electrode so as to enable the first grid electrode to be in insulating contact with the source electrode.
Further, the second gate region comprises a gate oxide layer, a second gate and a second insulating dielectric layer,
the grid oxide layer spans the second P-type base region and the third P-type base region and covers partial top surfaces of the second N+ ion implantation region and the third N+ ion implantation region;
the second grid electrode is positioned on the grid electrode oxide layer;
and the second insulating medium layer wraps the periphery of the second grid electrode and the grid electrode oxidation layer so as to enable the second grid electrode to be in insulating contact with the source electrode.
Further, the semiconductor structure further includes: the first source ohmic contact region, the second source ohmic contact region and the third source ohmic contact region are sequentially distributed at intervals;
the first source ohmic contact region covers the top surface of the first P+ ion implantation region and part of the top surface of the first N+ ion implantation region;
the second source ohmic contact region is arranged between the first gate region and the second gate region and covers the top surface of the third P+ ion implantation region and part of the top surfaces of the first N+ ion implantation region and the second N+ ion implantation region;
and the third source ohmic contact region covers part of the top surface of the third N+ ion implantation region and the top surface of the fourth P+ ion implantation region.
According to a second aspect of the present invention, there is also provided a method for producing a semiconductor, comprising:
s100, providing an N+ type substrate, and growing an N-type epitaxial layer on the N+ type substrate;
s200, P-type ion implantation is carried out on the surface, far away from the N+ type substrate, of the N-type epitaxial layer, and a first initial P-type base region, a second initial P-type base region and a third initial P-type base region which are distributed at intervals are formed in sequence;
s300, performing N-type ion implantation on partial top surfaces of the first initial P-type base region and the second initial P-type base region to form a first initial N+ ion implantation region connected with the first initial P-type base region and the second initial P-type base region; n-type ion implantation is carried out on partial top surfaces of the second initial P-type base region and the third initial P-type base region, so that a second initial N+ ion implantation region and a third initial ion implantation region are formed;
S400, P-type ion implantation is carried out on partial top surfaces of the first initial P-type base region, the second initial P-type base region and the third initial P-type base region, and a first P+ ion implantation region, a third P+ ion implantation region and a fourth P+ ion implantation region are respectively formed; p-type ion implantation is carried out on part of the top surface of the first initial N+ ion implantation region, so that a second P+ ion implantation region is formed;
s500, carrying out high-temperature annealing on the semiconductor structure after P-type and N-type ion implantation;
s600, forming a first gate region on the first initial N+ ion implantation region and a second gate region crossing over the second initial P-type base region and the third initial P-type base region;
s700, depositing and forming a source electrode covering the first gate region and the second gate region on the N-type epitaxial layer;
and S800, depositing a drain electrode on one side of the N+ type substrate layer far away from the N-type epitaxial layer.
Further, the S600 includes:
s610, growing an initial gate oxide layer on the N-type epitaxial layer;
s620, etching the initial gate oxide layer to form a gate oxide layer which spans the second P-type base region and the third P-type base region, wherein the gate oxide layer covers partial top surfaces of the second N+ ion implantation region and the third N+ ion implantation region;
S630, depositing a metal material on the surface of the N-type epitaxial layer to form a gate layer, and etching the gate layer to form a first gate positioned on the top surface of the second P+ ion implantation region and a second gate positioned on the top surface of the gate oxide layer;
and S640, depositing dielectric layer films on the surfaces of the N-type epitaxial layer and the first grid electrode and the second grid electrode, and etching the dielectric layer films to form a first insulating dielectric layer wrapping the first grid electrode and a second insulating dielectric layer wrapping the second grid electrode and the grid electrode oxide layer.
Further, after S640, before S700, the preparation method further includes:
and S650, depositing ohmic contact metal materials on the residual surface of the N-type epitaxial layer and annealing to form a first source ohmic contact region, a second source ohmic contact region and a third source ohmic contact region which are spaced apart.
By the technical scheme of the invention, the following technical effects can be obtained:
(1) The SiC MOSFET with the depletion type JFET structure can change the avalanche current discharging path, reduce the performance degradation of a diode of the MOSFET structure, improve the avalanche resistance of the device and improve the reliability of the device;
(2) The manufacturing process is compatible with the main stream SiC MOSFET manufacturing process, has simple process flow and low cost, and is suitable for large-scale production.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a semiconductor structure according to the present invention;
FIG. 2 is a schematic view of regions of a semiconductor structure according to the present invention;
FIG. 3 is a schematic diagram of a conventional body diode structure of a SiC MOSFET device in an avalanche state;
FIG. 4 is a schematic diagram of a current path of a semiconductor structure of the present invention in an avalanche state;
FIG. 5 is a schematic view of a current path of a semiconductor structure of the present invention in an avalanche state in an experiment;
FIGS. 6 to 14 are schematic views showing the structure of intermediate products of steps in a method for fabricating a semiconductor structure according to the present invention;
reference numerals: 1-N+ substrate layer, 2-N-type epitaxial layer, 3-first P type base region, 4-second P type base region, 5-third P type base region, 6-first N+ ion implantation region, 7-second N+ ion implantation region, 8-third N+ ion implantation region, 9-first P+ ion implantation region, 10-second P+ ion implantation region, 11-third P+ ion implantation region, 12-fourth P+ ion implantation region, 13-first source ohmic contact region, 14-second source ohmic contact region, 15-third source ohmic contact region, 16-first gate, 17-second gate, 18-gate oxide layer, 19-first insulating medium layer, 20-second insulating medium layer, 21-source, 22-drain ohmic contact layer, 23-drain, 24-first end, 25-second end, 26-connection.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that the terms "first," "second," "third," and "fourth," etc. in the description and claims of the present application are used for distinguishing between different objects and not for describing a particular sequential order. The terms "comprising" and "having" and any variations thereof, in embodiments of the present application, are intended to cover non-exclusive inclusions.
In the related art, as shown in fig. 3 of the specification, a body diode structure of a conventional SiC MOSFET device and a current path in an avalanche state, when the conventional SiC MOSFET structure is subjected to avalanche breakdown, a breakdown point is located in the body diode, which easily causes degradation of the body diode, causes drift of electrical characteristics, and reduces the reliability of the device. Therefore, the invention provides a semiconductor structure which is different from the traditional SiC MOSFET device and solves the problem of performance degradation of the SiC MOSFET device in an avalanche state.
Fig. 1 is a schematic diagram of a semiconductor structure according to an embodiment of the present invention, and as shown in fig. 1, the semiconductor structure provided in the present invention includes:
a drain electrode 23;
an n+ type substrate layer 1 in ohmic contact with the drain electrode 23;
the N-type epitaxial layer 2 is positioned on the N+ type substrate layer 1, and a first P-type base region 3, a second P-type base region 4 and a third P-type base region 5 which are distributed at intervals are sequentially formed on one side far away from the N+ type substrate layer 1;
the first P+ ion implantation region 9, the third P+ ion implantation region 11 and the fourth P+ ion implantation region 12 respectively cover partial top surfaces of the first P-type base region 3, the second P-type base region 4 and the third P-type base region 5;
the first N+ ion implantation region 6 is connected with the first P-type base region 3 and the second P-type base region 4 and covers partial top surfaces of the first P-type base region 3 and the second P-type base region 4; the first n+ ion implantation region 6 serves as a partial conduction channel of the semiconductor structure;
a second p+ ion implantation region 10 covering a part of the top surface of the first n+ ion implantation region 6;
the second N+ ion implantation region 7 covers part of the top surface of the second P-type base region 4, and a third P+ ion implantation region 11 is arranged between the second N+ ion implantation region 6 and the first P+ ion implantation region;
the third N+ ion implantation region 8 covers the third P-type base region 5 and is positioned at one side of the fourth P+ ion implantation region 12 close to the second P-type base region 4;
The first gate region is positioned above the first N+ ion implantation region 6 and covers the top surface of the second P+ ion implantation region 10;
a second gate region crossing over the second P-type base region 4 and the third P-type base region 5;
the source electrode 21 is located above the N-type epitaxial layer 2 and covers the first gate region and the second gate region.
In this embodiment, the semiconductor structure is sequentially distributed with a drain electrode 23, an n+ type substrate layer 1, an N-type epitaxial layer 2, a P-type base region, an n+ ion implantation region, a p+ ion implantation region, a gate region and a source electrode 21 from bottom to top; the P-type base region, the n+ ion implantation region and the p+ ion implantation region are wrapped by the N-type epitaxial layer 2, the P-type base region comprises a first P-type base region 3, a second P-type base region 4 and a third P-type base region 5,N + ion implantation region comprises a first n+ ion implantation region 6, a second n+ ion implantation region 7 and a third n+ ion implantation region 8, and the gate region comprises a first gate region and a second gate region.
The drain electrode 23 is disposed at the bottom layer of the semiconductor structure, and optionally, the drain electrode 23 is made of metal materials such as Ti, ni, ag, etc., which can be specifically selected according to actual requirements. Optionally, a drain ohmic contact layer 22 is formed on the surface of the drain electrode 23 near the substrate layer, and the material is a metal material such as Ti and Ni, and the specific doping concentration value can be selected according to practical requirements.
The n+ type substrate layer 1 is in ohmic contact with the drain electrode 23 through the drain ohmic contact layer 22. The N+ type substrate layer 1 is a substrate layer formed by doping N type ions in a silicon carbide material, and optionally, the N+ type substrate layer 1 is doped with N as a medium with doping concentration of 1e19-5e19cm -3 The thickness of the substrate ranges from 200 to 400 micrometers, and the specific doping concentration valueCan be selected according to actual requirements.
The N-type epitaxial layer 2 is formed by epitaxial growth on the surface of the n+ -type substrate layer 1 remote from the drain electrode 23. Optionally, the doping medium of the N-type epitaxial layer 2 is N, and the doping concentration is 1e14-1e17cm -3 The thickness of the epitaxial layer is 2-40 micrometers, and the specific doping concentration value can be selected according to actual requirements.
The P-type base region, the n+ type ion implantation region and the p+ ion implantation region are all disposed in the N-type epitaxial layer 2, and the specific structure is not limited. The P-type base region comprises a first P-type base region 3, a second P-type base region 4 and a third P-type base region 5 which are arranged at intervals, and optionally, the bottoms of the first P-type base region 3, the second P-type base region 4 and the third P-type base region 5 are flush. The doping medium of the first P-type base region 3, the second P-type base region 4 and the third P-type base region 5 are P-type ions with the same doping concentration, and the doping concentration range of the P-type ions is 1e16-5e18cm -3 The specific doping concentration value can be selected according to actual requirements. In this embodiment, the doping medium of the P-type base region is Al ions.
It should be noted that, based on the position design of the P-type base region, the n+ type ion implantation region and the p+ ion implantation region, as shown in fig. 4, a first body diode is formed at the first P-type base region 3, a second body diode is formed at the second P-type base region 4, and a third body diode is formed at the third P-type base region 5.
The N+ ion implantation region comprises a first N+ ion implantation region 6, a second N+ ion implantation region 7 and a third N+ ion implantation region 8 which are distributed at intervals. The first n+ ion implantation region 6, the second n+ ion implantation region 7 and the third n+ ion implantation region 8 are all flush with the top surface of the N-type epitaxial layer 2. The doping mediums of the first N+ ion implantation region 6, the second N+ ion implantation region 7 and the third N+ ion implantation region 8 are N-type ions with the same doping concentration, and the doping concentration range of the N-type ions is 1e17-1e19cm -3 The specific doping concentration value can be selected according to actual requirements.
The first n+ ion implantation region 6 includes a first end 24, a connection portion 26, and a second end 25, the first end 24 is located above the first P-type base region 3, the second end 25 is located above the second P-type base region 4, and the connection portion 26 connects the first end 24 and the second end 25 and bridges the first P-type base region 3 and the second P-type base region 4. In this embodiment, the first n+ ion implantation region 6 has a U-shaped structure.
The second n+ ion implantation region 7 and the third n+ ion implantation region 8 are both flush with the bottom surface of the first n+ ion implantation region 6. Optionally, the depths of the three n+ ion implantation regions are the same, and the depths are perpendicular to the interval setting direction of the three n+ ion implantation regions. In this embodiment, the second n+ ion implantation region 7 and the third n+ ion implantation region 8 each have a square structure.
The p+ ion implantation regions comprise a first p+ ion implantation region 9, a second p+ ion implantation region 10, a third p+ ion implantation region 11 and a fourth p+ ion implantation region 12 which are arranged at intervals, and the first p+ ion implantation region 9, the second p+ ion implantation region 10, the third p+ ion implantation region 11 and the fourth p+ ion implantation region 12 are all flush with the top surface of the N-type epitaxial layer 2. Alternatively, the four p+ ion implantation regions have the same depth. Optionally, the bottom surfaces of the four p+ ion implantation regions are flush. The doping mediums of the first P+ ion implantation region 9, the second P+ ion implantation region 10, the third P+ ion implantation region 11 and the fourth P+ ion implantation region 12 are all P-type ions with the same doping concentration, and the doping concentration range of the P-type ions is 6e18-5e19cm -3 The specific doping concentration value can be selected according to actual requirements. It should be noted that the doping concentration of P-type ions in the p+ ion implantation region is different from that of P-type ions in the P-type base region, and the doping concentration values are determined according to the required device withstand voltage design.
Wherein the second p+ ion implantation region 10 is located above the connection portion 26 in the first n+ ion implantation region 6 and covers the top surface of the connection portion 26; the sidewall of the second p+ ion implantation region 10 is surrounded by the first n+ ion implantation region 6.
The first p+ ion implantation region 9 is located above the first P-type base region 3, and the first p+ ion implantation region 9 is adjacent to the first n+ ion implantation region 6. The third p+ ion implantation region 11 connects the first n+ ion implantation region 6 and the second n+ ion implantation region 7; the fourth p+ ion implantation region 12 is located above the third P-type base region 5 and is adjacent to the third n+ ion implantation region 8. It will be appreciated that the third P-type base region 5, the third n+ ion implantation region 8 and the fourth p+ ion implantation region 12 form a first structure of the MOSFET, and that the portion of the second P-type base region 4, the second n+ ion implantation region 7 and the portion of the third p+ ion implantation region 11 form a second structure of the MOSFET, and that the first structure is symmetrical to the second structure.
Wherein the bottom surface of the first n+ ion implantation region 6 is lower than the bottom surfaces of the first p+ ion implantation region 9, the second p+ ion implantation region 10 and the third p+ ion implantation region 11, respectively; the bottom surface of the second N+ ion implantation region 7 is lower than the bottom surface of the third P+ ion implantation region 11; the bottom surface of the third n+ ion implantation region 8 is lower than the bottom surface of the fourth p+ ion implantation region 12. That is, the bottom surfaces of the three P-type base regions are lower than the bottom surfaces of the three n+ ion implantation regions, and the bottom surfaces of the three n+ ion implantation regions are lower than the bottom surfaces of all the p+ ion implantation regions.
The gate region comprises a first gate region and a second gate region, wherein the first gate region further comprises a first gate electrode 16 and a first insulating medium layer 19, the first gate electrode 16 is located above the second p+ ion implantation region 10 and covers a part of the top surface of the second p+ ion implantation region 10, i.e. the length of the second p+ ion implantation region 10 in the horizontal direction is greater than the length of the first gate electrode 16.
The first insulating dielectric layer 19 is located above the first n+ ion implantation region 6, and wraps the upper surface and the left and right sides of the first gate electrode 16, so that the first gate electrode 16 is in insulating contact with the source electrode 21. The length of the second p+ ion implantation region 10 is smaller than the length of the first insulating dielectric layer 19, and the length of the first insulating dielectric layer 19 is smaller than the length of the first n+ ion implantation region 6. The first gate 16 is a gate of a depletion JFET structure.
The second gate region includes a gate oxide layer 18, a second gate 17, and a second insulating dielectric layer 20, where the gate oxide layer 18 spans the second P-type base region 4 and the third P-type base region 5 and covers part of the top surfaces of the second n+ ion implantation region 7 and the third n+ ion implantation region 8. Specifically, one side of the gate oxide layer 18 covers part of the top surfaces of the second P-type base region 4 and the second n+ ion implantation region 7, the opposite side covers part of the top surfaces of the third P-type base region 5 and the third n+ ion implantation region 8, and the middle region of the gate oxide layer 18 covers part of the top surface of the N-epitaxial layer.
The second gate 17 is located on the gate oxide layer 18 and covers the top surface of the gate oxide layer 18. The second gate 17 is a gate of a silicon carbide MOSFET structure, and works independently of the first gate 16, and does not affect each other.
The second insulating dielectric layer 20 wraps the outer peripheries of the second gate electrode 17 and the gate oxide layer 18 so as to make insulating contact between the second gate electrode 17 and the source electrode 21. Specifically, the sidewall and the upper surface of the second gate 17, and the sidewall of the gate oxide layer 18 are all surrounded by the second insulating dielectric layer 20.
Further, the semiconductor structure further includes a first source ohmic contact region 13, a second source ohmic contact region 14, and a third source ohmic contact region 15 sequentially spaced apart from each other. The first source ohmic contact region 13 covers the top surface of the first p+ ion implantation region 9 and a portion of the top surface of the first n+ ion implantation region 6; the second source ohmic contact region 14 is disposed between the first gate region and the second gate region, and covers the top surface of the third p+ ion implantation region 11 and part of the top surfaces of the first n+ ion implantation region 6 and the second n+ ion implantation region 7; the third source ohmic contact region 15 covers a portion of the top surface of the third n+ ion implantation region 8 and the top surface of the fourth p+ ion implantation region 12.
Specifically, the first insulating dielectric layer 19 is disposed between the first source ohmic contact region 13 and the second source ohmic contact region 14, and the second insulating dielectric layer 20 is disposed between the second source ohmic contact region 14 and the third source ohmic contact region 15; the first source ohmic contact region 13 overlaps the first p+ ion implantation region 9 and a portion of the first n+ ion implantation region 6, the second source ohmic contact region 14 overlaps the second p+ ion implantation region 10, a portion of the first n+ ion implantation region 6 and a portion of the second n+ ion implantation region 7, and the third source ohmic contact region 15 overlaps the third p+ ion implantation region 11 and a portion of the third n+ ion implantation region 8, so that the device on-current capability can be improved, and conduction of parasitic BJTs of MOSFETs can be effectively suppressed. Alternatively, the materials of the three source electrode 21 ohmic contact regions include, but are not limited to, a metal material such as Ti, ni, or W.
The source electrode 21 is disposed above the N-epi layer 2 and covers the first gate region, the second gate region and the three source electrode 21 ohmic contact regions, and optionally, the source electrode 21 is made of a metal material such as Al, alSi, alCu or AlSiCu.
In this embodiment, in the above semiconductor structure, a left side structure in the semiconductor structure forms a depletion JFET structure, where the left side is a side where the first P-type base region 3 is located; the right side structure of the semiconductor structure forms a silicon carbide MOSFET structure, and the right side is one side of the position where the third P-type base region 5 is located. It is understood that the JFET structure shares the drain 23 and source 21 with the MOSFET structure.
In the depletion JFET structure, the left regions of the first p+ ion implantation region 9 and the third p+ ion implantation region 11 are used as a part of the ohmic contact region of the source 21, and are located in the P-type base region, the second p+ ion implantation region 10 is located in the first n+ ion implantation region 6, and the first n+ ion implantation region 6 formed between the first P-type base region 3 and the second p+ ion implantation region 10 forms a conductive channel of the depletion JFET structure. When the semiconductor structure is in an avalanche state, current flows from the drain electrode 23 into the connecting portion 26 of the first n+ ion implantation region 6 through the N-type epitaxial layer 2 between the n+ type substrate layer 1, the first P-type base region 3 and the second P-type base region 4 in sequence, and then the two sets of currents flow through the first end portion 24 and the second end portion 25 to drain respectively, and in this process, the drain current does not enter the first n+ ion implantation region 6 through the first P-type base region 3 or the second P-type base region 4, so that the influence on the performance of the first body diode is avoided.
In the MOSFET structure, the second P-type base region 4, the second n+ ion implantation region 7 and the bottom surface of the gate oxide layer 18 form a conductive channel in the horizontal direction, and similarly, the third P-type base region 5, the third n+ ion implantation region 8 and the bottom surface of the gate oxide layer 18 form a conductive channel in the horizontal direction in the overlapping portion. When the semiconductor structure is in an avalanche state, current is not discharged basically through a conductive channel between the second P-type base region 4 and the third P-type base region 5, that is, when the semiconductor structure provided by the invention discharges current, almost all current is discharged through the first n+ ion implantation region 6, and at the moment, the current can be considered to be not discharged through the second body diode and the third body diode, so that the problem of performance degradation of the SiC MOSFET device in the avalanche state can be solved.
In the semiconductor structure, the depletion type JFET structure and the MOSFET structure have two different driving voltages and channel conduction capacity, and the closing and opening of the devices can be realized simultaneously by adjusting different driving voltage differences of the two devices. Meanwhile, the JFET structure utilizes the depletion of a PN junction end to realize the closing of the device, and the MOSFET structure utilizes the formation and disappearance of an inversion layer below a gate oxide layer to realize the opening and closing of the device, so that the channel conduction capacity and the closing capacity of the two structures are different. When the silicon carbide JFET device and the SiC MOSFET device are closed, the silicon carbide JFET device and the SiC MOSFET device have two different channel depletion capacities, so that the leakage path of current passing through the body diode in an avalanche state is effectively solved, the avalanche resistance of the device is improved, and the reliability of the device is improved.
Fig. 4 shows a schematic diagram of a current drain path of the semiconductor structure in an avalanche state, as shown in fig. 4, a-18V driving voltage is applied to a gate of a depletion type JFET structure in the semiconductor structure to realize JFET turn-off, and a-5V driving voltage is applied to a gate of a MOSFET structure to realize MOSFET turn-off, so as to obtain a schematic diagram of simulation results as shown in fig. 5. As can be seen from fig. 4 and fig. 5, the semiconductor structure is in an avalanche state, the current is almost completely discharged from the conductive channel of the depletion type JFET structure and does not pass through the body diode in the JFET structure, and the conductive channel of the silicon carbide MOSFET structure is almost free from current, so that the effects of reducing the performance degradation of the body diode of the MOSFET structure, improving the avalanche resistance of the device and improving the reliability of the device are realized.
According to the invention, the depletion type JFET structure conductive channel and the silicon carbide MOSFET structure conductive channel are formed by designing the position relation, the doping medium and the doping concentration of the three P-type base regions, the three N+ ion implantation regions and the four P+ ion implantation regions. It can be understood that the invention forms the silicon carbide MOSFET structure and the depletion type JFET structure in the same device, so that the semiconductor structure almost entirely discharges current from the conductive channel of the depletion type JFET structure in an avalanche state, the current does not pass through the body diode in the JFET structure, and the conductive channel of the silicon carbide MOSFET structure almost does not pass through the current, thereby reducing the performance degradation of the body diode in the silicon carbide MOSFET structure in an avalanche state.
The invention also provides a preparation method of the semiconductor structure, which comprises the following steps:
s100, providing an N+ type substrate, and growing an N-type epitaxial layer 2 on the N+ type substrate to obtain a structure shown in FIG. 6;
s200, P-type ion implantation is carried out on the surface, far away from the N+ type substrate, of the N-type epitaxial layer 2, and a first initial P-type base region, a second initial P-type base region and a third initial P-type base region which are distributed at intervals are formed in sequence, so that a structure shown in FIG. 7 is obtained;
s300, performing N-type ion implantation on partial top surfaces of the first initial P-type base region and the second initial P-type base region to form a first initial N+ ion implantation region connected with the first initial P-type base region and the second initial P-type base region; n-type ion implantation is carried out on partial top surfaces of the second initial P-type base region and the third initial P-type base region, so that a second initial N+ ion implantation region and a third initial N+ ion implantation region are formed, and a structure shown in figure 8 is obtained;
s400, P-type ion implantation is carried out on partial top surfaces of the first initial P-type base region, the second initial P-type base region and the third initial P-type base region, and a first P+ ion implantation region 9, a third P+ ion implantation region 11 and a fourth P+ ion implantation region 12 are respectively formed; and P-type ion implantation is carried out on part of the top surface of the first initial N+ ion implantation region to form a second P+ ion implantation region 10, so as to obtain a structure shown in FIG. 9;
S500, carrying out high-temperature annealing on the semiconductor structure after P-type and N-type ion implantation;
s600, forming a first gate region on the first initial N+ ion implantation region and a second gate region crossing over the second initial P-type base region and the third initial P-type base region;
s700, depositing and forming a source electrode 21 covering the first gate region and the second gate region on the N-type epitaxial layer 2 to obtain a structure shown in fig. 14;
and S800, depositing and forming a drain electrode 23 on the side of the N+ type substrate layer 1 away from the N-type epitaxial layer 2 to obtain the structure shown in fig. 1.
After step S100, the method further comprises: and manufacturing a first ion implantation blocking layer on the surface of the N-type epitaxial layer 2, carrying out P-type ion implantation under the high temperature condition by the aid of the first ion implantation blocking layer, sequentially forming a first initial P-type base region, a second initial P-type base region and a third initial P-type base region which are distributed at intervals, and removing the first ion implantation layer after P+ type ion implantation is completed to obtain a structure diagram shown in figure 6. Optionally, the P-type ion is Al ion or other metal ion, and the ion implantation dosage is 5e11-1e14cm -3 The implantation energy is 300keV-1000keV, and can be specifically selected according to actual requirements.
The step S300 specifically includes: after the first P-type base region 3, the second P-type base region 4 and the third P-type base region 5 are manufactured, a second ion implantation blocking layer is continuously manufactured on the surface of the N-type epitaxial layer 2, N ion implantation is performed under the high temperature condition by the aid of the second ion implantation blocking layer, and a first initial N+ ion implantation region which is connected with the first initial P-type base region and the second initial P-type base region is formed; simultaneously forming a second initial N+ ion implantation region positioned in the second initial P-type base region and a third initial ion implantation region positioned in the third initial P-type base region; and after the N+ type ion implantation is completed, removing the second ion implantation blocking layer to obtain a structural diagram shown in fig. 8. Optionally, the ion implantation dose is 1e13-5e14cm -3 The energy range is 100-300keV, and can be specifically selected according to actual requirements.
The steps S400 and S500 specifically include: after the first N+ ion implantation region 6, the second N+ ion implantation region 7 and the third N+ ion implantation region 8 are manufactured, the method comprises the following steps ofThe N-type epitaxial layer 2 continues to manufacture a third ion blocking layer, and P-type ion implantation is carried out under the high temperature condition by the assistance of the third ion implantation blocking layer to form a first P+ ion implantation region 9, a second P+ ion implantation region 10, a third P+ ion implantation region 11 and a fourth P+ ion implantation region 12 respectively; and after the P+ type ion implantation is completed, removing the third ion implantation blocking layer, and carrying out annealing activation on the current semiconductor structure under the high-temperature condition, so that the structure diagram shown in fig. 9 is obtained after the activation. Optionally, the P-type ion is Al ion or other metal ion, and the ion implantation dosage is 1e14-5e15cm -3 The energy range is 50-200keV. Optionally, the annealing temperature is 1700-2000 ℃, and can be specifically selected according to actual requirements.
In the semiconductor structure formed in step S500, the remaining area after the first n+ ion implantation region 6 and the first p+ ion implantation region 9 are implanted in the first initial P-type base region is the first P-type base region 3, the remaining area after the p+ ion implantation and the n+ ion implantation are completed in the second initial P-type base region is the second P-type base region 4, and the remaining area after the p+ ion implantation and the n+ ion implantation are completed in the third initial P-type base region is the third P-type base region 5. The remaining area after p+ ions are implanted in the first n+ ion implantation area 6 is the first n+ ion implantation area 6, any ions are implanted in the second initial n+ ion implantation area and the third initial ion implantation area, that is, the second initial n+ ion implantation area is the second n+ ion implantation area 7, and the third initial n+ ion implantation area is the third n+ ion implantation area 8.
In this embodiment, the first ion implantation blocking layer, the second ion implantation blocking layer and the third ion implantation blocking layer are hard mask layers, and the structures of the three mask layers are different. The structure of the first ion implantation barrier layer is related to the distribution position of the P-type base region; the structure of the second ion implantation barrier layer is related to the distribution position of the N+ ion implantation region; the structure of the third ion implantation barrier layer is related to the distribution position of the P+ ion implantation region.
Further, forming a first gate region on the first initial n+ ion implantation region in step S600 includes:
s610, growing an initial gate oxide layer 18 on the N-type epitaxial layer 2; optionally, the oxide layer is about 50nm thick;
and S620, etching the initial gate oxide layer 18 to form a gate oxide layer 18 which spans the second P-type base region 4 and the third P-type base region 5, wherein the gate oxide layer 18 covers partial top surfaces of the second N+ ion implantation region 7 and the third N+ ion implantation region 8.
In this step, a photolithography barrier layer may be formed over the initial gate oxide layer 18, and then the initial gate oxide layer 18 is etched by a dry etching method to form the gate oxide layer 18, as shown in fig. 10.
S630, depositing a metal material on the surface of the N-type epitaxial layer 2 to form a gate layer, and etching the gate layer to form a first gate 16 positioned on the top surface of the second P+ ion implantation region 10 and a second gate 17 positioned on the top surface of the gate oxide layer 18;
in this step, the gate layer may be etched by photolithography, thereby forming the first gate electrode 16 and the second gate electrode 17 as shown in fig. 11. Optionally, the metal material is a polysilicon material.
And S640, depositing dielectric layer films on the surfaces of the N-type epitaxial layer 2 and the first grid electrode 16 and the second grid electrode 17, and etching the dielectric layer films to form a first insulating dielectric layer 19 wrapping the first grid electrode 16 and a second insulating dielectric layer 20 wrapping the second grid electrode 17 and the grid electrode oxide layer 18.
In this step, a chemical vapor deposition method may be adopted to deposit and form the dielectric layer film on the N-type epitaxial layer 2 and the surfaces of the first gate electrode 16 and the second gate electrode 17; then, the redundant dielectric layer films are etched away in the areas outside the first grid electrode 16 and the second grid electrode 17 through photoetching, and a first insulating dielectric layer 19 and a second insulating dielectric layer 20 which are mutually independent are respectively formed, as shown in fig. 12.
Further, after the step S640, before the step S700, the preparation method further includes:
at S650, an ohmic contact metal material is deposited on the remaining surface of the N-type epitaxial layer 2 and annealed to form a first source ohmic contact region 13, a second source ohmic contact region 14 and a third source ohmic contact region 15, which are spaced apart, as shown in fig. 13.
In this step, optionally, the annealing temperature is in the range of 900-1100 ℃ and the annealing time is in the range of 60-250 s. Optionally, the ohmic contact metal includes, but is not limited to, ti, ni, W, or the like.
The step S700 specifically includes: electrode metal is deposited on the N-epi layer 2 to form a source 21 covering the first gate region, the second gate region and the three source ohmic contact regions, as shown in particular in fig. 14. Optionally, the electrode metal includes, but is not limited to Al, alSi, alCu or AlSiCu, etc. The thickness of the electrode metal can be specifically selected according to actual requirements. In this embodiment, the electrode metal thickness is 5 microns.
The step S800 specifically includes: and thinning the back of the N+ type substrate, depositing ohmic contact metal on the back, forming a drain ohmic contact layer 22 through high-temperature annealing, and depositing a drain metal layer on the drain ohmic contact layer 22 to form a drain 23, as shown in fig. 1. Optionally, the ohmic contact metal includes, but is not limited to, ti or Ni. The material of the drain electrode 23 metal layer includes but is not limited to Ti, ni or Ag, and may be specifically selected according to practical requirements.
The beneficial effects of the invention are as follows: firstly, the semiconductor structure provided by the invention is a SiC MOSFET with a depletion type JFET structure, and by changing an avalanche current discharging path, the performance degradation of a diode of the MOSFET structure body is reduced, the avalanche resistance of the device is improved, and the reliability of the device is improved; secondly, the preparation method of the semiconductor structure provided by the invention is compatible with the main stream SiC MOSFET manufacturing process, no new process is needed, the process flow is simple, the cost is low, and the method is suitable for large-scale production.
Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the apparatus and device described above may refer to corresponding procedures in the foregoing method embodiments, which are not described herein again.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other manners. For example, the device embodiments described above are merely illustrative.
It will be appreciated by persons skilled in the art that the scope of the invention referred to in the present invention is not limited to the specific combinations of the technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the inventive concept. Such as the above-mentioned features and the technical features disclosed in the present invention (but not limited to) having similar functions are replaced with each other.
It should be understood that, the sequence numbers of the steps in the summary and the embodiments of the present invention do not necessarily mean the order of execution, and the execution order of the processes should be determined by the functions and the internal logic, and should not be construed as limiting the implementation process of the embodiments of the present invention.
Claims (13)
1. A semiconductor structure, the structure comprising:
a drain electrode;
an N+ type substrate layer in ohmic contact with the drain electrode;
the N-type epitaxial layer is positioned on the N+ type substrate layer, and a first P type base region, a second P type base region and a third P type base region which are distributed at intervals are sequentially formed on one side of the N+ type substrate layer;
the first P+ ion implantation region, the third P+ ion implantation region and the fourth P+ ion implantation region respectively cover partial top surfaces of the first P-type base region, the second P-type base region and the third P-type base region;
the first N+ ion implantation region is connected with the first P-type base region and the second P-type base region and covers partial top surfaces of the first P-type base region and the second P-type base region; the first N+ ion implantation region is used as a part of a conductive channel of the semiconductor structure;
a second P+ ion implantation region covering a part of the top surface of the first N+ ion implantation region;
the second N+ ion implantation region covers the top surface of the second P-type base region part, and the third P+ ion implantation region is arranged between the second N+ ion implantation region and the first N+ ion implantation region;
the third N+ ion implantation region covers the third P-type base region and is positioned at one side of the fourth P+ ion implantation region close to the second P-type base region;
The first grid region is positioned above the first N+ ion implantation region and covers the top surface of the second P+ ion implantation region;
a second gate region crossing over the second P-type base region and the third P-type base region;
and the source electrode is positioned above the N-type epitaxial layer and covers the first gate electrode region and the second gate electrode region.
2. The semiconductor structure of claim 1, wherein a bottom surface of the first n+ ion implantation region is lower than bottom surfaces of the first, second, and third p+ ion implantation regions, respectively;
the bottom surface of the second N+ ion implantation region is lower than the bottom surface of the third P+ ion implantation region;
and the bottom surface of the third N+ ion implantation region is lower than the bottom surface of the fourth P+ ion implantation region.
3. The semiconductor structure of claim 2, wherein the first p+ ion implantation region, the second p+ ion implantation region, the third p+ ion implantation region, and the fourth p+ ion implantation region are all flush with the top surface of the N-type epitaxial layer;
the first N+ ion implantation region, the second N+ ion implantation region, the third N+ ion implantation region and the fourth P+ ion implantation region are all flush with the top surface of the N-type epitaxial layer.
4. The semiconductor structure of claim 1, wherein the first n+ ion implantation region exhibits a U-shaped structure, and the second n+ ion implantation region and the third n+ ion implantation region are both square structures.
5. The semiconductor structure of claim 1, wherein the first, second and third P-type base regions are P-type ions with the same doping concentration, and the P-type ion doping concentration ranges from 1e16 cm to 5e18cm -3 。
6. The semiconductor structure of claim 1, wherein the first, second, third and fourth p+ ion implantation regions are P-type ions and have the same doping concentration, and the P-type ion doping concentration ranges from 6e18 cm to 5e19cm -3 。
7. The semiconductor structure of claim 1, wherein the first, second and third n+ ion implantation regions are doped with N-type ions having the same doping concentration in a range of 1e17-1e19cm -3 。
8. The semiconductor structure of claim 1, wherein the first gate region comprises a first gate and a first insulating dielectric layer;
the first grid electrode covers part of the top surface of the second P+ ion implantation region;
and the first insulating medium layer wraps the periphery of the first grid electrode so as to enable the first grid electrode to be in insulating contact with the source electrode.
9. The semiconductor structure of claim 1, wherein the second gate region comprises a gate oxide layer, a second gate, and a second insulating dielectric layer,
the grid oxide layer spans the second P-type base region and the third P-type base region and covers partial top surfaces of the second N+ ion implantation region and the third N+ ion implantation region;
the second grid electrode is positioned on the grid electrode oxide layer;
and the second insulating medium layer wraps the periphery of the second grid electrode and the grid electrode oxidation layer so as to enable the second grid electrode to be in insulating contact with the source electrode.
10. The semiconductor structure of claim 1, wherein the semiconductor structure further comprises: the first source ohmic contact region, the second source ohmic contact region and the third source ohmic contact region are sequentially distributed at intervals;
the first source ohmic contact region covers the top surface of the first P+ ion implantation region and part of the top surface of the first N+ ion implantation region;
the second source ohmic contact region is arranged between the first gate region and the second gate region and covers the top surface of the third P+ ion implantation region and part of the top surfaces of the first N+ ion implantation region and the second N+ ion implantation region;
And the third source ohmic contact region covers part of the top surface of the third N+ ion implantation region and the top surface of the fourth P+ ion implantation region.
11. A method of fabricating a semiconductor structure according to any one of claims 1 to 10, comprising:
s100, providing an N+ type substrate, and growing an N-type epitaxial layer on the N+ type substrate;
s200, P-type ion implantation is carried out on the surface, far away from the N+ type substrate, of the N-type epitaxial layer, and a first initial P-type base region, a second initial P-type base region and a third initial P-type base region which are distributed at intervals are formed in sequence;
s300, performing N-type ion implantation on partial top surfaces of the first initial P-type base region and the second initial P-type base region to form a first initial N+ ion implantation region connected with the first initial P-type base region and the second initial P-type base region; n-type ion implantation is carried out on partial top surfaces of the second initial P-type base region and the third initial P-type base region, so that a second initial N+ ion implantation region and a third initial N+ ion implantation region are formed;
s400, P-type ion implantation is carried out on partial top surfaces of the first initial P-type base region, the second initial P-type base region and the third initial P-type base region, and a first P+ ion implantation region, a third P+ ion implantation region and a fourth P+ ion implantation region are respectively formed; p-type ion implantation is carried out on part of the top surface of the first initial N+ ion implantation region, so that a second P+ ion implantation region is formed;
S500, carrying out high-temperature annealing on the semiconductor structure after P-type and N-type ion implantation;
s600, forming a first gate region on the first initial N+ ion implantation region and a second gate region crossing over the second initial P-type base region and the third initial P-type base region;
s700, depositing and forming a source electrode covering the first gate region and the second gate region on the N-type epitaxial layer;
and S800, depositing a drain electrode on one side of the N+ type substrate layer far away from the N-type epitaxial layer.
12. The method of claim 11, wherein S600 comprises:
s610, growing an initial gate oxide layer on the N-type epitaxial layer;
s620, etching the initial gate oxide layer to form a gate oxide layer which spans the second P-type base region and the third P-type base region, wherein the gate oxide layer covers partial top surfaces of the second N+ ion implantation region and the third N+ ion implantation region;
s630, depositing a metal material on the surface of the N-type epitaxial layer to form a gate layer, and etching the gate layer to form a first gate positioned on the top surface of the second P+ ion implantation region and a second gate positioned on the top surface of the gate oxide layer;
And S640, depositing dielectric layer films on the surfaces of the N-type epitaxial layer and the first grid electrode and the second grid electrode, and etching the dielectric layer films to form a first insulating dielectric layer wrapping the first grid electrode and a second insulating dielectric layer wrapping the second grid electrode and the grid electrode oxide layer.
13. The method of claim 12, wherein after S640, before S700, the method further comprises:
and S650, depositing ohmic contact metal materials on the residual surface of the N-type epitaxial layer and annealing to form a first source ohmic contact region, a second source ohmic contact region and a third source ohmic contact region which are spaced apart.
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| CN107785367A (en) * | 2016-08-31 | 2018-03-09 | 无锡华润上华科技有限公司 | It is integrated with the device and its manufacture method of depletion type junction field effect transistor |
| JP2020061518A (en) * | 2018-10-12 | 2020-04-16 | トヨタ自動車株式会社 | Semiconductor device and manufacturing method thereof |
| JP2020141130A (en) * | 2019-02-27 | 2020-09-03 | 株式会社デンソー | Silicon carbide semiconductor device and manufacturing method of the same |
| US20210143255A1 (en) * | 2019-11-11 | 2021-05-13 | Hitachi, Ltd. | Semiconductor device |
| CN114927562A (en) * | 2022-07-20 | 2022-08-19 | 深圳平创半导体有限公司 | Silicon carbide JFET device structure and preparation method thereof |
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