CN116314242A - Display panel and display device - Google Patents
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- CN116314242A CN116314242A CN202310388722.8A CN202310388722A CN116314242A CN 116314242 A CN116314242 A CN 116314242A CN 202310388722 A CN202310388722 A CN 202310388722A CN 116314242 A CN116314242 A CN 116314242A
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- 239000010410 layer Substances 0.000 claims description 139
- 239000002184 metal Substances 0.000 claims description 72
- 239000011241 protective layer Substances 0.000 claims description 22
- 239000000758 substrate Substances 0.000 claims description 22
- 230000000694 effects Effects 0.000 description 14
- 238000004519 manufacturing process Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008054 signal transmission Effects 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Theoretical Computer Science (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The application relates to a display panel and a display device. The display panel comprises a light emitting chip and a driving circuit electrically connected with the light emitting chip, wherein the light emitting chip is overlapped with the driving circuit and is arranged at intervals, the light emitting chip comprises a first pad and a second pad which are oppositely arranged, the driving circuit comprises a first voltage signal wire and a second voltage signal wire, the first pad is electrically connected with the first voltage signal wire, the second pad is electrically connected with the second voltage signal wire, the driving circuit is used for generating a voltage signal and transmitting the voltage signal to the first pad through the first voltage signal wire, and the light emitting chip receives the voltage signal and emits light according to the voltage signal; the light emitting chip also transmits a voltage signal to the second voltage signal line through the second pad. In the display panel of the application, the driving circuit and the light emitting chips are overlapped and are arranged on the display panel at intervals, so that the layout space of the display panel is effectively saved, and the space utilization rate of the display panel is improved.
Description
Technical Field
The present disclosure relates to the field of display technologies, and in particular, to a display panel and a display device having the display panel.
Background
In a conventional display panel, a driving circuit and a light emitting chip are generally separately laid out (Layout), wherein the driving circuit includes components such as a switching device and a signal line.
However, these components occupy more space in the Active Area (AA) of the display panel, which results in a smaller number of Pixels Per Inch diagonal, i.e., a smaller pixel density unit (PPI) of the display panel, which makes it difficult to improve the resolution of the display panel, thereby affecting the display effect of the display panel.
Therefore, how to optimize the layout of the components of the display panel to improve the resolution of the display panel is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the shortcomings of the prior art, an object of the present application is to provide a display panel and a display device, in which a light emitting chip and a driving circuit are arranged at a certain distance and in an overlapping manner, and the light emitting chip and the driving circuit are not required to be laid out separately, so that the layout space of the display panel is effectively saved.
In a first aspect, the present application provides a display panel, where the display panel includes a light emitting chip and a driving circuit electrically connected to the light emitting chip, the light emitting chip overlaps the driving circuit and is disposed at intervals, the light emitting chip includes a first pad and a second pad that are disposed opposite to each other, the driving circuit includes a first voltage signal line and a second voltage signal line, the first pad is electrically connected to the first voltage signal line, the second pad is electrically connected to the second voltage signal line, the driving circuit is configured to generate a voltage signal, and transmit the voltage signal to the first pad through the first voltage signal line, and the light emitting chip receives the voltage signal and emits light according to the voltage signal; the light emitting chip also transmits the voltage signal to the second voltage signal line through the second pad.
In some embodiments, the driving circuit further includes a data line, a scan line, a first control transistor, and a second control transistor, wherein a control terminal of the first control transistor receives a control signal from the scan line, a first terminal of the first control transistor receives a data signal from the data line, a second terminal of the first control transistor is electrically connected to a control terminal of the second control transistor, and the first control transistor transmits the data signal to the second control transistor according to the control signal;
the first end of the second control transistor is electrically connected to the second pad, receives the voltage signal from the second pad, the second end of the second control transistor is electrically connected to a second voltage signal line, and the second control transistor receives the data signal and is in a conducting state to receive the voltage signal from the second pad and transmit the voltage signal to the second voltage signal line;
the first voltage signal line, the second voltage signal line, the data line and the scanning line are arranged on one side of the light-emitting chip, and orthographic projection parts of the first voltage signal line, the second voltage signal line, the data line and the scanning line on the light-emitting chip are positioned on the light-emitting chip;
The first control transistor and the second control transistor are arranged on the same side of the light-emitting chip with the data line, and the orthographic projection of the first control transistor on the light-emitting chip is positioned on the light-emitting chip.
In some embodiments, the drive circuit further includes a substrate base plate, a first metal layer, an insulating layer, a second metal layer, a protective layer, and a conductive layer,
the first metal layer is arranged in a partial area on the substrate and is used for arranging the scanning lines;
the insulating layer is arranged on one side of the first metal layer, which is opposite to the substrate, and the surface of the substrate, which is not covered by the first metal layer, and is used for separating electric signals between the first metal layer and the second metal layer;
the second metal layer is arranged on a part of the surface of the insulating layer, which is opposite to the first metal layer, and is used for laying the first voltage signal line and the second voltage signal line, and the first control transistor and the second control transistor are formed on the first metal layer and the second metal layer;
the protective layer is arranged on the side, facing away from the insulating layer, of the second metal layer, and the surface, not covered by the insulating layer, of the second metal layer;
The conducting layer is arranged on one side of the protective layer, which is opposite to the substrate, and is used for electrically connecting the light-emitting chip with the driving circuit, and electrically connecting the first control transistor and the second control transistor.
In some embodiments, the first metal layer includes a first control electrode and a second control electrode, where the first control electrode is disposed at an interval from the second control electrode, the first control electrode is used to lay the scan line and serve as a control end of the first control transistor, the second control electrode is used as a control end of the second control transistor, and orthographic projections of the first control electrode and the second control electrode on the light emitting chip are located on the light emitting chip;
the second metal layer is used for setting the first voltage signal line and the second voltage signal line, the first voltage signal line is arranged on one side of the second metal layer, and the second voltage signal line and the first voltage signal line are arranged at intervals.
In some embodiments, the second metal layer includes a first electrode, a second electrode, a third electrode, and a fourth electrode, the first electrode and the second electrode are disposed between the first voltage signal line and the second voltage signal line with a first gap therebetween, and the first gap corresponds to a position of the first control electrode, the first electrode, the second electrode, and the first control electrode being a first end, a second end, and a control end of the first control transistor;
The third electrode and the fourth electrode are arranged on one side, far away from the first voltage signal line, of the second voltage signal line, a second gap is formed between the third electrode and the fourth electrode, the second gap corresponds to the position of the second control electrode, the third electrode, the fourth electrode and the second control electrode serve as a second end, a first end and a control end of the second control transistor, and the third electrode is electrically connected with the second voltage signal line.
In some embodiments, the third electrode is spaced from the second voltage signal line a distance less than the fourth electrode is spaced from the second voltage signal line.
In some embodiments, the distance between the third electrode and the second voltage signal line is greater than the distance between the fourth electrode and the second voltage signal line, and the orthographic projection of the third electrode on the light emitting chip is not located on the light emitting chip.
In some embodiments, the conductive layer includes a first conductive signal line, a second conductive signal line, and a third conductive signal line, where the first conductive signal line is disposed on a side of the protective layer opposite to the first voltage signal line and is embedded in the protective layer, one side of the first conductive signal line embedded in the protective layer is electrically connected to the first voltage signal line, and the other side of the first conductive signal line is electrically connected to the first pad;
The second conductive signal wire is arranged on one side of the protection layer, which is opposite to the fourth electrode, and is embedded into the protection layer, one side of the second conductive signal wire, which is embedded into the protection layer, is electrically connected with the fourth electrode, and the other side of the second conductive signal wire is electrically connected with the second liner;
the third conductive signal wire is used for electrically connecting the second electrode and the second control electrode, is arranged on one side of the protection layer opposite to the second metal layer and is positioned between the first conductive signal wire and the second conductive signal wire, part of the third conductive signal wire is embedded into the protection layer to the second electrode and is electrically connected with the second electrode, and part of the third conductive signal wire penetrates through the protection layer and penetrates through the insulating layer and is electrically connected with the second control electrode.
In some embodiments, the first conductive signal line is positioned corresponding to the first pad, and an orthographic projection of the first pad on the second metal layer is positioned on the first conductive signal line;
the position of the second conductive signal line corresponds to the second pad, and the orthographic projection of the second pad on the second metal layer is positioned on the fourth electrode;
One side of the third conductive signal wire is embedded into the protective layer and is electrically connected with the second electrode, and the other side of the third conductive signal wire penetrates through the insulating layer and is electrically connected with one side, close to the first control electrode, of the second control electrode.
In a second aspect, the present application provides a display device, where the display device includes a power module and the display panel, and the power module is electrically connected to the display panel, and is configured to provide electric energy for performing picture display on the display panel.
In summary, in the display panel and the display device of the present application, the light emitting chip and the driving circuit are disposed at a certain distance and overlap, that is, the first signal line, the second signal line, the first control transistor, the second control transistor and other components are disposed under the light emitting chip, so that the light emitting chip and the driving circuit do not need to be separately laid out, and the layout space of the display panel is effectively saved. According to the technical scheme, more pixel units can be distributed on the display panel, so that the pixel density unit and resolution of the display panel are effectively improved. Moreover, the saved space can be used for laying other electronic components, the pixel density unit, resolution and space utilization rate of the display panel are improved, the display effect of the display panel is further improved, and the display panel is favorably pushed to the application of the virtual reality technology. Meanwhile, as the light emitting chip and the driving circuit are arranged at a certain distance in an overlapping way, the wiring distance for realizing electric connection between the light emitting chip and the driving circuit is effectively shortened, and the wiring cost is effectively reduced.
In addition, the first control transistor is arranged below the light emitting chip, heat is generated after the light emitting chip is electrified, so that the temperature of the first control transistor is raised, the threshold voltage of the transistor is reduced, the charging efficiency of the first control transistor is improved, the problem of insufficient charging of the first control transistor is avoided, the first control transistor is helped to be in a correctly-conducted state, and the display effect of the display panel is ensured while the layout space of the display panel is saved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a part of a structure of a display panel according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of the display panel shown in FIG. 1;
FIG. 3 is a schematic cross-sectional view of the display panel shown in FIG. 2 along the line B-B;
FIG. 4 is a schematic view of another structure of the display panel shown in FIG. 1;
FIG. 5 is a schematic top view of the display panel of FIG. 1;
FIG. 6 is a flow chart of a method for manufacturing the display panel shown in FIG. 1;
fig. 7 is a flowchart illustrating step S10 in the method for manufacturing the display panel shown in fig. 6.
Reference numerals illustrate:
100-a display panel; 10-a light emitting chip; 20-a driving circuit; 11-a first liner; 12-a second liner; 26-a first control transistor; 27-a second control transistor; 13-chip body; 21-a substrate base; 23-an insulating layer; 28-a protective layer; 26 c-a first control electrode; 27 c-a second control electrode; 26 a-a first electrode; 26 b-a second electrode; 27 a-a third electrode; 27 b-a fourth electrode; 29 a-a first conductive signal line; 29 b-a second conductive signal line; 29 c-a third conductive signal line; S10-S30, a manufacturing method; S11-S15, namely a step of manufacturing a method S10; m-overlap direction; gate-control signal; a Data-Data signal; vdd-a first voltage signal line; vss-a second voltage signal line.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
The following description of the embodiments refers to the accompanying drawings, which illustrate specific embodiments that can be used to practice the present application. The numbering of the components itself, e.g. "first", "second", etc., is used herein merely to distinguish between the described objects and does not have any sequential or technical meaning. The terms "coupled" and "connected," as used herein, are intended to encompass both direct and indirect coupling (coupling), unless otherwise indicated. Directional terms referred to in this application, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outer", "side", etc., are merely directions referring to the attached drawings, and thus, directional terms are used for better, more clear description and understanding of the present application, rather than indicating or implying that the apparatus or element being referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; may be a mechanical connection; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context. It should be noted that the terms "first," "second," and the like in the description and claims of the present application and in the drawings are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprises," "comprising," "includes," "including," "may be" or "including" as used in this application mean the presence of the corresponding function, operation, element, etc. disclosed, but not limited to other one or more additional functions, operations, elements, etc. Furthermore, the terms "comprises" or "comprising" mean that there is a corresponding feature, number, step, operation, element, component, or combination thereof disclosed in the specification, and that there is no intention to exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof. It will also be understood that the meaning of "at least one" as described herein is one and more, such as one, two or three, etc., and the meaning of "a plurality" is at least two, such as two or three, etc., unless specifically defined otherwise. The terms "step 1", "step 2", and the like in the description and claims of the present application and in the drawings, are used for distinguishing between different objects and not for describing a particular sequential order.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
Referring to fig. 1, fig. 1 is a schematic diagram illustrating a partial structure of a display panel according to an embodiment of the disclosure. As shown in fig. 1, in the embodiment of the present application, the display panel 100 includes a light emitting chip 10 and a driving circuit 20 electrically connected to the light emitting chip 10, where the light emitting chip 10 overlaps the driving circuit 20 and is disposed at intervals, that is, the light emitting chip 10 is disposed on the driving circuit 20 and is spaced from the driving circuit 20, the light emitting chip 10 includes a first pad 11 and a second pad 12 disposed opposite to each other, the driving circuit 20 includes a first voltage signal line Vdd and a second voltage signal line Vss, the first pad 11 is electrically connected to the first voltage signal line Vdd, the second pad 12 is electrically connected to the second voltage signal line Vss, and the driving circuit 20 is configured to generate a voltage signal and transmit the voltage signal to the first pad 11 through the first voltage signal line Vdd, and the light emitting chip 10 receives the voltage signal and emits light according to the voltage signal. The light emitting chip also transmits the voltage signal to the second voltage signal line Vss through the second pad 12.
In the embodiment of the present application, the display panel 100 may be a Micro light emitting diode (Micro Light Emitting Diode, micro LED) display panel, which is not particularly limited in this application.
In the embodiment of the present application, the light emitting chip 10 may emit red light, blue light or yellow light, which is not particularly limited in the present application. The first pad 11 and the second pad 12 may be metal pads, which are not particularly limited in this application.
As shown in fig. 1, in the embodiment of the present application, the driving circuit 20 further includes a data line, a scan line, a first control transistor 26, and a second control transistor 27. The driving circuit 20 transmits the voltage signal to the first pad 11 through the first voltage signal line Vdd.
The first control transistor 26 is electrically connected to the second control transistor 27, and the second control transistor 27 is electrically connected to the second pad 12; the first control transistor 26 receives a control signal Gate from the scan line and a Data signal Data from the Data line, and the first control transistor 26 transmits the Data signal Data to the second control transistor 27 according to the control signal Gate; the second control transistor 27 receives the Data signal Data and is in an on state to receive the voltage signal from the second pad 12 and transmit the voltage signal to the second voltage signal line Vss.
In the specific embodiment of the present application, the first control transistor 26 and the second control transistor 27 each include a control terminal, a first terminal and a second terminal. The control terminal of the first control transistor 26 is configured to receive a control signal Gate from the scan line, the first terminal of the first control transistor 26 is configured to receive a Data signal Data from the Data line, the second terminal of the first control transistor 26 is electrically connected to the control terminal of the second control transistor 27, the first terminal of the second control transistor 27 is electrically connected to the second pad 12, the first terminal of the second control transistor 27 is configured to receive the voltage signal from the second pad 12, and the second terminal of the second control transistor 27 is electrically connected to the second voltage signal line Vss. When the second control transistor 27 is in the on state, the voltage signal received by the first end of the second control transistor 27 is transmitted to the second voltage signal line Vss through the second control transistor 27, that is, the second control transistor 27 may selectively transmit the voltage signal to the second voltage signal line Vss.
In the specific embodiment of the present application, the control terminal may be the gates of the first control transistor 26 and the second control transistor 27, the first terminal may be the sources of the first control transistor 26 and the second control transistor 27, and the second terminal may be the drains of the first control transistor 26 and the second control transistor 27, which is not specifically limited in the present application.
In the embodiment of the present application, the first voltage signal line Vdd, the second voltage signal line Vss, the data line and the scan line portion are disposed on one side of the light emitting chip 10, and the arrangement direction thereof is perpendicular to the overlapping direction of the light emitting chip 10 and the driving circuit 20; the first control transistor 26 and the data line are disposed on the same side of the light emitting chip 10, and the orthographic projection of the first control transistor 26 on the light emitting chip 10 is located on the light emitting chip 10.
In the embodiment of the present application, the driving circuit 20 and the light emitting chip 10 are spaced a certain distance and are overlapped, so that the arrangement of the driving circuit 20 and the light emitting chip 10 on the display panel 100 effectively saves the layout space of the display panel 100. Moreover, the saved space can be used for arranging more pixel units, so as to effectively improve the pixel density unit (PPI) and resolution of the display panel 100, thereby improving the display effect of the display panel. Meanwhile, the saved space can be used for laying other electronic components, so that the space utilization rate of the display panel 100 is improved.
In addition, the first control transistor 26 is disposed below the light emitting chip 10, and heat is generated after the light emitting chip 10 is powered on, so that the temperature of the first control transistor 26 is raised, and the threshold voltage of the transistor is reduced, thereby improving the charging efficiency of the first control transistor 26, avoiding the problem of insufficient charging, helping the first control transistor 26 to be correctly in a conductive state, and improving the display effect of the display panel 100.
Referring to fig. 2 and fig. 3 together, fig. 2 is a schematic structural diagram of the display panel 100 shown in fig. 1. Fig. 3 is a schematic cross-sectional view of the display panel shown in fig. 2 along line B-B. As shown in fig. 2 and 3, in the embodiment of the present application, the light emitting chip 10 may be a circular sheet structure or a square sheet structure as a whole. The light emitting chip 10 further includes a chip body 13, and the first pad 11 and the second pad 12 are disposed at opposite ends of the chip body 13 and located at a side of the chip body 13 close to the driving circuit 20. In other words, the first pad 11 and the second pad 12 are also located at opposite ends of the light emitting chip 10.
It should be noted that, in fig. 2, the direction indicated by the arrow M and the opposite direction thereof are the overlapping direction of the light emitting chip 10 and the driving circuit 20, specifically, the light emitting chip 10 is disposed above the driving circuit 20 and is spaced from the driving circuit 20 by a preset distance, that is, the light emitting chip 10 and the driving circuit 20 form overlapping and are disposed at intervals.
In the embodiment of the present application, the driving circuit 20 includes a substrate 21, a first metal layer (not shown), an insulating layer 23, a second metal layer (not shown), a protective layer 28, and a conductive layer (not shown). Wherein the substrate 21 is used as a bottom layer of the driving circuit 20 for supporting other layer structures thereon.
The first metal layer is disposed in a partial region on the substrate 21, and is used for laying out scan lines and a part of structures of the first control transistor 26 and the second control transistor 27. The insulating layer 23 is disposed on a surface of the first metal layer facing away from the substrate 21, and the surface of the first metal layer not covering the substrate 21. The insulating layer 23 is used to isolate electrical signals between the first metal layer and the second metal layer. The second metal layer is disposed on a portion of the insulating layer 23 facing away from the first metal layer. The second metal layer is used for laying out the first voltage signal line, the second voltage signal line and another part of structures of the first control transistor 26 and the second control transistor 27. That is, the first control transistor 26 and the second control transistor 27 are disposed on the first metal layer and the second metal layer at the same time.
The protective layer 28 is disposed on a surface of the second metal layer opposite to the insulating layer 23 and a surface of the second metal layer not covered by the insulating layer 23, for protecting other layer structures located thereunder. The conductive layer is disposed on a side of the protective layer 28 opposite to the substrate 21, and is used for electrically connecting the light emitting chip 10 and the driving circuit 20, and electrically connecting the first control transistor 26 and the second control transistor 27.
As shown in fig. 3, in the embodiment of the present application, the first metal layer includes a first control electrode 26c and a second control electrode 27c, where the first control electrode 26c is spaced from the second control electrode 27c, and the first control electrode 26c is used for laying out the scan line and is used as a control terminal of the first control transistor 26. The second control electrode 27c is used as a control terminal of the second control transistor 27. The orthographic projection of the first control electrode 26c and the second control electrode 27c on the light emitting chip 10 is located on the light emitting chip 10. Specifically, the first control electrode 26c and the second control electrode 27c leave a gap in a direction parallel to the upper surface of the substrate 21.
In this embodiment, the second metal layer is used to set the first voltage signal line Vdd and the second voltage signal line Vssb. The first voltage signal line Vdd is disposed on one side of the second metal layer, and the second voltage signal line Vss is spaced from the first voltage signal line Vdd. The first voltage signal line Vdd and the second voltage signal line Vss are located on the light emitting chip 10 at the front projection portion of the light emitting chip 10.
In this embodiment, the second metal layer includes a first electrode 26a and a second electrode 26b, where the first electrode 26a and the second electrode 26b are disposed between the first voltage signal line Vdd and the second voltage signal line Vss, and a first gap is formed between the first electrode 26a and the second electrode 26b, and the first gap corresponds to the position of the first control electrode 26c, that is, the front projection portion of the first gap on the first metal layer is located on the first control electrode 26 c. The first electrode 26a, the second electrode 26b, and the first control electrode 26c may serve as a first terminal, a second terminal, and a control terminal of the first control transistor 26, respectively. Specifically, the first electrode 26a may serve as a source of the first control transistor 26, the second electrode 26b may serve as a drain of the first control transistor 26, and the first control electrode 26c may serve as a gate of the first control transistor 26.
In the embodiment of the present application, the first electrode 26a is closer to the first voltage signal line Vdd than the second electrode 26b, that is, the distance between the first electrode 26a and the first voltage signal line Vdd is smaller than the distance between the second electrode 26b and the first voltage signal line Vdd.
In other embodiments of the present application, the first electrode 26a is further away from the first voltage signal line Vdd than the second electrode 26b, that is, the distance between the first electrode 26a and the first voltage signal line Vdd is greater than the distance between the second electrode 26b and the first voltage signal line Vdd.
As shown in fig. 3, in the embodiment of the present application, the second metal layer further includes a third electrode 27a and a fourth electrode 27b, where the third electrode 27a and the fourth electrode 27b are disposed on a side of the second voltage signal line Vss away from the first voltage signal line Vdd, and a second gap is between the third electrode 27a and the fourth electrode 27b, and the second gap corresponds to a position of the second control electrode 27c, that is, a orthographic projection portion of the second gap on the first metal layer is located on the first control electrode 26 c. The third electrode 27a is electrically connected to the second voltage signal line Vss, and the third electrode 27a, the fourth electrode 27b and the second control electrode 27c may be respectively used as a second terminal, a first terminal and a control terminal of the second control transistor 27.
Specifically, the third electrode 27a may serve as a drain of the second control transistor 27, the fourth electrode 27b may serve as a source of the second control transistor 27, and the second control electrode 27c may serve as a gate of the second control transistor 27.
In other embodiments of the present application, the third electrode 27a is closer to the second voltage signal line Vss than the fourth electrode 27b, that is, the distance between the third electrode 27a and the second voltage signal line Vss is smaller than the distance between the fourth electrode 27b and the second voltage signal line Vss. Alternatively, the third electrode 27a is located at a side of the second voltage signal line Vss away from the first voltage signal line Vdd and is in contact with the second voltage signal line Vss, so as to electrically connect the third electrode 27a and the second voltage signal line Vss.
As shown in fig. 3, in the embodiment of the present application, the conductive layer includes a first conductive signal line 29a, a second conductive signal line 29b, and a third conductive signal line 29c, where the first conductive signal line 29a is disposed on a side of the protection layer 28 opposite to the first voltage signal line Vdd and is embedded in the protection layer 28, one side of the first conductive signal line 29a embedded in the protection layer 28 is electrically connected to the first voltage signal line Vdd, and the other side of the first conductive signal line 29a is electrically connected to the first pad 11. At this time, the first pad 11 and the first voltage signal line Vdd are electrically connected. Optionally, the position of the first conductive signal line 29a corresponds to the first pad 11, and the orthographic projection of the first pad 11 on the second metal layer is located on the first conductive signal line 29a, so that the wiring distance for electrically connecting the first conductive signal line 29a and the first pad 11 is shortest, and the wiring space is saved.
The second conductive signal line 29b is disposed on a side of the protection layer 28 opposite to the fourth electrode 27b and is embedded in the protection layer 28, one side of the second conductive signal line 29b embedded in the protection layer 28 is electrically connected to the fourth electrode 27b, and the other side of the second conductive signal line 29b is electrically connected to the second pad 12. At this time, the second pad 12 and the fourth electrode 27b are electrically connected. Optionally, the second conductive signal line 29b is located at a position corresponding to the second pad 12, and the orthographic projection of the second pad 12 on the second metal layer is located on the fourth electrode 27b, so that the wiring distance electrically connecting the fourth electrode 27b and the second pad 12 is shortest, and the wiring space is saved.
The third conductive signal line 29c is configured to electrically connect the second electrode 26b and the second control electrode 27c, that is, electrically connect the second end of the first control transistor 26 and the control end of the second control transistor 27. The third conductive signal line 29c is disposed on a side of the protection layer 28 opposite to the second metal layer and located between the first conductive signal line 29a and the second conductive signal line 29b, and a portion of the third conductive signal line 29c is embedded in the protection layer 28 to the second electrode 26b and electrically connected to the second electrode 26b, and a portion of the third conductive signal line 29c penetrates through the protection layer 28 and penetrates through the insulating layer 23 and is electrically connected to the second control electrode 27 c. At this time, the second electrode 26b and the second control electrode 27c are electrically connected through the third conductive signal line 29 c. Optionally, one end of the third conductive signal line 29c near the first pad 11 is embedded in the protective layer 28 and penetrates through the protective layer 28 to be electrically connected with the second electrode 26b, and the other end of the third conductive signal line 29c near the second pad 12 penetrates through the protective layer 28 and the insulating layer 23 and is electrically connected with one end of the second control electrode 27c near the first control electrode 26c, so as to shorten the wiring distance and save the wiring space.
In the embodiment of the present application, the light emitting chip 10 and the driving circuit 20 are overlapped at a certain distance, so that the light emitting chip 10 and the driving circuit 20 do not need to be separately laid out, and the layout space of the display panel 100 is effectively saved. According to the technical scheme, more pixel units can be distributed on the display panel 100, so that the PPI and the resolution of the display panel 100 are effectively improved, and the display effect of the display panel is further improved. Meanwhile, the saved space can be used for laying other electronic components, so that the space utilization rate of the display panel 100 is improved.
In addition, since the light emitting chip 10 and the driving circuit 20 are spaced a certain distance and are overlapped, the wiring distance for realizing electrical connection between the light emitting chip 10 and the driving circuit 20 can be effectively shortened, and the wiring cost is further effectively reduced.
Referring to fig. 4 and fig. 5 together, fig. 4 is a schematic structural diagram of the display panel 100 shown in fig. 1. Fig. 5 is a schematic top view of the display panel shown in fig. 1. As shown in fig. 4, in other embodiments, the third electrode 27a is farther from the second voltage signal line Vss than the fourth electrode 27b, that is, the distance between the third electrode 27a and the second voltage signal line Vss is greater than the distance between the fourth electrode 27b and the second voltage signal line Vss. The orthographic projection of the third electrode 27a on the light emitting chip 10 is not located on the light emitting chip 10.
In the embodiment of the present application, the third electrode 27a is electrically connected to the second voltage signal line Vss.
In this embodiment, the second control transistor 27 is not integrally disposed below the light emitting chip 10, and the temperature rise of the control transistor causes the mobility of carriers to be reduced while the threshold voltage is reduced, so that the leakage current of the transistor is obviously increased, and the second control transistor 27 is electrically connected to the light emitting chip 10, and the mobility and the leakage current directly affect the light emitting effect of the light emitting chip 10, so that the second control transistor is disposed in a region of the light emitting chip 10 not corresponding to the driving circuit 20, so as to ensure the display effect.
In this way, the first voltage signal line Vdd, the second voltage signal line Vss and the first control transistor 26 are disposed below the light emitting chip 10, and the second control transistor 27 is disposed in a region of the light emitting chip 10 not corresponding to the driving circuit 20, so that a space for laying out the driving circuit 20 is saved, and a display effect of the light emitting chip 10 is ensured.
Referring to fig. 6, fig. 6 is a flow chart illustrating a manufacturing method of the display panel 100 shown in fig. 1. Based on the same concept, the present application also provides a manufacturing method for the display panel 100 described above, for manufacturing the display panel shown in fig. 1 to 5. The content of the display panel related to the manufacturing method of the display panel provided in the embodiment of the present application is referred to the related description of the display panel related to the above embodiment, and is not repeated herein. Referring to fig. 6, the method for manufacturing the display panel at least includes the following steps.
S10, manufacturing a driving circuit 20.
In the embodiment of the present application, referring to fig. 7, fig. 7 is a schematic flow chart of step S10 in the manufacturing method of the display panel shown in fig. 6. In the embodiment of the present application, referring to fig. 1 to 4 together, the step S10 mainly includes the following steps.
S11, providing a substrate 21, and arranging a first metal layer on part of the surface of the substrate 21;
s12, disposing an insulating layer 23 on a surface of the first metal layer facing away from the substrate 21, wherein the insulating layer 23 does not cover the surface of the substrate 21;
s13, disposing a second metal layer on a part of the surface of the insulating layer 23 facing away from the first metal layer;
s14, arranging a protective layer on the surface of the second metal layer, which is opposite to the first metal layer, and the surface of the second metal layer, which is not covered by the insulating layer 23;
s15, a conductive layer is disposed to electrically connect the first control transistor 26 and the second control transistor 27.
S20, electrically connecting the first voltage signal line Vdd of the driving circuit 20 with the first pad 11 of the light emitting chip 10, and electrically connecting the fourth electrode 27b of the driving circuit 20 with the second pad 12 of the light emitting chip 10.
In the present embodiment, the conductive layer includes a first conductive signal line 29a and a second conductive signal line 29b. The first conductive signal line 29a is disposed on a side of the protection layer 28 opposite to the first voltage signal line Vdd and is embedded in the protection layer 28, one side of the first conductive signal line 29a embedded in the protection layer 28 is electrically connected to the first voltage signal line Vdd, and the other side of the first conductive signal line 29a is electrically connected to the first pad 11. At this time, the first pad 11 and the first voltage signal line Vdd are electrically connected.
The second conductive signal line 29b is disposed on a side of the protection layer 28 opposite to the fourth electrode 27b and is embedded in the protection layer 28, one side of the second conductive signal line 29b embedded in the protection layer 28 is electrically connected to the fourth electrode 27b, and the other side of the second conductive signal line 29b is electrically connected to the second pad 12. At this time, the second pad 12 and the fourth electrode 27b are electrically connected.
S30, binding and connecting (bonding) two opposite ends of the chip body 13 of the light emitting chip 10 with the first pad 11 and the second pad 12 respectively, so as to overlap the light emitting chip 10 and the driving circuit 20 at a certain distance and realize signal transmission between the two.
In this embodiment of the present application, the chip body 13 and the first pad 11 may be connected in a binding manner through solder paste, the chip body 13 and the second pad 12 may be connected in a binding manner through solder paste, and then the chip body 13 is connected between the first pad 11 and the second pad 12 in a binding manner, so that the light emitting chip 10 and the driving circuit 20 are overlapped in a direction perpendicular to a connection line of the first pad 11 and the second pad 12 of the light emitting chip 10 and a line which is not coplanar with a plane where the connection line is located, and signal transmission between the two is implemented.
Specifically, the first pad 11 and the second pad 12 are coated with solder paste, and then one end of the chip body 13 is connected with the first pad 11 through solder paste binding, and the other end of the chip body 13 is connected with the second pad 12 through solder paste binding.
Based on the same conception, the application also provides a display device, which comprises a power supply module and the display panel, wherein the power supply module is electrically connected with the display panel and is used for providing electric energy for executing picture display of the display panel.
In summary, in the display panel 100, the manufacturing method thereof, and the display device of the present application, the light emitting chip 10 and the driving circuit 20 are disposed at a certain distance and overlapped, that is, the components such as the first voltage signal line Vdd, the second voltage signal line Vss, and the first control transistor 26 are disposed under the light emitting chip 10, so that the light emitting chip 10 and the driving circuit 20 do not need to be separately laid out, and the layout space of the display panel 100 is effectively saved. According to the technical scheme, more pixel units can be distributed on the display panel 100, so that PPI and resolution of the display panel 100 are effectively improved. Moreover, the saved space can be used for laying other electronic components, so that the pixel density unit (PPI), resolution and space utilization of the display panel 100 are improved, and further the display effect of the display panel is improved, which is beneficial to pushing the display panel 100 to the application of Virtual Reality technology (VR). Meanwhile, since the light emitting chip 10 and the driving circuit 20 are spaced a certain distance and are overlapped, the wiring distance for realizing electrical connection between the light emitting chip 10 and the driving circuit 20 is effectively shortened, and the wiring cost is effectively reduced.
In addition, the first control transistor 26 is disposed below the light emitting chip 10, and heat is generated after the light emitting chip 10 is powered on, so that the temperature of the first control transistor 26 is raised, and the threshold voltage of the transistor is reduced, thereby improving the charging efficiency of the first control transistor 26, avoiding the problem of insufficient charging, helping the first control transistor 26 to be correctly in a conductive state, and improving the display effect of the display panel 100.
It should be noted that, when the threshold voltage is lowered due to the temperature rise of the control transistor, the mobility of carriers is lowered, the leakage current of the transistor is significantly increased, and the second control transistor 27 is electrically connected to the light emitting chip 10, and the mobility and the leakage current directly affect the light emitting effect of the light emitting chip 10, so that the second control transistor 27 cannot be placed below the light emitting chip 10 to avoid affecting the display effect.
In this way, the first voltage signal line Vdd, the second voltage signal line Vss and the first control transistor 26 are disposed below the light emitting chip 10, and the second control transistor 27 is disposed in a region of the light emitting chip 10 not corresponding to the driving circuit 20, so that a space for laying out the driving circuit 20 is saved, and a display effect of the light emitting chip 10 is ensured.
All possible combinations of the technical features in the above embodiments are described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
In the description of the present specification, reference to the terms "one embodiment," "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
It is to be understood that the above examples represent only a few embodiments of the present application, which are described in more detail and detail, but are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. The display panel comprises a light emitting chip and a driving circuit electrically connected with the light emitting chip, and is characterized in that the light emitting chip is overlapped with the driving circuit and is arranged at intervals, the light emitting chip comprises a first pad and a second pad which are oppositely arranged, the driving circuit comprises a first voltage signal wire and a second voltage signal wire, the first pad is electrically connected with the first voltage signal wire, the second pad is electrically connected with the second voltage signal wire, the driving circuit is used for generating a voltage signal, transmitting the voltage signal to the first pad through the first voltage signal wire, and the light emitting chip receives the voltage signal and emits light according to the voltage signal; the light emitting chip also transmits the voltage signal to the second voltage signal line through the second pad.
2. The display panel of claim 1, wherein the driving circuit further comprises a data line, a scan line, a first control transistor, and a second control transistor, a control terminal of the first control transistor receiving a control signal from the scan line, a first terminal of the first control transistor receiving a data signal from the data line, a second terminal of the first control transistor being electrically connected to a control terminal of the second control transistor, the first control transistor transmitting the data signal to the second control transistor according to the control signal;
The first end of the second control transistor is electrically connected to the second pad, receives the voltage signal from the second pad, the second end of the second control transistor is electrically connected to a second voltage signal line, and the second control transistor receives the data signal and is in a conducting state to receive the voltage signal from the second pad and transmit the voltage signal to the second voltage signal line;
the first voltage signal line, the second voltage signal line, the data line and the scanning line are arranged on one side of the light-emitting chip, and orthographic projection parts of the first voltage signal line, the second voltage signal line, the data line and the scanning line on the light-emitting chip are positioned on the light-emitting chip;
the first control transistor and the second control transistor are arranged on the same side of the light-emitting chip with the data line, and the orthographic projection of the first control transistor on the light-emitting chip is positioned on the light-emitting chip.
3. The display panel of claim 2, wherein the driving circuit further comprises a substrate base, a first metal layer, an insulating layer, a second metal layer, a protective layer, and a conductive layer,
The first metal layer is arranged in a partial area on the substrate and is used for arranging the scanning lines;
the insulating layer is arranged on one side of the first metal layer, which is opposite to the substrate, and the surface of the substrate, which is not covered by the first metal layer, and is used for separating electric signals between the first metal layer and the second metal layer;
the second metal layer is arranged on a part of the surface of the insulating layer, which is opposite to the first metal layer, and is used for laying the first voltage signal line and the second voltage signal line, and the first control transistor and the second control transistor are formed on the first metal layer and the second metal layer;
the protective layer is arranged on the side, facing away from the insulating layer, of the second metal layer, and the surface, not covered by the insulating layer, of the second metal layer;
the conducting layer is arranged on one side of the protective layer, which is opposite to the substrate, and is used for electrically connecting the light-emitting chip with the driving circuit, and electrically connecting the first control transistor and the second control transistor.
4. The display panel according to claim 3, wherein the first metal layer includes a first control electrode and a second control electrode, the first control electrode and the second control electrode are disposed at intervals, the first control electrode is used for laying the scan line and being used as a control end of the first control transistor, the second control electrode is used as a control end of the second control transistor, and an orthographic projection of the first control electrode and the second control electrode on the light emitting chip is located on the light emitting chip;
The second metal layer is used for setting the first voltage signal line and the second voltage signal line, the first voltage signal line is arranged on one side of the second metal layer, and the second voltage signal line and the first voltage signal line are arranged at intervals.
5. The display panel according to claim 4, wherein the second metal layer includes a first electrode, a second electrode, a third electrode, and a fourth electrode, the first electrode and the second electrode are disposed between the first voltage signal line and the second voltage signal line with a first gap therebetween, and the first gap corresponds to a position of the first control electrode, the first electrode, the second electrode, and the first control electrode are a first end, a second end, and a control end of the first control transistor;
the third electrode and the fourth electrode are arranged on one side, far away from the first voltage signal line, of the second voltage signal line, a second gap is formed between the third electrode and the fourth electrode, the second gap corresponds to the position of the second control electrode, the third electrode, the fourth electrode and the second control electrode serve as a second end, a first end and a control end of the second control transistor, and the third electrode is electrically connected with the second voltage signal line.
6. The display panel of claim 5, wherein a distance between the third electrode and the second voltage signal line is smaller than a distance between the fourth electrode and the second voltage signal line.
7. The display panel of claim 6, wherein a distance between the third electrode and the second voltage signal line is greater than a distance between the fourth electrode and the second voltage signal line, and an orthographic projection of the third electrode on the light emitting chip is not located on the light emitting chip.
8. The display panel of any one of claims 5-7, wherein the conductive layer comprises a first conductive signal line, a second conductive signal line, and a third conductive signal line, the first conductive signal line is disposed on a side of the protective layer opposite to the first voltage signal line and embedded in the protective layer, one side of the first conductive signal line embedded in the protective layer is electrically connected to the first voltage signal line, and the other side of the first conductive signal line is electrically connected to the first pad;
the second conductive signal wire is arranged on one side of the protection layer, which is opposite to the fourth electrode, and is embedded into the protection layer, one side of the second conductive signal wire, which is embedded into the protection layer, is electrically connected with the fourth electrode, and the other side of the second conductive signal wire is electrically connected with the second liner;
The third conductive signal wire is used for electrically connecting the second electrode and the second control electrode, is arranged on one side of the protection layer opposite to the second metal layer and is positioned between the first conductive signal wire and the second conductive signal wire, part of the third conductive signal wire is embedded into the protection layer to the second electrode and is electrically connected with the second electrode, and part of the third conductive signal wire penetrates through the protection layer and penetrates through the insulating layer and is electrically connected with the second control electrode.
9. The display panel of claim 8, wherein the first conductive signal line is positioned corresponding to the first pad, and an orthographic projection of the first pad on the second metal layer is positioned on the first conductive signal line;
the position of the second conductive signal line corresponds to the second pad, and the second pad is orthographic projected on the second metal layer and positioned on the fourth electrode;
one side of the third conductive signal wire is embedded into the protective layer and is electrically connected with the second electrode, and the other side of the third conductive signal wire penetrates through the insulating layer and is electrically connected with one side, close to the first control electrode, of the second control electrode.
10. A display device, characterized in that the display device comprises a power module and a display panel according to any one of claims 1-9, the power module being electrically connected to the display panel for providing power for performing picture display on the display panel.
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| CN202310388722.8A CN116314242A (en) | 2023-04-03 | 2023-04-03 | Display panel and display device |
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| CN202310388722.8A CN116314242A (en) | 2023-04-03 | 2023-04-03 | Display panel and display device |
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| CN114220397A (en) * | 2022-02-10 | 2022-03-22 | 上海天马微电子有限公司 | Display panel, driving method thereof and display device |
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| US20200321390A1 (en) * | 2019-04-04 | 2020-10-08 | Bor-Jen Wu | System and Method for Making Micro LED Display |
| CN112750854A (en) * | 2021-02-04 | 2021-05-04 | 上海天马微电子有限公司 | Display panel and display device |
| CN113345946A (en) * | 2021-05-31 | 2021-09-03 | 京东方科技集团股份有限公司 | Display substrate, manufacturing method and control method thereof, and display device |
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