CN116314225A - Image sensor and method for manufacturing the same - Google Patents
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- CN116314225A CN116314225A CN202310180386.8A CN202310180386A CN116314225A CN 116314225 A CN116314225 A CN 116314225A CN 202310180386 A CN202310180386 A CN 202310180386A CN 116314225 A CN116314225 A CN 116314225A
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Abstract
The invention provides a preparation method of an image sensor, which comprises the following steps: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a grid electrode positioned on the substrate, and a photodiode region is formed in the substrate; forming a first side wall on the side wall of the grid electrode; performing ion implantation on the substrate to form a clamping region on the photodiode region; and forming a second side wall on the side wall of the first side wall. According to the preparation method of the image sensor, the clamping area is formed before the second side wall is formed, the clamping area can cover the photodiode area under the second side wall, the coverage area of the clamping area on the photodiode area is enlarged, and therefore the electron overflow of the photodiode area is effectively prevented, and the generation of white pixels is reduced. The invention also provides an image sensor, wherein the clamping area of the image sensor can cover the photodiode area under the second side wall, so that the electron overflow of the photodiode area is effectively prevented, and the generation of white pixels is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductor manufacturing, in particular to an image sensor and a preparation method thereof.
Background
An image sensor (ImageSensor) is a component that converts an optical image into an electrical signal, and mainly includes a CMOS image sensor and a CCD image sensor. CMOS image sensors are increasingly being referred to as the mainstream of image sensors because of their manufacturing process being compatible with existing integrated circuit manufacturing processes, and having advantages of low manufacturing cost, low power consumption, etc. compared to CCD image sensors. The reduction of white pixels to improve the performance of CMOS image sensors has been a hot spot research problem, which is one of the key factors limiting the performance and quality of CMOS image sensors.
Disclosure of Invention
The present invention aims to reduce white pixels of an image sensor, thereby improving the performance of the image sensor.
In order to achieve the above object, the present invention provides a method for manufacturing an image sensor, comprising the steps of:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a grid electrode positioned on the substrate, and a photodiode region is formed in the substrate;
forming a first side wall on the side wall of the grid electrode;
performing ion implantation on the substrate to form a clamping region on the photodiode region;
and forming a second side wall on the side wall of the first side wall.
Preferably, the step of ion implanting the substrate to form a clamping region on the photodiode region includes:
forming a first patterned photoresist layer on the gate and the substrate, wherein the first patterned photoresist layer exposes a portion of the substrate on one side of the gate, and the portion of the substrate on one side of the gate comprises a portion of the photodiode region;
ion implantation is carried out on the substrate by taking the first patterned photoresist layer as a mask so as to form a clamping area on the photodiode area;
the first patterned photoresist layer is removed.
Preferably, the semiconductor structure further comprises a gate dielectric layer between the substrate and the gate electrode.
Preferably, the photodiode region includes a first sub-region, a second sub-region and a third sub-region, the first sub-region is located at the lowest layer of the photodiode region, the second sub-region is located on the first sub-region, and the third sub-region is located on the second sub-region.
Preferably, the substrate includes a well region adjacent to the photodiode region.
Preferably, the substrate comprises a first doping type substrate, the photodiode region comprises a second doping type photodiode region, and the clamping region comprises a first doping type clamping region.
Preferably, the first doping type comprises a P-type and the second doping type comprises an N-type.
Preferably, the ion implantation dose in the step of ion implanting the substrate is 10 13 /cm 2 ～10 15 /cm 2 。
Meanwhile, to achieve the above object, the present invention also provides an image sensor including:
a substrate in which a photodiode region is formed;
a gate formed on the substrate;
the first side wall and the second side wall are formed on the side wall of the grid electrode;
the clamping area is formed in the substrate and is positioned on the photodiode area, and the clamping area covers the photodiode area under the second side wall;
the image sensor is formed by the preparation method of the image sensor.
Preferably, the photodiode region includes a first sub-region, a second sub-region and a third sub-region, the first sub-region is located at the lowest layer of the photodiode region, the second sub-region is located on the first sub-region, and the third sub-region is located on the second sub-region.
Compared with the prior art, the invention has the following advantages:
in the method for manufacturing the image sensor in the prior art, the clamping area is formed after the second side wall is formed, so that the clamping area cannot cover the photodiode area under the second side wall, and electrons in the photodiode area under the second side wall overflow to form white pixels. According to the preparation method of the image sensor, the clamping area is formed before the second side wall is formed, and can extend to the position below the second side wall and cover the photodiode area below the second side wall, so that the coverage area of the clamping area on the photodiode area is enlarged, the electron overflow of the photodiode area is effectively prevented, the generation of white pixels is reduced, and the performance of the image sensor is improved. In addition, the preparation method of the image sensor provided by the invention only needs to properly optimize the working procedures of the existing preparation process of the image sensor, does not need to greatly change the existing process flow, and improves the compatibility with the existing process flow. Compared with the image sensor in the prior art, the clamp area is larger, and can effectively prevent electrons in the photodiode area from overflowing, reduce the generation of white pixels and improve the performance of the image sensor.
Drawings
FIGS. 1A-1C are schematic views showing a semiconductor structure of steps of a method for fabricating an image sensor;
FIG. 2 is a flowchart illustrating steps of a method for fabricating an image sensor according to an embodiment;
fig. 3 to fig. 6 are schematic semiconductor structures of steps of a method for manufacturing an image sensor according to an embodiment;
wherein reference numerals are as follows:
1A-1C, 00-substrate; 01-gate dielectric layer; 02-gate; 03-photodiode region; 031-first subregion; 032-a second subregion; 033-a third subregion; 04-isolation structure; 05-cell P-well; 06-deep P-well; 07-a first side wall; 08-a second side wall; 09-clamping region;
in FIGS. 3-6, 10-substrate; 11-gate dielectric layer; 12-grid; 13-photodiode region; 131-a first subregion; 132-a second subregion; 133-a third subregion; 14-isolation structures; 15-cell P-well; 16-deep P-well; 17-a first side wall; 18-clamping region; 19-a second side wall.
Detailed Description
To make the objects, advantages and features of the present invention more apparent, the image sensor and the method for manufacturing the same according to the present invention will be described in further detail with reference to the accompanying drawings. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Referring to fig. 1A to 1C, a conventional method for manufacturing an image sensor includes the following steps:
first, referring to fig. 1A, a semiconductor structure is provided, the semiconductor structure includes a substrate 00, a gate dielectric layer 01 formed on the substrate 00, and a gate 02 formed on the gate dielectric layer 01, and a photodiode region 03 is further formed in the substrate 00. The photodiode region 03 may be an N-type photodiode region, for example. The photodiode region 03 may include a first sub-region 031, a second sub-region 032, and a third sub-region 033, the first sub-region 031 being the lowest layer of the photodiode region 03, the second sub-region 032 being located on the first sub-region 031, and the third sub-region 033 being located on the second sub-region 032. An isolation structure 04 may also be formed in the substrate 00, and the isolation structure 04 may be a Shallow Trench Isolation (STI) structure. A well region for isolating the photodiode region 03 may also be formed in the substrate 00, and may include, for example, a cell P-well 05 and a deep P-well 06.
Then, referring to fig. 1B, a first sidewall 07 is formed on a sidewall of the gate 02 and a second sidewall 08 is formed on a sidewall of the first sidewall 07. The specific structure and the forming process of the first side wall 07 and the second side wall 08 can refer to the prior art, and are not described herein.
Thereafter, referring to fig. 1C, a clamping region 09 is formed on the photodiode region 03. The specific method comprises the following steps: forming a patterned photoresist layer on the gate 02 and the gate dielectric layer 01, wherein the patterned photoresist layer exposes the substrate 00 on one side of the gate 02, and the substrate 00 on one side of the gate 02 at least comprises a part of the photodiode region 03; the first ion implantation is performed on the substrate 00 using the first patterned photoresist layer as a mask to form the clamping region 09 on the photodiode region 03. The doping types of the clamping region 09 and the photodiode region 03 are different, so that the clamping region 09 and the photodiode region 03 form a PN junction, and a space charge region of the PN junction prevents electrons in the photodiode region 03 from overflowing onto the substrate 00.
In the above method for manufacturing an image sensor, since the clamping region 09 is formed after the second sidewall 08, the clamping region 09 cannot cover the photodiode region 03 under the second sidewall 08, so that electrons in the photodiode region 03 overflow onto the substrate 00, and the overflow electrons form dark current, which generates white pixels.
Based on the analysis, the inventor provides a preparation method of the image sensor after researching, which can effectively reduce white pixels of the image sensor, thereby improving the performance of the image sensor.
Referring to fig. 2, the method for manufacturing an image sensor provided by the invention includes the following steps:
step S1: providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a grid electrode positioned on the substrate, and a photodiode region is formed in the substrate;
step S2: forming a first side wall on the side wall of the grid electrode;
step S3: and performing ion implantation on the substrate to form a clamping region on the photodiode region.
Step S4: and forming a second side wall on the side wall of the first side wall.
Referring to fig. 3, step S1 is performed to provide a semiconductor structure including a substrate 10 and a gate 12 on the substrate 10, wherein a photodiode region 13 is formed in the substrate 10.
In the present embodiment, the substrate 10 includes a P-type substrate, but is not limited thereto, and may be an N-type substrate, for example. The P-type substrate can be a P-type epitaxial layer formed on a base, or a P-type base. The substrate includes, but is not limited to, a silicon substrate, but may be other suitable semiconductor substrates. The substrate 10 may also have formed therein an isolation structure 14 for defining an active region, and the isolation structure 14 may be a Shallow Trench Isolation (STI) structure. The process of forming the isolation structure 14 may refer to the prior art, and will not be described herein.
In this embodiment, a gate dielectric layer 11 may also be formed on the substrate 10, and the gate dielectric layer 11 may include SiO 2 A layer for covering the gate dielectric layer 11 on the substrate 10 by a corresponding thin film deposition process such as thermal oxidation process, wherein the gate dielectric layer 11 can be used for forming an insulating medium between the gate electrode 12 and the substrate 10, and can also be used as a sacrificial layer for subsequent ion implantation to protectThe substrate 10 is protected from ion implantation. After forming the gate dielectric layer 11, the gate electrode 12 is formed on the gate dielectric layer 11. The gate 12 may serve as the gate of a transfer transistor. The gate 12 may include a polysilicon gate, but is not limited thereto. The method for forming the gate 12 may refer to the prior art, and will not be described herein.
A photodiode region 13 is also formed in the substrate 10, and in this embodiment, the photodiode region 13 includes a first sub-region 131, a second sub-region 132, and a third sub-region 133, where the first sub-region 131 is located at the lowest layer of the photodiode region 13, the second sub-region 132 is located on the first sub-region 131, and the third sub-region 133 is located on the second sub-region 132. The photodiode region 13 is an ion doped region, and by setting the first sub-region 131, the second sub-region 132 and the third sub-region 133 with different concentrations, the ion concentration gradient of the photodiode region 13 can be reduced, and the dopant ion concentration gradient at the interface between the photodiode region 13 and the substrate 10 and the interface between the photodiode region 13 and the clamp region formed subsequently can be adjusted, so as to form a depletion layer meeting the expectations. In this embodiment, the first sub-region 131 may be a first deep N-well photodiode region (DNPPD 1), the second sub-region 132 may be a second deep N-well photodiode region (DNPPD 2), and the third sub-region 133 may be an N-type photodiode region (NPPD); the first sub-region 131 and the second sub-region 132 may be formed by a corresponding well region ion implantation process before forming the gate 12; the third sub-region 133 may be formed by a corresponding ion implantation process after the gate electrode 12 is formed. The doping ion concentration and the width of the first sub-region 131, the second sub-region 132 and the third sub-region 133 in the horizontal direction are not limited, and may be determined according to the actual process requirements.
In this embodiment, the gate electrode 12 covers a part of the photodiode region 13, and the gate electrode 12 may also cover the photodiode region 13 entirely. Since the gate dielectric layer 11 may be further included between the gate electrode 12 and the photodiode region 13, the gate electrode 12 may not directly cover the photodiode region 13, and a projection area of the gate electrode 12 on the upper surface of the gate dielectric layer 11 may partially or entirely cover a projection area of the photodiode region 13 on the upper surface of the gate dielectric layer 11. This design ensures effective contact between the photodiode region 13 and the gate 12, thereby ensuring that the photodiode region 13 is electrically connected to the gate 12 when the image sensor is in operation.
A well region may also be formed in the substrate 10; the well region has a doping type different from that of the photodiode region. Several photodiode regions 13 may be formed on one active region, and the well regions are used to isolate adjacent photodiode regions 13 to prevent crosstalk between the adjacent photodiode regions 13. In the present embodiment, the well region is preferably adjacent to the photodiode region 13 to achieve a better isolation effect, but is not limited thereto. In this embodiment, the photodiode region 13 includes an N-type photodiode region, the well region includes a P-type well region, and further, the P-type well region may include a cell P-well 15 (CPW) and a deep P-well 16 (DPW), and the deep P-well 16 is located in the substrate 10 deeper below the cell P-well 15. In the present embodiment, the isolation structure 14 and the cell P-well 15 are provided separately from each other; in another embodiment, the isolation structure 14 may be disposed in the cell P-well 15. The cell P-well 15, the deep P-well and the isolation structure 14 form an isolation region that more effectively electrically isolates the adjacent photodiode region 13 from the adjacent active region. The unit P-well 15 and the deep P-well 16 may be formed by a corresponding well region ion implantation process, and reference may be made to the prior art, which is not described herein.
Referring to fig. 4, step S2 is performed to form a first sidewall 17 on the sidewall of the gate 12.
In this embodiment, the first side wall 17 may comprise SiO 2 /Si 3 N 4 A laminated structure (ON structure), the forming method comprising: first depositing a thickness (e.g
) SiO of (2) 2 Overlying the substrate 10 and the gate 12 and then depositingAccumulate a certain thickness (e.g.)>
) Si of (2) 3 N 4 Etching Si by anisotropic first dry etching 3 N 4 Layer, dry etching stop at SiO 2 The layers form said first side wall 17. The first dry etching does not need mask and photoetching, and can simplify the process flow. The first side wall 17 is not limited to the ON structure, but may be other suitable structure; the first side wall 17 may be formed by other suitable methods, which will not be described in detail herein.
Referring to fig. 5, step S3 is performed to perform ion implantation on the substrate 10 to form a clamping region 18 on the photodiode region 13.
The clamping region 18, also called a fixed layer (pinnedlayer), serves as a protective layer for preventing charges of the photodiode region 13 from overflowing onto the substrate 10. The clamping region 18 is generally of a different doping type from the photodiode region 13 to form a PN junction therebetween, and a space charge region formed by the PN junction prevents charge of the photodiode region 13 from overflowing.
The substrate 10 comprises a first doping type substrate, the photodiode region 13 comprises a second doping type photodiode region, and the clamping region 18 comprises a first doping type clamping region. The first doping type comprises a P type, and the second doping type comprises an N type; alternatively, the first doping type includes an N-type and the second doping type includes a P-type. For example, in this embodiment, the first doping type is P-type, the second doping type is N-type, that is, the substrate 10 includes a P-type substrate, the photodiode region 13 includes an N-type photodiode region, the clamping region 18 includes a P-type clamping region, and the substrate 10, the photodiode region 13 and the clamping region 18 form a P-N-P depletion region, which is a photosensitive region of the photodiode. The P-type doped impurity ions can be boron ions or boron fluoride ions, and can also be other suitable element ions or compound ions; the impurity ions of the N-type doping can be arsenic ions or phosphorus ions, and can also be other suitable simple substance ions or compound ions.
The formation of the clamping region 18 after the formation of the first sidewall 17 ensures that the clamping region 18 (e.g., P-type clamping region) does not cover the photodiode region 13 under the first sidewall 17, i.e., the clamping region 18 is isolated from the well region (e.g., P-type well region) by the photodiode region 13 (e.g., N-type photodiode region).
In the present embodiment, the step of forming the clamping region 18 on the photodiode region 13 includes: forming a first patterned photoresist layer on the gate electrode 12 and the substrate 10, the first patterned photoresist layer exposing a portion of the substrate 10 on one side of the gate electrode 12, the portion of the substrate 10 on one side of the gate electrode 12 including a portion of the photodiode region 13; performing a first ion implantation on the substrate 10 using the first patterned photoresist layer as a mask to form the clamping region 18 on the photodiode region 13; and removing the first patterned photoresist layer. The implantation dose of the first ion implantation is preferably 10 13 /cm 2 ～10 15 /cm 2 Other process parameters of the first ion implantation may be determined according to actual process requirements, and are not limited herein, to obtain the clamping region 18 with a suitable doping concentration.
In this embodiment, the first ion implantation uses the first patterned photoresist layer as a mask, and the first ion implantation uses the isolation structure 14 and the first sidewall 17 as a mask, so that one side (left side in fig. 5) of the clamping region 18 extends to the isolation structure 14, and the other side (right side in fig. 5) is aligned with the boundary of the first sidewall 17.
Referring to fig. 6, step S4 is performed to form a second sidewall 19 on the sidewall of the first sidewall 17.
In this embodiment, the second sidewall may include SiO 2 /Si 3 N 4 /SiO 2 The forming method of the laminated structure, namely the ONO structure, comprises the following steps: first, a thickness (e.g
) SiO of (2) 2 Layer, then at the SiO 2 A layer is deposited to a certain thickness (e.g.)>
) Si of (2) 3 N 4 A layer is thereafter deposited to a greater thickness (e.g
) SiO of (2) 2 Layer, etching SiO by using second dry etching 2 Layer is stopped at Si 3 N 4 The layer is etched by dry etching for the third time 3 N 4 Layer is stopped at SiO 2 A layer. The second sidewall 19 is not limited to the ONO structure, but may be any other suitable structure; the second side wall 19 may be formed by other suitable methods, which will not be described herein.
In this embodiment, the clamp region 18 is formed before the second sidewall 19 is formed, so that the clamp region 18 extends below the second sidewall 19 and covers the photodiode region 13 below the second sidewall 19, thereby enlarging the coverage area of the clamp region 18 on the photodiode region 13, thereby more effectively blocking the electron overflow of the photodiode region 13, reducing the generation of white pixels, and improving the performance of the device.
Based on the above-mentioned method for manufacturing the image sensor, the present invention further provides an image sensor, and fig. 6 may be regarded as a schematic structural diagram of an embodiment of the image sensor provided by the present invention.
Referring to fig. 6, an image sensor provided by the present invention at least includes:
a substrate 10, in which a photodiode region 13 is formed in the substrate 10;
a gate electrode 12 formed on the substrate 10;
a first side wall 17 and a second side wall 19 formed on the side wall of the gate 12;
a clamping region 18 formed in the substrate 10, the clamping region 18 being located on the photodiode region 13, the clamping region 18 covering the photodiode region 13 under the second sidewall 19;
the image sensor is formed using the method of manufacturing an image sensor as described above.
In this embodiment, a gate dielectric layer 11 may be further formed on the substrate, the gate electrode 12 is formed on the gate dielectric layer 11, and the gate dielectric layer 11 is used for electrically isolating the gate electrode 12 from the substrate.
In this embodiment, the photodiode region 13 preferably includes a first sub-region 131, a second sub-region 132, and a third sub-region 133, wherein the first sub-region 131 is located at the lowest layer of the photodiode region 13, the second sub-region 132 is located on the first sub-region 131, and the third sub-region 133 is located on the second sub-region 132. The first, second and third sub-regions 132, 133 may have different doping concentrations to adjust the ion concentration gradient of the photodiode region 13 and to adjust the doping concentration gradient at the interface of the photodiode region 13 and the substrate 10 and at the interface of the photodiode region 13 and the clamping region 18, thereby forming a depletion layer in accordance with the expectation. The first sub-region 131 may be a first deep N-well photodiode region (DNPPD 1), the second sub-region 132 may be a second deep N-well photodiode region (DNPPD 2), and the third sub-region 133 may be an N-type photodiode region (NPPD).
The substrate 10 may further have a well region formed therein, the well region having a doping type different from that of the photodiode region, the well region being for isolating the photodiode region. In this embodiment, the photodiode region is a P-type photodiode region, and the well region is a P-type well region; further, the P-type well region may include a cell P-well 15 (CPW) and a deep P-well 16 (DPW), the deep P-well 16 being located in the substrate 10 deeper below the cell P-well 15. Isolation structures 14, which may be Shallow Trench Isolation (STI) structures, may also be formed in the substrate.
In the image sensor in the prior art, the clamping area cannot cover the photodiode area under the second side wall, so that the charge protection of the clamping area to the photodiode area is reduced. In the image sensor provided in this embodiment, since the clamping area 18 covers the photodiode area 13 under the second sidewall 19, compared with the image sensor in the prior art, the clamping area/is larger, so that the clamping area 18 can effectively prevent charges in the photodiode area 13 from overflowing onto the substrate, thereby reducing the generation of white pixels and improving the performance of the image sensor.
In summary, in the method for manufacturing an image sensor provided by the present invention, the clamping region is formed before the second sidewall is formed, so that the clamping region extends to the position below the second sidewall and covers the photodiode region below the second sidewall, and the coverage area of the clamping region on the photodiode region is enlarged, thereby more effectively blocking the electron overflow of the photodiode region, reducing the generation of white pixels, and improving the performance of the image sensor. In addition, the preparation method of the image sensor provided by the invention only needs to properly optimize the working procedures of the existing preparation process of the image sensor, does not need to greatly change the existing process flow, and improves the compatibility with the existing process flow. Compared with the image sensor in the prior art, the clamp area is larger, and can effectively prevent electrons in the photodiode area from overflowing, reduce the generation of white pixels and improve the performance of the image sensor.
In addition, it will be understood that while the invention has been described in terms of preferred embodiments, the above embodiments are not intended to limit the invention. Many possible variations and modifications of the disclosed technology can be made by anyone skilled in the art without departing from the scope of the technology, or the technology can be modified to be equivalent. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention still fall within the scope of the technical solution of the present invention. It is also to be understood that this invention is not limited to the particular methodology, compounds, materials, manufacturing techniques, uses, and applications described herein, as such may vary. It should also be understood that the terminology described herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a step" means a reference to one or more steps, and may include sub-steps. All conjunctions used should be understood in the broadest sense. Thus, the word "or" should be understood as being provided with a definition of a logical "or" rather than a definition of a logical "exclusive or" unless the context clearly indicates the contrary. Structures described herein will be understood to also refer to the functional equivalents of such structures. Language that may be construed as approximate should be construed unless the context clearly indicates the contrary.
Claims (10)
1. A method for manufacturing an image sensor, comprising the steps of:
providing a semiconductor structure, wherein the semiconductor structure comprises a substrate and a grid electrode positioned on the substrate, and a photodiode region is formed in the substrate;
forming a first side wall on the side wall of the grid electrode;
performing ion implantation on the substrate to form a clamping region on the photodiode region;
and forming a second side wall on the side wall of the first side wall.
2. The method of manufacturing an image sensor according to claim 1, wherein the step of performing ion implantation on the substrate to form a clamping region on the photodiode region comprises:
forming a first patterned photoresist layer on the gate and the substrate, wherein the first patterned photoresist layer exposes a part of the substrate on one side of the gate, and the part of the substrate on one side of the gate comprises a part of the photodiode region;
ion implantation is carried out on the substrate by taking the first patterned photoresist layer as a mask so as to form a clamping area on the photodiode area;
and removing the first patterned photoresist layer.
3. The method of manufacturing an image sensor of claim 1, wherein the semiconductor structure further comprises a gate dielectric layer between the substrate and the gate electrode.
4. The method of manufacturing an image sensor of claim 1, wherein the photodiode region comprises a first sub-region, a second sub-region and a third sub-region, the first sub-region being located at a lowermost layer of the photodiode region, the second sub-region being located on the first sub-region, and the third sub-region being located on the second sub-region.
5. The method of manufacturing an image sensor of claim 1, wherein a well region is further formed in the substrate, the well region being adjacent to the photodiode region.
6. The method of manufacturing an image sensor of claim 1, wherein the substrate comprises a first doping type substrate, the photodiode region comprises a second doping type photodiode region, and the clamping region comprises a first doping type clamping region.
7. The method of manufacturing an image sensor of claim 6, wherein the first doping type comprises a P-type and the second doping type comprises an N-type.
8. The method of manufacturing an image sensor according to claim 1, wherein the ion implantation dose in the step of ion implanting the substrate is 10 13 /cm 2 ～10 15 /cm 2 。
9. An image sensor, comprising:
a substrate having a photodiode region formed therein;
a gate formed on the substrate;
the first side wall and the second side wall are formed on the side wall of the grid electrode;
the clamping area is formed in the substrate and is positioned on the photodiode area, and the clamping area covers the photodiode area under the second side wall;
the image sensor is formed using the method for manufacturing an image sensor according to any one of claims 1 to 8.
10. The image sensor of claim 9, wherein the photodiode region comprises a first sub-region, a second sub-region, and a third sub-region, the first sub-region being located at a lowermost layer of the photodiode region, the second sub-region being located on the first sub-region, and the third sub-region being located on the second sub-region.
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