CN116314139A - Test structure and test method - Google Patents

Abstract

The application discloses a test structure and a test method, wherein the test structure is based on a flash memory device, and the flash memory device comprises: a first metal layer; a second metal layer over the first metal layer; the metal plugs are formed between the first metal layer and the second metal layer; the test structure comprises: an inscription unit for realizing the series connection of all the metal plugs; and the external unit is used for realizing the connection between the test structure and external test equipment. According to the scheme, the problem that the communication condition inside the device cannot be confirmed in real time in the related technology can be solved.

Description

Test structure and test method

Technical Field

The application relates to the technical field of semiconductor production, in particular to a test structure and a test method.

Background

Flash memory (flash) is a non-volatile memory with high storage speed and high density. The nod flash memory with the floating gate structure comprises a floating gate, a control gate, an ono (silicon oxide-silicon nitride-silicon oxide) structure arranged between the floating gate and the control gate, and a coupling oxide layer arranged between the floating gate and the substrate. The coupling oxide layer and ono structure play a key role in the performance of the flash memory device.

With the shrinking of Nord Flash devices, the back-end Pitch is also reduced, which increases the difficulty of the etching process. When the All-In-One etching process is performed, via open is easy to occur between two layers of metals, namely, the two layers of through holes between the metals are not etched through, so that the interconnection between the two layers of metals is invalid.

At present, the monitoring of the on-line back section All-In-One etching process can only be carried out by using microstructure measuring tools such as a scanning electron microscope, an ellipsometer and the like, and the communication condition inside the device can not be confirmed In real time.

Disclosure of Invention

The application provides a test structure and a forming method thereof, which can realize real-time monitoring of an on-line All-In-One etching process.

In a first aspect, embodiments of the present application provide a test structure, where the test structure is based on a flash memory device, the flash memory device includes:

a first metal layer;

a second metal layer over the first metal layer;

the metal plugs are formed between the first metal layer and the second metal layer;

the test structure comprises:

an inscription unit for realizing the series connection of all the metal plugs;

and the external unit is used for realizing the connection between the test structure and external test equipment.

In some embodiments, the external unit is a metal contact connected to the second metal layer.

In some embodiments, the test device is a source table of the picoampere scale.

In some embodiments, the test structure is formed in the flash memory device simultaneously during the formation of the first metal layer, the second metal layer, and the metal plug.

In some embodiments, the test structure is formed by a damascene process in synchronization with the first metal layer, the second metal layer, and the metal plug.

In some embodiments, the test structure is suitable for flash memory devices below 90 nm.

In a second aspect, an embodiment of the present application provides a testing method, where the testing method is based on the testing structure of the first aspect, and includes:

the testing device is connected through the external unit;

measuring monitoring parameters through the test equipment;

and judging whether the defect that the through hole is not etched through occurs or not based on the monitoring parameters.

In some embodiments, the monitored parameter is Rc, which refers to the sum of the resistances of the test structure, the first metal layer, the second metal layer, and the metal plug.

In some embodiments, the determining, based on the monitoring parameter, whether the defect condition that the through hole is not etched through includes:

and when the Rc exceeds a preset reasonable interval, judging that the defect that the through hole is not carved through occurs.

The technical scheme of the application at least comprises the following advantages:

1. by forming the test structure in the flash memory device, all the metal plugs in the flash memory device can be connected in series, and then after the test structure and the metal plugs are connected with external test equipment, the communication condition of all the metal plugs, namely the etching condition of the through holes, can be monitored, so that whether the defect that the through holes are not etched through or not can be timely judged.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a possible routing scheme in a flash memory device according to an exemplary embodiment of the present application;

FIG. 2 is a schematic diagram of a wiring pattern of a flash memory device after forming a test structure according to an exemplary embodiment of the present application;

fig. 3 is a flow chart of a test method provided in an exemplary embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made apparent and complete in conjunction with the accompanying drawings, in which embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

In the description of the present application, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of description of the present application and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.

In addition, the technical features described below in the different embodiments of the present application may be combined with each other as long as they do not collide with each other.

The application provides a test structure formed in a flash memory device under process. The flash memory device comprises a first metal layer, a second metal layer formed above the first metal layer, and a metal plug formed between the first metal layer and the second metal layer. The test structure comprises an internal connection unit and an external connection unit, wherein the internal connection unit is used for realizing the serial connection of all metal plugs, and the external connection structure is used for realizing the connection of the test structure and external test equipment. The test device may be a source meter of the picoampere scale, such as a semiconductor parameter analyzer.

By way of example, referring to fig. 1, one possible arrangement of a first metal layer 1, a metal plug 2 and a second metal layer 3 in a flash memory device is shown.

Referring to fig. 2, a schematic diagram of the above-mentioned flash memory device after forming the test structure is shown, wherein the first metal layer 1 and the second metal layer 3 are respectively formed with the internal connection unit 41, and the internal connection unit 41 may be made of the same material as the first metal layer 1 and/or the second metal layer 3. Two ends of the trace of the second metal layer 3 are respectively formed with an external unit 42, and the external unit 42 may be a metal contact, for example. After the inscription unit 41 is added, all the metal plugs 2 and the inscription unit 41, the external connection unit 42, and part of the lines in the first metal layer 1 and the second metal layer 3 can form a series line with external test equipment.

Further, the test structure is formed in the flash memory device simultaneously during the formation of the first metal layer 1, the second metal layer 3 and the metal plug 2.

The test structure may be formed simultaneously with the first metal layer 1, the second metal layer 3 and the metal plug 2 by a damascene process, for example.

Illustratively, the test structure may be formed as follows:

s101: a wafer structure coated with photoresist is provided.

S102: and adjusting the layout of the original wiring of the flash memory device, so as to add the wiring of the test structure into the layout.

S103: and updating the graph on the photomask based on the updated layout.

S104: and performing photoetching treatment to transfer the graph on the updated layout to the photoresist.

S105: and under the shielding of the photoresist, performing etching operation on the wafer to form grooves and through holes.

In this step, the grooves and the through holes can be etched simultaneously by an All-In-One Etch process.

S106: and performing metal filling treatment on the grooves and the through holes to form a first metal layer, a second metal layer, a metal plug and a test structure.

Wherein, S105 and S106 are damascene processes.

The test structure described above is mainly applicable to flash memory devices below 90nm, for example.

Based on the above test structure, the embodiment of the application also discloses a test method, referring to fig. 3, the method specifically may include the following:

s201: and the testing equipment is connected through an external unit.

The external unit may be two metal contacts formed at two ends of the trace of the second metal layer, the test device may be a semiconductor parameter analyzer, and positive and negative inputs of the test device are connected to the two metal contacts through probes, respectively.

S202: the monitoring parameters are measured by the test equipment.

Illustratively, the monitored parameter may be Rc, where Rc refers to the sum of the resistances of the test structure, the first metal layer, the second metal layer, and the metal plug. After the test equipment is started, all the metal plugs, the internal connection unit, the external connection unit, partial circuits in the first metal layer and the second metal layer and the serial circuit formed by the test equipment are conducted, so that Rc can be measured.

S203: based on the monitoring parameters, judging whether the defect that the through hole is not etched through occurs.

Illustratively, under normal conditions, the values of the monitoring parameters Rc are all within a preset reasonable interval. When the fault that the through hole is not carved through occurs, the series circuit is equivalent to the circuit breaking, so that the measured monitoring parameter Rc changes in order of magnitude, and the reasonable interval is exceeded. Therefore, when the monitoring parameter Rc exceeds a preset reasonable interval, the defect that the through hole is not engraved in the machining process can be judged.

It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While nevertheless, obvious variations or modifications may be made to the embodiments described herein without departing from the scope of the invention.

Claims (9)

1. A test structure, the test structure being based on a flash memory device, the flash memory device comprising:

a first metal layer;

a second metal layer over the first metal layer;

the metal plugs are formed between the first metal layer and the second metal layer;

the test structure comprises:

an inscription unit for realizing the series connection of all the metal plugs;

and the external unit is used for realizing the connection between the test structure and external test equipment.

2. The test structure of claim 1, wherein the external unit is a metal contact connected to the second metal layer.

3. The test structure of claim 1, wherein the test device is a source meter of the pico ampere scale.

4. The test structure of claim 1, wherein the test structure is formed in the flash memory device simultaneously during formation of the first metal layer, the second metal layer, and the metal plug.

5. The test structure of claim 4, wherein the test structure is formed simultaneously with the first metal layer, the second metal layer, and the metal plug by a damascene process.

6. The test structure of claim 1, wherein the test structure is suitable for use in a flash memory device below 90 nm.

7. A test method based on the test structure of any one of claims 1-6, comprising:

the testing device is connected through the external unit;

measuring monitoring parameters through the test equipment;

and judging whether the defect that the through hole is not etched through occurs or not based on the monitoring parameters.

8. The method of claim 7, wherein the monitored parameter is Rc, the Rc being the sum of the resistances of the test structure, the first metal layer, the second metal layer, and the metal plug.

9. The method according to claim 8, wherein the determining whether the defect condition that the through hole is not etched through occurs based on the monitoring parameter comprises:

and when the Rc exceeds a preset reasonable interval, judging that the defect that the through hole is not carved through occurs.

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