CN116314040A - Bearing substrate and manufacturing method thereof - Google Patents
Bearing substrate and manufacturing method thereof Download PDFInfo
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- CN116314040A CN116314040A CN202310593292.3A CN202310593292A CN116314040A CN 116314040 A CN116314040 A CN 116314040A CN 202310593292 A CN202310593292 A CN 202310593292A CN 116314040 A CN116314040 A CN 116314040A
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- angle
- substrate
- substrate body
- pentagon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention belongs to the technical field of semiconductor packaging, and particularly discloses a bearing substrate and a manufacturing method thereof, which are used for semiconductor packaging, and the bearing substrate comprises a substrate body, wherein the shape of the substrate body is pentagon with side length and inner angle not being equal, and the inner angle of the substrate body meets the following conditions: (1) Any plurality of identical substrate bodies can be spliced into a seamless integral flat plate in a seamless way, or the integral flat plate can be formed by dividing a plurality of identical substrate bodies without gaps and residual materials; (2) At least three of the five interior corners of the pentagon of the substrate body profile are obtuse angles. The design of the appearance enables the bearing substrate to be mainly an obtuse outer contour, reduces corner stress, and further enables the bearing substrate to be cut from the raw material plate without gaps through a preferable angle, reduces the bus length of cutting, and achieves the purposes of improving yield and reducing cost.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a bearing substrate and a manufacturing method thereof.
Background
With the rapid development of the electronic industry, electronic products are increasingly focusing on versatility and high performance. There are many techniques currently used in the field of chip packaging, such as flip chip packaging modules, for example CSP, DCA, MCM, and integration is achieved by stacking the chips into a 3D IC chip stack module.
The carrier substrate in the prior art is generally rectangular with four corners being right angles, and mechanical stress can accumulate at the corners during the subsequent manufacturing process of soldering, wire laying, via hole manufacturing and packaging, and the package fails when the package is impacted by mechanical external force, temperature change or dropping. And the build-up of corner stresses (Die Corner Stress) is difficult to measure and control before destructive testing is performed, resulting in a greatly reduced reliability of the finished closure.
Some approaches to reducing corner stress by changing the shape of the carrier substrate have been developed, such as chinese patent CN107154386B, the contents of which are incorporated by reference in their entirety. Fig. 1 of the specification is a generalized diagram of the technical scheme of the patent, and adopts the shape of the outline of the substrate with water drop-shaped protrusions at four corners, so that in terms of the line degree of the outline, the shape is not deformed at right angles of 90 degrees as in the prior art, but only has arc transition or obtuse angle transition (see the figure of the patent), and corner stress is reduced. However, such a solution presents certain problems. Referring first to fig. 1, when a blank is cut from a carrier substrate stock during manufacture, the stock to be discarded by rough machining is located between the dashed lines; the raw materials to be discarded in the finish machining are arranged between the dotted line and the solid line, and the utilization rate of the raw materials is low overall; on the other hand, the arc is difficult to excessively cut, and the production cost is high.
Disclosure of Invention
First technical problem
1. Aiming at the problem of corner stress aggregation of a rectangular substrate, a bearing substrate for reducing corner stress is designed;
2. aiming at the problem of low utilization rate of raw materials in the existing scheme for reducing corner stress, a technical scheme for fully utilizing high-precision silicon raw materials is provided.
(II) technical scheme
In order to solve the technical problems, the invention provides the following technical scheme:
a carrier substrate for semiconductor package comprises a substrate body, wherein the shape of the substrate body is pentagon with side length and inner angle not equal, and the inner angle of the substrate body satisfies:
(1) Any plurality of identical substrate bodies can be spliced into a seamless integral flat plate in a seamless way, or the integral flat plate can be formed by dividing a plurality of identical substrate bodies without gaps and residual materials;
(2) At least three of the five interior corners of the pentagon of the substrate body profile are obtuse angles.
As a preferred embodiment of the carrier substrate according to the present invention, wherein: four of the five internal corners of the pentagon of the outline of the substrate body are obtuse angles.
As a preferred embodiment of the carrier substrate according to the present invention, wherein: and (2) a plurality of groups of constraint conditions of the pentagon are met, and any one of the constraint conditions is met, so that the pentagon meets the requirement in the (1).
As a preferred embodiment of the carrier substrate according to the present invention, wherein: at least one electrical device is packaged on the substrate body, and the interior angle of the substrate body is selected so that the area, outside the projection of the outline of the electrical device, on the substrate body is minimum.
As a preferred embodiment of the carrier substrate according to the present invention, wherein: and (5) carrying out fillet treatment on the acute angle of the substrate body.
The invention also discloses a manufacturing method of the bearing substrate, and the bearing substrate is formed by cutting at one time according to the shape of the substrate body.
(III) beneficial effects
The invention provides a bearing substrate and a manufacturing method thereof, which are used for semiconductor packaging, and the bearing substrate comprises a substrate body, wherein the shape of the substrate body is pentagonal with side length and inner angle not being equal, and the inner angle of the substrate body meets the following conditions: (1) Any plurality of identical substrate bodies can be spliced into a seamless integral flat plate in a seamless way, or the integral flat plate can be formed by dividing a plurality of identical substrate bodies without gaps and residual materials; (2) At least three of the five interior corners of the pentagon of the substrate body profile are obtuse angles. The design of the appearance enables the bearing substrate to be mainly an obtuse outer contour, reduces corner stress, and further enables the bearing substrate to be cut from the raw material plate without gaps through a preferable angle, reduces the bus length of cutting, and achieves the purposes of improving yield and reducing cost.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a technical solution manufacturing in the prior art CN 107154386B;
FIG. 2 is a schematic view of a carrier substrate dicing scheme according to the present invention corresponding to FIG. 1;
FIG. 3 is a schematic diagram illustrating the decomposition of a carrier substrate according to the present invention;
fig. 4 is a schematic diagram of a carrier substrate geometry.
Reference numerals: 1-substrate body of the invention
2-electric device
W-width
20-substrate body in the prior art
21-substrate body protrusion structure in the prior art
20' -substrate body in the prior art
3-substrate body silicon wafer full-page panel block in the prior art
30-substrate body pre-cut in the prior art
30' -substrate body dicing streets in the prior art
30 "-prior art substrate body pre-scribe line material.
Description of the embodiments
The following description will be made clearly and fully with reference to the technical solutions in the embodiments, and it is apparent that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The technical schemes described in the embodiments of the present invention may be arbitrarily combined without any collision. The invention is further illustrated below with reference to examples.
As shown in fig. 2-4, a carrier substrate for semiconductor packaging includes a substrate body 1, wherein the shape of the substrate body 1 is a pentagon with side length and inner angle not equal, and the inner angle of the substrate body 1 satisfies:
(1) Any plurality of identical substrate bodies 1 can be spliced into a seamless integral flat plate without gaps, or can be formed by dividing a plurality of identical substrate bodies 1 by a integral flat plate without gaps and with surplus materials;
(2) At least three of the five interior corners of the pentagon outline of the substrate body 1 are obtuse angles.
Referring to the comparison between fig. 1 and fig. 2, in the present invention, a gapless cutting mode is designed for generating excessive waterproof remainder on the basis of CN 107154386B. In the manufacture of semiconductor substrates, high-precision silicon materials as raw materials are very expensive, and the loss should be minimized. The cutting solution according to the invention makes it possible to use silicon material to the greatest extent and, because of the gap-free cutting solution, it is possible to actually cut one less contour during cutting.
Geometrically, such pentagons exist, but to meet general conditions, they are described in the examples below. However, not all pentagons satisfying these conditions are suitable as outline schemes for cutting a substrate. Considering the design goal of reducing corner stresses (Die Corner Stress) that can rapidly build up when there is a steep change in the plate-like outer profile; in addition, the small angle can lead the substrate to have more obvious vibration and mechanical defects when being cut; it is thus defined that the outer contour of the base plate is as obtuse as possible, which may have 3-4 obtuse interior angles depending on the geometry of the pentagon, and of the pentagons that may form a gapless monolithic panel, a pentagon with more interior angles than obtuse angles should be chosen.
On the other hand, considering that the regular hexagons can form an integral body which is arranged without gaps, and the inner angles are obtuse angles, but the regular hexagons are not suitable for use, because the chip to be packaged by the bearing substrate is still mainly rectangular, all the regular hexagons are similar, and space is difficult to fully utilize for packaging the rectangular chip; while there are many available pentagons, the pentagon of the corresponding shape can be selected according to the shape and the number of chips actually laid out.
In one embodiment, four of the five interior corners of the pentagon profile of the substrate body 1 are obtuse angles.
And (2) a plurality of groups of constraint conditions of the pentagon are met, and any one of the constraint conditions is met, so that the pentagon meets the requirement in the (1).
Referring to fig. 4 of the specification, the corner is a pentagon, its vertex is A, B, C, D, E, and the inner corners are angle a, angle B, angle C, angle D, and angle E.
In one embodiment, the condition is: angle B + angle C = 180 ° and angle a + angle D + angle E = 360 °, and wherein angles a, B, D, E are obtuse angles.
Ae=de may be further defined for ease of manufacture. However, the actual angle is determined by the total peripheral outline of the chip to be laid out on the chip, and the technical means that the chip can be further optimized under the limitation of the constraint conditions are as follows:
at least one electrical device 2 (such as three chips in fig. 3) is packaged on the substrate body 1, and the interior angle of the substrate body 1 is selected so that the area of the substrate body 1 outside the projection by the outline of the electrical device 2 is minimized.
In another embodiment, see fig. 4 of the specification, it is a pentagon, whose vertices are A, B, C, D, E, respectively, and whose interior angles are angle a, angle B, angle C, angle D, and angle E, respectively. The conditions are as follows: angle B + angle d=180° and bc=de.
In another embodiment, see fig. 4 of the specification, it is a pentagon, whose vertices are A, B, C, D, E, respectively, and whose interior angles are angle a, angle B, angle C, angle D, and angle E, respectively. The conditions are as follows: angle b+2 angle e=2 angle c+d=360° and ab=bc=cd=de.
In another embodiment, see fig. 4 of the specification, it is a pentagon, whose vertices are A, B, C, D, E, respectively, and whose interior angles are angle a, angle B, angle C, angle D, and angle E, respectively. The conditions are as follows: angle B + angle d=180° and angle b=angle E and ae=cd=de and ab=bc.
In all the shapes satisfying the above conditions, if only one angle is an acute angle, there is still a problem in that the angular stress is excessive. In this case, only one acute angle is rounded, which is acceptable in terms of manufacturing costs.
In a further embodiment, the acute angle of the substrate body 1 is rounded.
The circular arc shape of the cut is costly to manufacture for silicon feedstock (which is generally brittle) and should minimize the outer profile of the curve, thus the outer profile of the split line is designed in CN 107154386B. But in general, because of the combination of pentagonal profiles satisfying the above conditions, only one acute angle thereof requires a rounding process, which is acceptable from the viewpoint of manufacturing costs.
Another embodiment of the present invention also discloses a method for manufacturing a carrier substrate, wherein the carrier substrate is cut and molded at one time according to the shape of the substrate body 1 defined in the above embodiment.
In the prior art (such as the scheme of CN 107154386B), there is a gap between the substrate finished products, so each substrate needs to be cut out to form an outline independently, but the substrates conforming to the shape condition in the invention can be spliced into a gapless pattern, and the substrate body of the finished product can be obtained only by cutting once.
The shape of the bearing substrate body is pentagon with side length and inner angle not being equal, and the inner angle of the substrate body meets the following conditions: (1) Any plurality of identical substrate bodies can be spliced into a seamless integral flat plate in a seamless way, or the integral flat plate can be formed by dividing a plurality of identical substrate bodies without gaps and residual materials; (2) At least three of the five interior corners of the pentagon of the substrate body profile are obtuse angles. The design of the appearance enables the bearing substrate to be mainly an obtuse outer contour, reduces corner stress, and further enables the bearing substrate to be cut from the raw material plate without gaps through a preferable angle, reduces the bus length of cutting, and achieves the purposes of improving yield and reducing cost.
In the description of the present invention, furthermore, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present invention, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.
In the present invention, unless explicitly specified and limited otherwise, the terms "mounted," "connected," "secured," and the like are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally formed; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present invention can be understood by those of ordinary skill in the art according to the specific circumstances.
For purposes of this disclosure, the terms "one embodiment," "some embodiments," "example," "a particular example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction.
While embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives and variations may be made to the above embodiments by one of ordinary skill in the art within the scope of the invention.
Claims (8)
1. A carrier substrate for semiconductor packaging, characterized by: the novel solar cell panel comprises a substrate body, wherein the shape of the substrate body is pentagon with side length and inner angle not being equal, and the inner angle of the substrate body meets the following conditions:
(1) Any plurality of identical substrate bodies can be spliced into a seamless integral flat plate in a seamless way, or the integral flat plate can be formed by dividing a plurality of identical substrate bodies without gaps and residual materials;
(2) At least three of the five interior corners of the pentagon of the substrate body profile are obtuse angles.
2. The carrier substrate of claim 1, wherein: four of the five internal corners of the pentagon of the outline of the substrate body are obtuse angles.
3. The carrier substrate of claim 1, wherein: the vertices of the pentagon of the outline of the substrate body are A, B, C, D, E, the inner angles are angle A, angle B, angle C, angle D and angle E, and the following conditions are satisfied: angle B + angle C = 180 ° and angle a + angle D + angle E = 360 °, and wherein angles a, B, D, E are obtuse angles.
4. The carrier substrate of claim 1, wherein: the vertices of the pentagon of the outline of the substrate body are A, B, C, D, E, the inner angles are angle A, angle B, angle C, angle D and angle E, and the following conditions are satisfied: angle B + angle d=180° and bc=de.
5. The carrier substrate of claim 1, wherein: the vertices of the pentagon of the outline of the substrate body are A, B, C, D, E, the inner angles are angle A, angle B, angle C, angle D and angle E, and the following conditions are satisfied: angle b+2 angle e=2 angle c+d=360° and ab=bc=cd=de.
6. The carrier substrate of claim 1, wherein: the vertices of the pentagon of the outline of the substrate body are A, B, C, D, E, the inner angles are angle A, angle B, angle C, angle D and angle E, and the following conditions are satisfied: angle B + angle d=180° and angle b=angle E and ae=cd=de and ab=bc.
7. The carrier substrate of claim 1, wherein: and (5) carrying out fillet treatment on the acute angle of the substrate body.
8. A method of manufacturing a carrier substrate, characterized in that the carrier substrate according to any one of claims 1-7, wherein the defined shape of the substrate body is cut from a stock plate without gaps to shape all substrate bodies.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310593292.3A CN116314040A (en) | 2023-05-24 | 2023-05-24 | Bearing substrate and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202310593292.3A CN116314040A (en) | 2023-05-24 | 2023-05-24 | Bearing substrate and manufacturing method thereof |
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| CN116314040A true CN116314040A (en) | 2023-06-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202310593292.3A Pending CN116314040A (en) | 2023-05-24 | 2023-05-24 | Bearing substrate and manufacturing method thereof |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5084595A (en) * | 1989-10-18 | 1992-01-28 | Shinko Electric Industries Co., Ltd. | Ceramic base for a semiconductor device |
| CN101093342A (en) * | 2006-06-19 | 2007-12-26 | 精碟科技股份有限公司 | Method for collocating fan shaped pieces on basal plate |
| US20080220220A1 (en) * | 2007-03-06 | 2008-09-11 | Ken Jian Ming Wang | Semiconductor die having increased usable area |
| JP2016111086A (en) * | 2014-12-03 | 2016-06-20 | 株式会社デンソー | Semiconductor device |
| CN107154386A (en) * | 2016-03-04 | 2017-09-12 | 矽品精密工业股份有限公司 | Electronic package and semiconductor substrate |
| CN107275290A (en) * | 2016-04-07 | 2017-10-20 | 三菱电机株式会社 | Semiconductor device |
| CN209030512U (en) * | 2018-08-31 | 2019-06-25 | 奥特斯科技(重庆)有限公司 | Processing system for the load-bearing part of bearing substrate and for handling substrate |
-
2023
- 2023-05-24 CN CN202310593292.3A patent/CN116314040A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5084595A (en) * | 1989-10-18 | 1992-01-28 | Shinko Electric Industries Co., Ltd. | Ceramic base for a semiconductor device |
| CN101093342A (en) * | 2006-06-19 | 2007-12-26 | 精碟科技股份有限公司 | Method for collocating fan shaped pieces on basal plate |
| US20080220220A1 (en) * | 2007-03-06 | 2008-09-11 | Ken Jian Ming Wang | Semiconductor die having increased usable area |
| JP2016111086A (en) * | 2014-12-03 | 2016-06-20 | 株式会社デンソー | Semiconductor device |
| CN107154386A (en) * | 2016-03-04 | 2017-09-12 | 矽品精密工业股份有限公司 | Electronic package and semiconductor substrate |
| CN107275290A (en) * | 2016-04-07 | 2017-10-20 | 三菱电机株式会社 | Semiconductor device |
| CN209030512U (en) * | 2018-08-31 | 2019-06-25 | 奥特斯科技(重庆)有限公司 | Processing system for the load-bearing part of bearing substrate and for handling substrate |
Non-Patent Citations (1)
| Title |
|---|
| TERUHISA SUGIMOTO: "PROPERTIES OF STRONGLY BALANCED TILINGS BY CONVEX POLYGONS", ARXIV:1606.07997 [MATH.MG], pages 1 - 14 * |
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