CN116312703A - Memory controller and flash memory chip - Google Patents

Memory controller and flash memory chip Download PDF

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Publication number
CN116312703A
CN116312703A CN202111563617.0A CN202111563617A CN116312703A CN 116312703 A CN116312703 A CN 116312703A CN 202111563617 A CN202111563617 A CN 202111563617A CN 116312703 A CN116312703 A CN 116312703A
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China
Prior art keywords
hardware accelerator
read
controller
erase
write
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CN202111563617.0A
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Chinese (zh)
Inventor
胡俊刚
卢中舟
宋思宪
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Wuhan Xinxin Semiconductor Manufacturing Co Ltd
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Priority to CN202111563617.0A priority Critical patent/CN116312703A/en
Publication of CN116312703A publication Critical patent/CN116312703A/en
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Read Only Memory (AREA)

Abstract

The invention discloses a memory controller and a flash memory chip, wherein the memory controller comprises an acceleration module and a controller, and the controller is electrically connected with the acceleration module; the acceleration module comprises a read operation hardware accelerator, a write operation hardware accelerator and an erase operation hardware accelerator, wherein the read operation hardware accelerator is electrically connected with the controller, and the read operation hardware accelerator comprises a read operation hardware logic circuit for accelerating the execution of a read operation process; the write operation hardware accelerator is electrically connected with the controller, and comprises a write operation hardware logic circuit for accelerating the execution of a write operation process; the erasure operation hardware accelerator is electrically connected with the controller, and comprises erasure operation hardware logic circuits for accelerating the erasure operation process, and the acceleration module formed by the controller based on the hardware logic circuits can accelerate and execute each instruction in the controller, so that the execution speed/efficiency of various operations is improved.

Description

Memory controller and flash memory chip
Technical Field
The invention relates to the technical field of storage, in particular to a storage controller and a flash memory chip.
Background
The memory controller in the traditional technical scheme can realize the corresponding memory function by implanting the corresponding read-erase algorithm into the control chip, and the operation mode simplifies the basic hardware architecture, but requires relatively complicated or lengthy software programs to realize the corresponding read-erase algorithm, and the instruction forming the read-erase algorithm also requires longer operation time, which seriously reduces the working efficiency of the memory chip.
It should be noted that the above description of the background art is only for the purpose of facilitating a clear and complete understanding of the technical solution of the present invention. Therefore, the technical solutions referred to above are not considered to be known to those skilled in the art, simply because they appear in the background of the invention.
Disclosure of Invention
The invention provides a memory controller and a flash memory chip, which are used for relieving the technical problem of lower working efficiency caused by a read-erase algorithm based on chip construction.
In a first aspect, the present invention provides a storage controller, which includes an acceleration module and a controller, wherein the controller is electrically connected with the acceleration module, and is provided with a main program for operating the acceleration module according to a user instruction; the acceleration module comprises at least one of a read operation hardware accelerator, a write operation hardware accelerator and an erase operation hardware accelerator, wherein the read operation hardware accelerator is electrically connected with the controller, and the read operation hardware accelerator comprises a read operation hardware logic circuit for accelerating the execution of a read operation process; the write operation hardware accelerator is electrically connected with the controller, and comprises a write operation hardware logic circuit for accelerating the execution of a write operation process; the erasing operation hardware accelerator is electrically connected with the controller, and comprises an erasing operation hardware logic circuit for accelerating the erasing operation process.
In some embodiments, the memory controller further includes a high voltage generator, a row-column decoder, a static memory, and a sense amplifier, where the high voltage generator is electrically connected to the read operation hardware accelerator, the write operation hardware accelerator, and the erase operation hardware accelerator, and is configured to generate a corresponding operation voltage; the row-column decoder is electrically connected with the read operation hardware accelerator, the write operation hardware accelerator and the erase operation hardware accelerator and is used for generating corresponding operation addresses; the static memory is electrically connected with the write operation hardware accelerator and is used for storing data to be written; the sense amplifier is electrically connected with the read operation hardware accelerator and is used for reading data in at least one memory cell.
In some of these embodiments, the user instruction comprises a read operation instruction; in response to the read operation instruction, the controller starts a read operation hardware accelerator based on the main program, the read operation hardware accelerator enables the high voltage generator to generate a corresponding read voltage, enables the row-column decoder to generate a corresponding read unit address, and enables the sense amplifier to read data stored in the read unit address.
In some of these embodiments, the read operation instruction includes a read command code and a read address code; in response to the read command code, the read operation hardware accelerator enables the high voltage generator to generate a corresponding read voltage; in response to the read address code, the read operation hardware accelerator enables the row and column decoder to generate a corresponding read cell address; under the supply of the read voltage, the read operation hardware accelerator enables the sense amplifier to read out the data stored in the read cell address.
In some embodiments, the memory controller further includes a serial interface and a data conversion module, the data conversion module is electrically connected with the output end of the sense amplifier and the serial interface, the read operation hardware accelerator enables the data conversion module to convert parallel data output by the sense amplifier into corresponding serial data, and the serial data is output to the outside through the serial interface.
In some of these embodiments, the user instruction comprises a write operation instruction; in response to the write operation instruction, the controller starts a write operation hardware accelerator based on the main program, the write operation hardware accelerator enables the static memory to store data to be written, enables the high voltage generator to generate corresponding write voltages, enables the row and column decoder to generate corresponding write unit addresses and executes write operation time sequences so as to transfer the data to be written in the static memory to corresponding storage units.
In some of these embodiments, the write operation instruction includes a write command code, a write address code, and data to be written; in response to the write command code, the write operation hardware accelerator enables the static memory to store data to be written and enables the high voltage generator to generate a corresponding write voltage; in response to the write address code, the write operation hardware accelerator enables the row and column decoder to generate a corresponding write unit address.
In some of these embodiments, the user instruction comprises a wipe operation instruction; in response to the erase operation command, the erase operation hardware accelerator enables the high voltage generator to generate a corresponding erase voltage, enables the row and column decoder to generate a corresponding erase cell address, and performs an erase operation timing to erase the memory contents corresponding to the erase cell address.
In some of these embodiments, the erase operation instructions include an erase command code and an erase address code; in response to the erase command code, the erase operation hardware accelerator enables the high voltage generator to generate a corresponding erase voltage; in response to the erase address code, the erase operation hardware accelerator enables the row and column decoder to generate a corresponding erase cell address.
In some of these embodiments, the acceleration module further includes an over-erasure correction hardware accelerator including over-erasure correction hardware logic for accelerating the performance of the over-erasure correction operation.
In some of these embodiments, the controller activates and monitors the acceleration module in response to user instructions.
In some of these embodiments, the controller communicates with the acceleration module via a bus under control of a clock signal; the communication from the controller to the acceleration module is realized through a request instruction and an acceleration instruction, wherein the request instruction is used for informing the acceleration module of the type of operation executed, and the acceleration instruction is used for determining a communication object; the communication from the acceleration module to the controller is realized through a response instruction and an acceleration instruction, wherein the response instruction is used for informing the controller of the operation state of the acceleration module, and the acceleration instruction is used for definitely communicating with the controller.
In a second aspect, the present invention provides a flash memory chip, which includes the memory controller and at least one memory unit in at least one embodiment, where the at least one memory unit is electrically connected to the acceleration module.
According to the memory controller and the flash memory chip provided by the invention, the main program is implanted into the controller, and the acceleration module formed based on the hardware logic circuit can accelerate and execute each instruction in the controller, so that the execution speed/efficiency of various operations is improved.
Meanwhile, based on the architecture of the software program and the hardware accelerator, the system has both the flexibility of the algorithm and the stability of the hardware; due to the reduced content of controller execution, custom instruction sets can also be developed based on this architecture that can greatly reduce the types and lengths of various commands.
Drawings
The technical solution and other advantageous effects of the present invention will be made apparent by the following detailed description of the specific embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of a flash memory chip according to an embodiment of the present invention.
FIG. 2 is a flow chart illustrating the operation of the flash memory chip shown in FIG. 1.
FIG. 3 is a schematic diagram of the intercommunication between the controller and the acceleration module shown in FIG. 1.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
In view of the above-mentioned technical problem of low working efficiency caused by the read-erase algorithm based on the chip construction, the present embodiment provides a flash memory chip, as shown in fig. 1 to 3, which includes a memory controller 100 and at least one memory unit 200, wherein the at least one memory unit 200 is electrically connected to the memory controller 100 to implement the read-erase operation on the at least one memory unit 200. The flash memory chip may be, but not limited to, a Nor flash chip, or may be any other memory chip suitable for the present invention.
As shown in fig. 1 and 2, in one embodiment, the present embodiment provides a memory controller 100, where the memory controller 100 includes a high voltage generator 120, a rank decoder 130, a static memory 140, a sense amplifier 150, a controller 110, and an acceleration module 191, and the high voltage generator 120 is used to generate a corresponding operating voltage; the row-column decoder 130 is configured to generate a corresponding operation address; the static memory 140 is used for storing data to be written; sense amplifier 150 is used to read data from at least one memory cell 200; the controller 110 is provided with a main program S100 for operating the acceleration module 191 according to a user instruction; the acceleration module 191 is electrically connected to at least one of the high voltage generator 120, the rank decoder 130, the static memory 140, the sense amplifier 150 and the controller 110, and is configured to invoke at least one of the high voltage generator 120, the rank decoder 130, the static memory 140 and the sense amplifier 150 according to a user instruction to accelerate the at least one memory cell 200.
By acceleration execution is meant that the accelerator of the present solution is implemented by hardware logic circuits, with a faster speed than software implementations.
Each accelerator can only consist of a hardware logic circuit so as to further improve the running speed and stability.
It can be understood that, in the memory controller 100 and the flash memory chip provided in this embodiment, the acceleration module 191 may call the corresponding main program S100 according to the user instruction to enable at least one of the high voltage generator 120, the row-column decoder 130, the static memory 140 and the sense amplifier 150 to perform the corresponding operation on the memory unit 200, so as to implement the read-write operation, for various hardware subroutines, the program execution speed is increased, the stability of the program is also enhanced, especially the hardware program is difficult to be modified, so that the safety of the memory is increased, the acceleration module 191 may have a higher execution speed, and the execution efficiency of the main program S100 based on the chip construction is improved, thereby improving the working efficiency of the memory controller 100 or the flash memory chip; meanwhile, the acceleration module 191 replaces part of the work of the controller 110, so that the operation load of the controller 110 is reduced, the operation efficiency of the main program S100 can be further improved, and the working efficiency of the memory controller 100 or the flash memory chip can be improved.
The acceleration module 191 may include at least one of the read operation hardware accelerator 160, the write operation hardware accelerator 170, the erase operation hardware accelerator 180, and the over-erase correction hardware accelerator 190, and it is understood that the acceleration module 191 may have a higher execution speed, and compared with the controller 110, the acceleration module 191 may be capable of improving the execution efficiency of the main program S100 based on chip construction for the same sub-program, thereby improving the working efficiency of the memory controller 100 or the flash memory chip.
The memory controller 100 may further include a serial interface 101 and a data conversion module, where the data conversion module is electrically connected to the output end of the sense amplifier 150, the serial interface 101, and the static memory 140. The data conversion module is used for mutual conversion between serial data and parallel data, and under the enabling of the controller 110, the data conversion module can convert the serial data input by the serial interface 101 into corresponding parallel data, and then store the parallel data into the static memory 140; the data conversion module may also convert the parallel data output from the sense amplifier 150 into corresponding serial data, and then the serial interface 101 transmits the serial data to the outside. Based on the design, the memory controller in the scheme can be compatible with the existing serial peripheral interface, and can process data in a parallel mode, so that the whole process is more efficient, and no change is needed on the peripheral.
The serial interface 101 may be a serial peripheral interface (SPI, serial Peripheral Interface), which is a high-speed, full duplex, synchronous communication bus, and occupies only four wires on the pins of the chip, so that the pins of the chip can be saved; the serial interface 101 may also be an IIC (Inter-Integrated Circuit Bus, integrated circuit bus) interface. The serial interface 101 may use a custom communication protocol, or may use a standard communication protocol, which is not particularly limited herein.
The data conversion module may be, but not limited to, disposed in the controller 110, so that the occupied area of the memory controller may be reduced. The data conversion module may also be disposed in the acceleration module 191, so that the serial-parallel conversion speed or efficiency may be improved.
The user instructions may include, among other things, read operation instructions, write operation instructions, and erase operation instructions. The read operation instruction may include a read command code and a read address code. The write operation instruction includes a write command code, a write address code, and data to be written. The erase operation instruction includes an erase command code and an erase address code.
The read command code, the write command code, and the erase command code may each be, but are not limited to, 8bits, the read address code, the write address code, and the erase address code may each be, but are not limited to, 32bits, and the data to be written may be, but are not limited to, one or more bytes.
In one embodiment, the read operation hardware accelerator 160 is electrically connected to the high voltage generator 120, the column decoder 130, the sense amplifier 150, and the controller 110.
Specifically, in response to the read operation instruction, the controller 110 starts the read operation hardware accelerator 160 based on the main program S100, and the read operation hardware accelerator 160 enables the high voltage generator 120 to generate a corresponding read voltage, enables the row and column decoder 130 to generate a corresponding read unit address, and enables the sense amplifier 150 to read out data stored in the read unit address.
In one embodiment, the read operation instruction includes a read command code and a read address code; in response to the read command code, the read operation hardware accelerator 160 enables the high voltage generator 120 to generate a corresponding read voltage; in response to the read address code, the read operations hardware accelerator 160 enables the row decoder 130 to generate a corresponding read cell address; under the supply of the read voltage, the read operation hardware accelerator 160 enables the sense amplifier 150 to read out the data stored in the read cell address.
In one embodiment, the write operation hardware accelerator 170 is electrically connected to the high voltage generator 120, the column decoder 130, the static memory 140, and the controller 110.
Specifically, in response to the write operation instruction, the controller 110 starts the write operation hardware accelerator 170 based on the main program S100, the write operation hardware accelerator 170 enables the static memory 140 to store data to be written, enables the high voltage generator 120 to generate a corresponding write voltage, enables the row-column decoder 130 to generate a corresponding write unit address, and enables the write status register to perform a write operation timing to transfer the data to be written in the static memory 140 to the corresponding memory unit 200.
Further, in response to the write command code, the write operation hardware accelerator 170 enables the static memory 140 to store data to be written and enables the high voltage generator 120 to generate a corresponding write voltage; in response to the write address code, the write operation hardware accelerator 170 enables the row decoder 130 to generate a corresponding write unit address.
In one embodiment, the erase operation hardware accelerator 180 is electrically connected to the high voltage generator 120, the column decoder 130, and the controller 110.
Specifically, in response to the erase operation instruction, the erase operation hardware accelerator 180 enables the high voltage generator 120 to generate a corresponding erase voltage, enables the row and column decoder 130 to generate a corresponding erase cell address, and performs an erase operation timing to erase the memory contents corresponding to the erase cell address.
Further, in response to the erase command code, the erase operation hardware accelerator 180 enables the high voltage generator 120 to generate a corresponding erase voltage; in response to the erase address code, erase operation hardware accelerator 180 enables row decoder 130 to generate a corresponding erase unit address.
In one embodiment, the over-erase correction hardware accelerator 190 is electrically connected to the high voltage generator 120, the column decoder 130, and the controller 110.
Specifically, in response to the execution of the erase operation timing, the over-erase correction hardware accelerator 190 executes an over-erase correction operation for the corresponding memory cell 200.
In one embodiment, the controller 110 may activate and monitor the acceleration module 191 in response to user instructions so that various operating states of the acceleration module 191 may be available in time.
The controller 110 may be a microcontroller or a micro control chip (MCU), or may be a central processing chip, or any one of a digital processing chip, an off-the-shelf programmable logic array, an off-the-shelf programmable logic device, or the like.
Because the scheme adopts the architecture of software (the controller 110 and software programs thereof) and hardware (various hardware accelerators), the programs in the controller 110 can be greatly simplified, and therefore, the controller 110 can also comprise a custom instruction set and a compiler. It is understood that the main program S100 described above can enable the acceleration module 191 based on the custom instruction set. Meanwhile, the compiler may convert various types of instructions into corresponding machine codes, for example, may convert assembly instructions into machine codes that the controller 110 may recognize, to execute the above-described main program S100.
As shown in fig. 2, which is a flow chart illustrating the operation of the flash memory chip or the memory controller 100, the main program S100 may enable the acceleration module in response to a user instruction.
As shown in fig. 1 to 3, the controller 110 may be connected to the acceleration module 191 by using a bus to simplify the electrical connection relationship between the two, so, based on the bus connection manner, fig. 3 shows a communication protocol between the two, which is specifically as follows:
in this communication protocol, the clock of the bus takes a clock signal CLK and samples on the rising edge of the clock signal CLK.
The controller 110 sends a Request command Request [ 1:0 ] and an acceleration command Acc [ 1:0 ] to one of the corresponding read operation hardware accelerator 160, write operation hardware accelerator 170, erase operation hardware accelerator 180 and over-erase correction hardware accelerator 190 according to the received user command, wherein the Request command Request [ 1:0 ] is 00, which indicates that the Request command is temporarily undefined and does not act on the read operation hardware accelerator 160, write operation hardware accelerator 170, erase operation hardware accelerator 180 and over-erase correction hardware accelerator 190; when the Request command Request [ 1:0 ] is 01, it indicates a start command issued by the controller 110 to the read operation hardware accelerator 160, the write operation hardware accelerator 170, the erase operation hardware accelerator 180, and the over-erase correction hardware accelerator 190; when the Request command Request [ 1:0 ] is 10, it indicates a query command issued by the controller 110 to the read operation hardware accelerator 160, the write operation hardware accelerator 170, the erase operation hardware accelerator 180 and the over-erase correction hardware accelerator 190; when the Request command Request [ 1:0 ] is 11, it indicates a stop command issued by the controller 110 to the read operation hardware accelerator 160, the write operation hardware accelerator 170, the erase operation hardware accelerator 180, and the over-erase correction hardware accelerator 190. When the acceleration command Acc [ 1:0 ] is 00, it indicates that the current communication object of the controller 110 is the read operation hardware accelerator 160; when the acceleration command Acc [ 1:0 ] is 01, it indicates that the current communication object of the controller 110 is a write operation hardware accelerator 170; when the acceleration command Acc [ 1:0 ] is 10, it indicates that the current communication object of the controller 110 is the erase operation hardware accelerator 180; when the acceleration command Acc [ 1:0 ] is 11, it indicates that the current communication object of the controller 110 is the over-erasure correction hardware accelerator 190.
The content of each accelerator feedback state for communication to the controller 110 includes a Response command Response [ 1:0 ] and the acceleration command Acc [ 1:0 ] described above, wherein the Response command Response [ 1:0 ] is 00, which indicates that the vehicle is in preparation; the Response command Response [ 1:0 ] of each accelerator feedback state to the controller 110 is 01, indicating that it is executing; the Response command Response [ 1:0 ] of each accelerator feedback state to the controller 110 is 10, indicating that execution is complete; the Response command Response [ 1:0 ] of each accelerator feedback state to the controller 110 is 11, indicating an exception.
For example, after receiving a read operation instruction sent by an external device, the controller 110 sends a Request instruction Request [ 1:0 ] to the bus at a rising edge of a clock, that is, a Requ No may be 01; an acceleration command Acc [ 1:0 ] is issued to the bus at a clock rising edge, i.e., acc No may be 00.
At this point, the read operation hardware accelerator 160 enters a startup mode.
Then, the read operation hardware accelerator 160 feeds back the operation state through the Response command Response [ 1:0 ], for example, the Response command Response [ 1:0 ] is 00, which indicates that the read operation hardware accelerator 160 is in preparation; a Response command Response [ 1:0 ] of 01 indicates that the read operation hardware accelerator 160 is in execution; a Response command Response [ 1:0 ] of 10 indicates that the read operation hardware accelerator 160 execution is complete; the Response command Response [ 1:0 ] is 11, indicating that the read operation hardware accelerator 160 is abnormal. The read operation hardware accelerator 160 then sends an acceleration command Acc [ 1:0 ] to the controller 110, i.e., acc No is 00, indicating that the operational state feedback is being performed at this time as the read operation hardware accelerator 160.
Thereafter, the controller 110 monitors the real-time status of the read operation hardware accelerator 160 by sending a query command of Requ No. 10.
It will be appreciated that other communication conditions between the accelerators and the controller 110 may be analogized in order and will not be described in detail herein.
As described above, the scheme adopts the combination of the software program (the main program S100) and the hardware accelerator, so that the execution pressure of the software program is greatly reduced, and a new instruction set is designed based on the architecture, and is greatly simplified compared with the original instruction, and various complex operations of the memory can be completed only through short instruction communication.
Meanwhile, it should be noted that the architecture of the software program and the hardware accelerator also has flexibility, namely, a user can modify the code of the software part so as to realize a part of customization function, and meanwhile, the hardware accelerator is more stable, more efficient and safer.
In the foregoing embodiments, descriptions of the various embodiments have been provided with emphasis, and for those portions of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.
The memory controller and the flash memory chip provided by the embodiments of the present invention are described in detail, and specific examples are applied to illustrate the principles and the embodiments of the present invention, and the description of the above embodiments is only used to help understand the technical solution and the core idea of the present invention; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims (13)

1. A memory controller, comprising:
an acceleration module; and
the controller is electrically connected with the acceleration module and is provided with a main program for operating the acceleration module according to a user instruction;
wherein the acceleration module comprises at least one of a read operation hardware accelerator, a write operation hardware accelerator, and an erase operation hardware accelerator:
the read operation hardware accelerator is electrically connected with the controller, and comprises a read operation hardware logic circuit for accelerating the execution of a read operation process;
the write operation hardware accelerator is electrically connected with the controller, and comprises a write operation hardware logic circuit for accelerating the execution of a write operation process;
the erasing operation hardware accelerator is electrically connected with the controller, and comprises an erasing operation hardware logic circuit for accelerating the execution of the erasing operation process.
2. The memory controller of claim 1, wherein the memory controller further comprises:
the high-voltage generator is electrically connected with the read operation hardware accelerator, the write operation hardware accelerator and the erase operation hardware accelerator and is used for generating corresponding operation voltages;
the row-column decoder is electrically connected with the read operation hardware accelerator, the write operation hardware accelerator and the erase operation hardware accelerator and is used for generating corresponding operation addresses;
the static memory is electrically connected with the write operation hardware accelerator and used for storing data to be written;
and the sense amplifier is electrically connected with the read operation hardware accelerator and is used for reading out data in at least one storage unit.
3. The memory controller of claim 2, wherein the user instruction comprises a read operation instruction;
in response to the read operation instruction, the controller starts the read operation hardware accelerator based on the main program, and the read operation hardware accelerator enables the high voltage generator to generate a corresponding read voltage, enables the row-column decoder to generate a corresponding read unit address, and enables the sense amplifier to read out data stored in the read unit address.
4. The memory controller of claim 3, wherein the read operation instruction comprises a read command code and a read address code;
in response to the read command code, the read operation hardware accelerator enables the high voltage generator to generate a corresponding read voltage;
in response to the read address code, the read operation hardware accelerator enables the rank decoder to generate a corresponding read unit address;
the read operation hardware accelerator enables the sense amplifier to read data stored in the read cell address under the supply of the read voltage.
5. The memory controller according to claim 3 or 4, further comprising a serial interface and a data conversion module, wherein the data conversion module is electrically connected to the output end of the sense amplifier and the serial interface, and the read operation hardware accelerator enables the data conversion module to convert parallel data output by the sense amplifier into corresponding serial data and output the serial data to the outside through the serial interface.
6. The memory controller of claim 2, wherein the user instruction comprises a write operation instruction;
in response to the write operation instruction, the controller starts the write operation hardware accelerator based on the main program, and the write operation hardware accelerator enables the static memory to store data to be written, enables the high voltage generator to generate corresponding write voltages, enables the row-column decoder to generate corresponding write unit addresses and executes write operation time sequences so as to transfer the data to be written in the static memory to corresponding storage units.
7. The memory controller of claim 6, wherein the write operation instruction includes a write command code, a write address code, and the data to be written;
in response to the write command code, the write operation hardware accelerator enables the static memory to store data to be written and enables the high voltage generator to generate a corresponding write voltage;
in response to the write address code, the write operation hardware accelerator enables the rank decoder to generate a corresponding write unit address.
8. The memory controller of claim 2, wherein the user instruction comprises a wipe operation instruction;
in response to the erase operation instruction, the erase operation hardware accelerator enables the high voltage generator to generate a corresponding erase voltage, enables the row-column decoder to generate a corresponding erase cell address, and performs an erase operation timing to erase the memory contents corresponding to the erase cell address.
9. The memory controller of claim 8, wherein the erase operation instruction includes an erase command code and an erase address code;
in response to the erase command code, the erase operation hardware accelerator enables the high voltage generator to generate a corresponding erase voltage;
in response to the erase address code, the erase operation hardware accelerator enables the row and column decoder to generate a corresponding erase unit address.
10. The memory controller of any one of claims 1 to 9, wherein the acceleration module further comprises an over-erasure correction hardware accelerator comprising over-erasure correction hardware logic to accelerate performance of over-erasure correction operations.
11. The storage controller of any one of claims 1 to 9, wherein the controller activates and monitors the acceleration module in response to the user instruction.
12. The memory controller according to any one of claims 1 to 9, wherein the controller communicates with the acceleration module via a bus under control of a clock signal;
the communication from the controller to the acceleration module is realized through a request instruction and an acceleration instruction, wherein the request instruction is used for informing the acceleration module of the type of operation executed, and the acceleration instruction is used for determining a communication object;
the communication from the acceleration module to the controller is realized through a response instruction and an acceleration instruction, the response instruction is used for informing the controller of the operation state of the acceleration module, and the acceleration instruction is used for definitely communicating with the controller.
13. A flash memory chip, comprising:
the memory controller of any one of claims 1 to 12; and
the at least one storage unit is electrically connected with the acceleration module.
CN202111563617.0A 2021-12-20 2021-12-20 Memory controller and flash memory chip Pending CN116312703A (en)

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