CN116301564A

CN116301564A - Memory controller and flash memory chip

Info

Publication number: CN116301564A
Application number: CN202111565060.4A
Authority: CN
Inventors: 胡俊刚; 卢中舟; 宋思宪
Original assignee: Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Current assignee: Wuhan Xinxin Semiconductor Manufacturing Co Ltd
Priority date: 2021-12-20
Filing date: 2021-12-20
Publication date: 2023-06-23

Abstract

The invention discloses a memory controller and a flash memory chip, wherein the memory controller comprises a controller, a control register group and an execution circuit, a main program, a writing algorithm subprogram, an erasing algorithm subprogram and a reading algorithm subprogram which are arranged in the controller based on an instruction set are triggered through user instructions, corresponding execution data can be generated, then the control register group can generate corresponding enabling data according to the execution data, and then the execution circuit can control the reading and erasing operation of a memory unit according to the enabling data; meanwhile, when the capacity is upgraded, namely the number of the storage units is increased, only the electrical connection relation between the execution circuit and the newly-added storage units is increased, and the capacity can be expanded by adjusting corresponding subroutines, so that the method is more convenient compared with the large-scale change of the whole special circuit.

Description

Memory controller and flash memory chip

Technical Field

The invention relates to the technical field of storage, in particular to a storage controller and a flash memory chip.

Background

In the conventional technical scheme, the controller of the memory chip generally realizes the read, write and erase operations through a special circuit, but the algorithm realized based on the special circuit is fixed, and if the algorithm needs to be changed, the corresponding special circuit needs to be adjusted, so that the controller is inconvenient to upgrade the read and erase algorithm and is also inconvenient to upgrade the memory capacity.

It should be noted that the above description of the background art is only for the purpose of facilitating a clear and complete understanding of the technical solution of the present invention. Therefore, the technical solutions referred to above are not considered to be known to those skilled in the art, simply because they appear in the background of the invention.

Disclosure of Invention

The invention provides a memory controller and a flash memory chip, which are used for relieving the technical problem that the memory controller formed by adopting a special circuit is inconvenient to upgrade an algorithm and upgrade capacity.

In a first aspect, the present invention provides a memory controller comprising a controller, a control register set, and an execution circuit, the controller being configured to execute a main program, a write algorithm subroutine, an erase algorithm subroutine, and a read algorithm subroutine set based on an instruction set in response to a user instruction, to generate corresponding execution data; the control register set is electrically connected with the controller and used for generating corresponding enabling data according to the execution data; the execution circuit is electrically connected with the control register set and is used for controlling the read-write operation of the memory unit according to the enabling data.

In some embodiments, the execution circuit includes a high voltage generator, a row-column decoder, a static memory, and a sense amplifier, where the high voltage generator is electrically connected to the control register set and is used to generate a corresponding operation voltage; the row-column decoder is electrically connected with the control register set and is used for generating a corresponding operation address; the static memory is electrically connected with the controller and the control register set and is used for storing data to be written; the sense amplifier is electrically connected with the control register set and used for reading out data in the memory cell.

In some embodiments, the control register set includes a read control register, a write control register, and a erase control register, where the read control register is electrically connected to the high voltage generator, the row-column decoder, and the sense amplifier, and is configured to enable the high voltage generator, the row-column decoder, and the sense amplifier to perform a read operation of the memory cell; the write control register is electrically connected with the high voltage generator, the row-column decoder and the static memory and is used for enabling the high voltage generator, the row-column decoder and the static memory to execute write operation of the memory unit; the erasing control register is electrically connected with the high voltage generator and the row-column decoder and is used for enabling the high voltage generator and the row-column decoder to execute the erasing operation of the memory cell.

In some embodiments, the control register set includes an over-erase correction control register, the over-erase correction control register being electrically connected to the controller, the over-erase correction control register being configured to control an over-erase correction operation of the at least one memory cell.

In some of these embodiments, the instruction set includes branch class instructions and bit operation class instructions, each branch class instruction including a 6 bit opcode and an 8 bit instruction address; each bit operation class instruction includes a 6-bit opcode and 8-bit register bit select data.

In some of these embodiments, the 6-bit opcode includes a 3-bit main opcode and a 3-bit sub opcode.

In some of these embodiments, the user instruction comprises a read operation instruction; in response to the read operation instruction, the controller enables the high voltage generator to generate a corresponding read voltage through the read control register, enables the row and column decoder to generate a corresponding read cell address, and enables the sense amplifier to read out data stored in the read cell address based on the read algorithm subroutine.

In some of these embodiments, the read operation instruction includes a read command code and a read address code; in response to the read command code, the controller enables the high voltage generator to generate a corresponding read voltage through the read control register based on the read algorithm subroutine; in response to the read address code, the controller enables the row and column decoder to generate a corresponding read cell address through the read control register based on the read algorithm subroutine; under the supply of the read voltage, the controller enables the sense amplifier to read out the data stored in the read cell address through the read control register based on the read algorithm subroutine.

In some embodiments, the memory controller further includes a serial interface and a data conversion module, the data conversion module is electrically connected with the output end of the sense amplifier and the serial interface, and the controller enables the data conversion module to convert the parallel data output by the sense amplifier into corresponding serial data and output the serial data to the outside through the serial interface.

In some of these embodiments, the user instruction comprises a write operation instruction; in response to the write operation instruction, the controller enables the static memory to store data to be written through the write control register based on the write algorithm subroutine, enables the high voltage generator to generate corresponding write voltages, and enables the row-column decoder to generate corresponding write unit addresses so as to transfer the data to be written in the static memory to corresponding storage units.

In some of these embodiments, the write operation instruction includes a write command code, a write address code, and data to be written; in response to the write command code, the controller enables the static memory to store data to be written and enables the high voltage generator to generate a corresponding write voltage through the write control register based on the write algorithm subroutine; in response to the write address code, the controller enables the row and column decoder to generate a corresponding write cell address via the write control register based on the write algorithm subroutine.

In some of these embodiments, the user instruction comprises a wipe operation instruction; in response to the erase operation instruction, the controller enables the high voltage generator to generate a corresponding erase voltage through the erase control register based on the erase algorithm subroutine, and enables the row and column decoder to generate a corresponding erase cell address to erase the memory cell corresponding to the erase cell address.

In some of these embodiments, the erase operation instructions include an erase command code and an erase address code; in response to the erase command code, the controller enables the high voltage generator to generate a corresponding erase voltage through the erase control register based on the erase algorithm subroutine; in response to the erase address code, the controller enables the row and column decoder to generate a corresponding erase cell address through the erase control register based on an erase algorithm subroutine.

In some of these embodiments, the erase algorithm subroutine further includes an over-erase correction subroutine, and the controller performs the over-erase correction subroutine on erased memory cells through the over-erase correction control register based on the erase algorithm subroutine in response to the erase operation instruction.

In a second aspect, the present invention provides a flash memory chip, which includes the memory controller and at least one memory unit in at least one embodiment, where the at least one memory unit is electrically connected to the execution circuit.

According to the memory controller and the flash memory chip provided by the invention, the main program, the writing algorithm subprogram, the erasing algorithm subprogram and the reading algorithm subprogram which are set in the controller based on the instruction set are triggered through the user instruction, so that corresponding execution data can be generated, then the control register set can generate corresponding enabling data according to the execution data, and then the execution circuit can control the reading and erasing operation of the memory unit according to the enabling data; meanwhile, when the capacity is upgraded, namely the number of the storage units is increased, only the electric connection relation between the execution circuit and the newly-increased storage units is increased, and the capacity can be expanded by adjusting corresponding subroutines.

Drawings

The technical solution and other advantageous effects of the present invention will be made apparent by the following detailed description of the specific embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 is a schematic structural diagram of a flash memory chip according to an embodiment of the present invention.

FIG. 2 is a schematic diagram of the read control register of FIG. 1.

FIG. 3 is a schematic diagram of the write control register of FIG. 1.

FIG. 4 is a schematic diagram of the erase control register of FIG. 1.

FIG. 5 is a schematic diagram of the over-erase correction control register of FIG. 1.

FIG. 6 is a flow chart illustrating the operation of the flash memory chip shown in FIG. 1.

Fig. 7 is a flow chart of the read algorithm subroutine shown in fig. 6.

Fig. 8 is a flow chart of the write algorithm subroutine shown in fig. 6.

Fig. 9 is a flow chart of the wiping algorithm subroutine shown in fig. 6.

FIG. 10 is a flow chart of the over-erase correction subroutine shown in FIG. 9.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.

In view of the above-mentioned technical problems that the memory controller formed by the dedicated circuit is inconvenient for upgrading the algorithm and the upgrade capacity, the present embodiment provides a flash memory chip, as shown in fig. 1 to 10, which includes a memory controller 100 and at least one serial interface 101, wherein the at least one serial interface 101 is electrically connected to the memory controller 100. The flash memory chip may be, but not limited to, a Nor flash chip, or may be any other memory chip suitable for the present invention.

As shown in fig. 1 and 6, in one embodiment, the present embodiment provides a memory controller 100, where the memory controller 100 includes a controller 110, a control register set 191, and an execution circuit 192, and the controller 110 is configured to execute a main program set based on an instruction set, a write algorithm subroutine S20, an erase algorithm subroutine S30, and a read algorithm subroutine S10 in response to a user instruction to generate corresponding execution data; the control register set 191 is electrically connected to the controller 110, and is configured to generate corresponding enabling data according to the execution data; the execution circuit 192 is electrically connected to the control register set 191, and is used for controlling the read/write operation of the memory cell according to the enable data.

The execution data may be logic data or control timing, and the data type of the execution data is not limited herein.

It can be understood that, in the memory controller 100 and the flash memory chip provided in this embodiment, the main program, the writing algorithm subroutine S20, the erasing algorithm subroutine S30 and the reading algorithm subroutine S10 set in the controller 110 based on the instruction set are triggered by the user instruction, corresponding execution data can be generated, then the control register set 191 can generate corresponding enabling data according to the execution data, and then the execution circuit 192 can control the reading and erasing operations of the memory unit according to the enabling data, on this basis, the corresponding subroutine can be flexibly and conveniently adjusted according to the use requirement without changing the hardware configuration; meanwhile, when the capacity is upgraded, namely the number of the memory units is increased, only the electrical connection relation between the execution circuit 192 and the newly increased memory units is increased, and the capacity can be expanded by adjusting corresponding subroutines.

The execution circuit 192 includes a high voltage generator 120, a row-column decoder 130, a static memory 140, and a sense amplifier 150, wherein the high voltage generator 120 is electrically connected to the control register set 191 for generating a corresponding operation voltage; the row-column decoder 130 is electrically connected to the control register set 191, and is configured to generate a corresponding operation address; the static memory 140 is electrically connected to the controller 110 and the control register set 191, and is used for storing data to be written; the sense amplifier 150 is electrically connected to the control register set 191 for reading data from the memory cells.

In one embodiment, the control register set 191 includes a read control register 160, a write control register 170, and a erase control register 180, where the read control register 160 is electrically connected to the high voltage generator 120, the column decoder 130, and the sense amplifier 150, and is used to enable the high voltage generator 120, the column decoder 130, and the sense amplifier 150 to perform a read operation of the memory cell; the write control register 170 is electrically connected to the high voltage generator 120, the row-column decoder 130 and the static memory 140, and is used for enabling the high voltage generator 120, the row-column decoder 130 and the static memory 140 to perform a write operation of the memory cell; the erase control register 180 is electrically connected to the high voltage generator 120 and the column decoder 130, and is used for enabling the high voltage generator 120 and the column decoder 130 to perform an erase operation of the memory cell.

As shown in fig. 2, in one embodiment, the read control register 160 includes a read enable operation bit, a read voltage start operation bit, a read preparation end operation bit, a read pre-process operation bit, and a read unit control bit, the read enable operation bit being used to control whether a read operation is performed; the read voltage start operation bit is used for controlling whether to start the read voltage of at least one memory cell; the read preparation ending operation bit is used for controlling whether to end the read preparation operation of at least one memory cell; the read preprocessing operation bit is used for controlling whether to perform read preprocessing operation of at least one memory cell; the read unit control bit is used to control whether a read operation is performed on the memory cell.

For example, the read control register 160 may have a capacity of at least 5bits, preferably typically 8bits, and bit 0 may be a read enable operation bit M_RDr, which when 1 indicates that a read operation of at least one memory cell is allowed; when it is 0, it indicates that the read operation of at least one memory cell is prohibited. Bit 1 may be a read voltage enable operation bit M_PUMPr, which when it is 1, indicates a read voltage that allows at least one memory cell to be enabled; when it is 0, it indicates that the read voltage of at least one memory cell is inhibited from being activated. Bit 2 may be a read ready end operation bit m_dischr, which when it is 1, indicates that the read ready operation of at least one memory cell is allowed to end; when it is 0, this indicates that the read preparation operation of at least one memory cell is prohibited from ending. Bit 3 may be a read pre-process operation bit M_PRER, which when it is 1, indicates that the read pre-process operation of at least one memory cell is allowed; when it is 0, it indicates that the read pre-processing operation of at least one memory cell is prohibited. Bit 4 may be a read unit control bit m_charge, which when it is 1, indicates that a read operation is allowed on the memory cell; when it is 0, it indicates that the read operation on the memory cell is prohibited. Bits 5 through 7 are Reserved (Reserved), and optionally, the user may define the function for bits 5 through 7 by himself.

It is appreciated that a read operation to at least one memory cell may be implemented in accordance with the present embodiment.

As shown in fig. 3, in one embodiment, the write control register 170 includes a write enable operation bit, a write voltage start operation bit, a write preparation end operation bit, a write pre-process operation bit, a write unit control bit, a first program state enable bit, a second program state enable bit, and a third program state enable bit, the write enable operation bit being used to control whether a write operation of at least one memory cell is performed; the write voltage enable operation bit is used for controlling whether to enable the write voltage of at least one memory cell; the write ready end operation bit is used to control whether to end a write ready operation of at least one memory cell; the write preprocessing operation bit is used for controlling whether write preprocessing operation of at least one storage unit is performed or not; the writing unit control bit is used for controlling whether writing operation is performed on the storage unit or not; the first program state enable bit is used to control whether the first program state is performed; the second program state enable bit is used to control whether the second program state is performed; the third program state enable bit is used to control whether the third program state is performed.

For example, the write control register 170 may have a capacity of at least 8bits, and bit 0 may be a write enable operation bit p_rdr, which when it is 1, indicates that a write operation of at least one memory cell is allowed; when it is 0, it indicates that the write operation of at least one memory cell is prohibited. Bit 1 may be a write voltage enable operation bit p_pur, which when it is 1, indicates a write voltage that allows at least one memory cell to be enabled; when it is 0, this indicates that the write voltage of at least one memory cell is inhibited from being activated. Bit 2 may be a write ready end operation bit p_dischr, which when it is 1, indicates that the write ready operation of at least one memory cell is allowed to end; when it is 0, it means that the write preparation operation of at least one memory cell is prohibited from ending. Bit 3 may be a write pre-process operation bit p_pre, which when it is 1, indicates that a write pre-process operation of at least one memory cell is allowed; when it is 0, it indicates that the write preprocessing operation of at least one memory cell is prohibited. Bit 4 may be a write unit control bit p_charge, which when it is 1, indicates that a write operation is allowed to be performed on the memory cell; when it is 0, it indicates that writing to the memory cell is prohibited. Bit 5 may be a first program state enable bit p_st2, which when it is 1, indicates that the first program state is allowed; when it is 0, this indicates that the first programming state is inhibited. Bit 6 may be a second program state enable bit p_st1, which when it is 1, indicates that the second program state is allowed; when it is 0, this indicates that the second programming state is inhibited. Bit 7 may be a third program state enable bit p_st0, which when it is 1, indicates that the third program state is allowed; when it is 0, this indicates that the third programming state is inhibited.

It is appreciated that a write operation to at least one memory cell may be implemented in accordance with the present embodiment.

As shown in fig. 4, in one embodiment, the erase control register 180 includes an erase enable operation bit, an erase voltage start operation bit, an erase preparation end operation bit, an erase pre-process operation bit, an erase unit control bit, a first erase state enable bit, a second erase state enable bit, and a third erase state enable bit, the erase enable operation bit being used to control whether an erase operation is performed; the erase voltage start operation bit is used for controlling whether to start the erase voltage of at least one memory cell; the erase preparation end operation bit is used for controlling whether to end the erase preparation operation of at least one memory cell; the wiping pretreatment operation bit is used for controlling whether wiping pretreatment operation of at least one storage unit is performed or not; the erasing unit control bit is used for controlling whether the memory cell is erased or not; the first erase state enable bit is used to control whether the first erase state is performed; the second erase state enable bit is used to control whether the second erase state is performed; the third erase state enable bit is used to control whether the third erase state is performed.

For example, the erase control register 180 may have a capacity of at least 8bits, and bit 0 may be an erase enable operation bit E_RDr, which when it is 1, indicates that an erase operation of at least one memory cell is allowed; when it is 0, it means that the erasing operation of at least one memory cell is prohibited. Bit 1 may be an erase voltage enable operation bit E_PUMPr, which when it is 1, indicates an erase voltage that allows at least one memory cell to be enabled; when it is 0, it indicates that the erase voltage of at least one memory cell is inhibited from being activated. Bit 2 may be a wipe ready end operation bit e_dischr, which when it is 1, indicates that the wipe ready operation of at least one memory cell is allowed to end; when it is 0, it means that the erase preparation operation of at least one memory cell is prohibited from ending. Bit 3 may be a wipe pre-process operation bit E_PRER, which when it is 1, indicates that the wipe pre-process operation of at least one memory cell is allowed; when it is 0, it means that the erase pretreatment operation of at least one memory cell is prohibited. Bit 4 may be an erase unit control bit E_CHARGER, which when it is 1, indicates that the memory cell is allowed to be erased; when it is 0, this indicates that the erasing operation on the memory cell is prohibited. Bit 5 may be a first erase state enable bit e_st2, which when it is 1, indicates that the first erase state is allowed; when it is 0, it indicates that the first erase state is prohibited. Bit 6 may be a second erase state enable bit e_st1, which when it is 1, indicates that the second erase state is allowed; when it is 0, it indicates that the second erase state is prohibited. Bit 7 may be a third erase state enable bit e_st0, which when it is 1, indicates that the third erase state is allowed; when it is 0, it means that the third erase state is prohibited.

It will be appreciated that the wiping operation of at least one memory cell may be implemented in accordance with the present embodiment.

As shown in fig. 5, in one embodiment, the over-erasure correction control register 190 includes an over-erasure correction enabling operation bit, an over-erasure correction voltage starting operation bit, an over-erasure correction preparation ending operation bit, an over-erasure correction preprocessing operation bit, an over-erasure correction unit control bit, a first over-erasure correction state enabling bit, a second over-erasure correction state enabling bit, and a third over-erasure correction state enabling bit, the over-erasure correction enabling operation bit being used to control whether or not to perform an over-erasure correction operation; the over-erase correction voltage enable operation bit is used to control whether to enable the over-erase correction voltage of at least one memory cell; an over-erase correction preparation end operation bit for controlling whether to end an over-erase correction preparation operation of at least one memory cell; the over-erase correction pre-process operation bit is used for controlling whether to perform over-erase correction pre-process operation of at least one memory cell; the over-erasure correction unit control bit is used for controlling whether over-erasure correction operation is performed on the memory cells; the first over-erase correction state enable bit is used for controlling whether the first over-erase correction state is performed; the second over-erase correction state enable bit is used to control whether the second over-erase correction state is performed; the third over-erase correction state enable bit is used to control whether the third over-erase correction state is performed.

For example, the capacity of the over-erasure correction control register 190 may be at least 8bits, and bit 0 may be an over-erasure correction enabling operation bit o_rdr, which when it is 1, indicates that over-erasure correction operation of at least one memory cell is allowed; when it is 0, it means that the over-erase correction operation of at least one memory cell is prohibited. Bit 1 may be an over-erase correction voltage enable operation bit o_pur, which when it is 1, indicates an over-erase correction voltage that allows at least one memory cell to be enabled; when it is 0, this indicates that the over-erase correction voltage of at least one memory cell is disabled. Bit 2 may be an over-erase correction preparation ending operation bit o_dischr, which when it is 1, indicates that the over-erase correction preparation operation of at least one memory cell is allowed to end; when it is 0, it means that the over-erasure correction preparation operation of at least one memory cell is prohibited. Bit 3 may be an over-erase correction pre-process operation bit o_pre, which when it is 1, indicates that over-erase correction pre-process operation of at least one memory cell is allowed; when it is 0, this indicates that the over-erase correction preprocessing operation of at least one memory cell is prohibited. Bit 4 may be an over-erase correction unit control bit o_charge, which when it is 1, indicates that over-erase correction operations are allowed for the memory cell; when it is 0, this indicates that the over-erase correction operation is prohibited for the memory cell. Bit 5 may be a first over-erase correction state enable bit o_st2, which when it is 1, indicates that the first over-erase correction state is allowed; when it is 0, it indicates that the first over-erase correction state is prohibited. Bit 6 may be a second over-erase correction state enable bit o_st1, which when it is 1, indicates that the second over-erase correction state is allowed; when it is 0, it indicates that the second over-erasure correcting state is prohibited. Bit 7 may be a third over-erase correction state enable bit o_st0, which when it is 1, indicates that the third over-erase correction state is allowed; when it is 0, it indicates that the third over-erase correction state is prohibited.

It is understood that the over-erase correction operation for at least one memory cell can be implemented based on the present embodiment.

It should be noted that, in the above embodiment, the at least one serial interface 101 is electrically connected to the high voltage generator 120, the row-column decoder 130, the static memory 140 and the sense amplifier 150 to implement the read/write operation of the at least one serial interface 101.

The memory controller 100 may further include a serial interface 101 and a data conversion module, where the data conversion module is electrically connected to the output end of the sense amplifier 150, the serial interface 101, and the static memory 140. The data conversion module is used for mutual conversion between serial data and parallel data, and under the enabling of the controller 110, the data conversion module can convert the serial data input by the serial interface 101 into corresponding parallel data, and then store the parallel data into the static memory 140; the data conversion module may also convert the parallel data output from the sense amplifier 150 into corresponding serial data, and then the serial interface 101 transmits the serial data to the outside. Based on this design, the memory controller 100 in this solution is compatible with existing serial peripheral interfaces, while being able to process data in a parallel fashion, making the overall process more efficient and without any changes on the peripheral.

The data conversion module may be, but not limited to, disposed in the controller 110, so that the occupied area of the memory controller 100 may be reduced. The data conversion module may also be disposed in the acceleration module 191, so that the serial-parallel conversion speed or efficiency may be improved.

The serial interface 101 may be a serial peripheral interface (SPI, serial Peripheral Interface), which is a high-speed, full duplex, synchronous communication bus, and occupies only four wires on the pins of the chip, so that the pins of the chip can be saved; the serial interface 101 may also be an IIC (Inter-Integrated Circuit Bus, integrated circuit bus) interface. The serial interface 101 may use a custom communication protocol, or may use a standard communication protocol, which is not particularly limited herein.

The user instructions may include, among other things, read operation instructions, write operation instructions, and erase operation instructions. The read operation instruction may include a read command code and a read address code. The write operation instruction includes a write command code, a write address code, and data to be written. The erase operation instruction includes an erase command code and an erase address code.

The read command code, the write command code, and the erase command code may each be, but are not limited to, 8bits, the read address code, the write address code, and the erase address code may each be, but are not limited to, 32bits, and the data to be written may be, but are not limited to, one or more bytes.

The controller 110 may further include a custom instruction set and a compiler, where the custom instruction set may include an unconditional jump instruction, a conditional jump instruction, a set instruction, a clear instruction, and a wait instruction, the set instruction may be used to set one or more bits of a register, and the clear instruction may be used to clear one or more bits of the register. It will be appreciated that the main program, the writing algorithm subroutine S20, the erasing algorithm subroutine S30, and the reading algorithm subroutine S10 described above may all be implemented based on the custom instruction set. Meanwhile, the compiler may convert various types of instructions into corresponding machine codes, for example, may convert assembly instructions into machine codes that the controller 110 may recognize, to call the above-described main program, write algorithm subroutine S20, erase algorithm subroutine S30, and read algorithm subroutine S10.

The controller 110 may be a micro-control chip, a central processing chip, or any one of a digital processing chip, an off-the-shelf programmable logic array, an off-the-shelf programmable logic device, etc.

As shown in fig. 1 to 7, in one embodiment, in response to a read operation instruction, the controller 110 enables the high voltage generator 120 to generate a corresponding read voltage through the read control register 160, enables the row and column decoder 130 to generate a corresponding read cell address, and enables the sense amplifier 150 to read out data stored in the read cell address based on the read algorithm subroutine S10.

Specifically, in response to the read command code, the controller 110 enables the high voltage generator 120 to generate a corresponding read voltage through the read control register 160 based on the read algorithm subroutine S10; in response to the read address code, controller 110 enables row and column decoder 130 to generate a corresponding read cell address via read control register 160 based on read algorithm subroutine S10; under the supply of the read voltage, the controller 110 enables the sense amplifier 150 to read out the data stored in the read cell address through the read control register 160 based on the read algorithm subroutine S10.

For example, as shown in fig. 7, the working procedure of the above-mentioned reading algorithm subroutine S10 may be: the serial interface 101 receives a read operation instruction, and then starts the read operation process: then selecting a storage unit with a corresponding address, and switching to the read operation of the storage unit through a transfer instruction; then, data processing is performed, that is, the corresponding bit value of the read control register 160 is adjusted by the corresponding instruction, so that the sense amplifier 150 can read the data in the memory cell to the controller 110; the parallel data is converted into serial data under the control of the corresponding instruction of the controller 110, and is output to the outside through the serial interface 101.

As shown in fig. 1, 6 and 8, in one embodiment, in response to the write operation instruction, the controller 110 enables the static memory 140 to store data to be written through the write control register 170, enables the high voltage generator 120 to generate a corresponding write voltage, and enables the row and column decoder 130 to generate a corresponding write unit address based on the write algorithm subroutine S20 to transfer the data to be written in the static memory 140 to the corresponding serial interface 101.

Specifically, in response to the write command code, the controller 110 enables the static memory 140 to store data to be written and enables the high voltage generator 120 to generate a corresponding write voltage through the write control register 170 based on the write algorithm subroutine S20; in response to the write address code, controller 110 enables row and column decoder 130 to generate a corresponding write unit address via write control register 170 based on write algorithm subroutine S20.

For example, as shown in fig. 8, the working procedure of the above-mentioned writing algorithm subroutine S20 may be: the serial interface 101 receives the write operation instruction, and starts the write operation process: preparing data, namely preparing and starting a write voltage; comparing the data to be written with the data in the storage unit to obtain a comparison result; if the comparison result is that the data to be written is stored in the storage unit, the writing operation is ended. If the data to be written is not stored in the storage unit, starting and preparing the write voltage, and adjusting the corresponding bit value of the write control register 170 through a plurality of instructions to control the high voltage generator 120 to start the charge pump to prepare the high voltage; adjusting the corresponding bit value of the write control register 170 by a plurality of instructions, writing to the first cell; restarting and preparing the write voltage, adjusting the corresponding bit value of the write control register 170 by a plurality of instructions to control the high voltage generator 120 to start the charge pump to prepare the high voltage; adjusting the corresponding bit value of the write control register 170 by a plurality of instructions, writing to the second cell; and then replacing the address of the writing unit, and switching to the next storage unit for writing operation through an instruction.

It will be appreciated that when the present write operation is completed, the controller 110 enters a wait state until the serial interface 101 receives a next write operation instruction.

It should be noted that one write unit address may correspond to one or more units, for example, one write unit address may correspond to a first unit or a second unit, or one write unit address may also correspond to both the first unit and the second unit. The storage space of the first unit or the second unit may be one bit or a plurality of bits, for example, may be 16bits, 32bits, 64bits, and so on.

As shown in fig. 1, 6 and 9, in one embodiment, in response to the erase operation instruction, the controller 110 enables the high voltage generator 120 to generate a corresponding erase voltage through the erase control register 180 and enables the row and column decoder 130 to generate a corresponding erase unit address based on the erase algorithm subroutine S30 to erase the serial interface 101 corresponding to the erase unit address.

Specifically, in response to the wipe command code, the controller 110 enables the high voltage generator 120 to generate a corresponding wipe voltage through the wipe control register 180 based on the wipe algorithm subroutine S30; in response to the erase address code, the controller 110 enables the row and column decoder 130 to generate a corresponding erase unit address through the erase control register 180 based on the erase algorithm subroutine S30.

For example, as shown in fig. 9, the operation of the wiping algorithm subroutine S30 may be: the serial interface 101 receives the wiping operation instruction, and then starts the wiping operation process: firstly, adjusting corresponding bit values of the write control register 170 through a plurality of instructions to realize programming operation on a memory unit; then the corresponding bit value of the erasing control register 180 is adjusted through a plurality of instructions, so that the erasing operation on the memory cell is realized; optionally, finally, the over-erase correction operation on the memory cell is implemented based on the over-erase correction subroutine S31 and by adjusting the corresponding bit values of the over-erase correction control register 190 through a plurality of instructions.

After the end of the wiping operation, the controller 110 may enter a waiting state until the serial interface 101 receives a next wiping operation instruction.

The working process of the over-erase correction subroutine S31 may be as shown in fig. 10, and is specifically as follows:

firstly, starting an over-erasure correction process; then setting a start address of over-erasure correction; then, performing over-erasure correction verification operation on the storage unit corresponding to the starting address through an instruction or a program, obtaining a verification operation result, and then completing comparison of the verification operation result through the instruction; if the verification operation result is that the over-erasure does not occur, jumping to the next address through the instruction, judging whether the next address is the last address, and if so, ending the over-erasure correction process; if not, the address is added, and the corresponding verification operation result after the address is added is compared, and the verification operation result is sequentially circulated and directly added to the last address. If the result of the verify operation is that over-erasure occurs, the corresponding bit values of the over-erasure correction control register 190 are adjusted by a plurality of instructions to program the corresponding memory bits, for example, 0 to 31 bits, 32 to 63 bits, 64 to 95 bits, 96 to 127 bits, etc. may be programmed in sequence, then 0 to 127 bits may be discharged, and then the comparison step may be skipped by the instructions.

TABLE 1-1

opcode(6bit)	instruction address(8bit)
		opcode(6bit)	bit-register(8bit)

TABLE 1-2

Tables 1 to 3

In one embodiment, the instruction set includes a branch type instruction and a bit operation type instruction, where the branch type instruction may be a control program branch type instruction, which may include an unconditional branch type instruction and a conditional branch type instruction. The bit manipulation class instructions may include a set instruction that may be used to set one or more bits of a register and a clear instruction that may be used to clear one or more bits of a register. This may be to zero out or set the code value on the corresponding bit in each register. When there is a time interval for the transfer-type instructions and/or the bit-operation-type instructions to execute with respect to each other, the instruction set may be appropriately configured with wait instructions for executing wait operations to transition the time interval. It will be appreciated that this wait instruction is not necessary.

Specifically, in table 1-1 shown below, "opcode (6 bit)" is used to represent an operation code of 6 bits in a control program transfer type instruction or a bit operation type instruction, "instruction address (8 bit)" is used to represent an instruction address of 8 bits in a control program transfer type instruction, and "bit-register (8 bit)" is used to represent register bit selection data of 8 bits.

The operation codes of 6 bits in the table 1-1 can be further divided into a main operation code of 3 bits "op code 3bit" and a sub operation code of 3 bits "sub-op code 3bit" as shown in the table 1-2 and the table 1-3. "flag register bit" in tables 1-2 may be specifically expressed as three combined bits corresponding to the third through tenth rows in the second column in tables 1-3, which in turn correspond to different conditional jump instructions. The "address of the control register" of the fourth row in tables 1-2 may be specifically expressed as three combined bits corresponding to the eleventh row through the fourteenth row in the second column in tables 1-3, each of which may determine a bit of one register and then set the bit by the master opcode. The "address of control register" of the fifth row in tables 1-2 may be specifically expressed as three combined bits corresponding to the fifteenth row through the eighteenth row in the second column in tables 1-3, each of which may determine a bit of a register, and then clear the bit by the master opcode. Therefore, the bit values of each register can be operated through the self-defined instruction set shown in the table 1-2 or the table 1-3, and further the read-erase operation of the storage unit can be realized through the hardware logic circuit, and the read-erase operation of the storage unit can also be realized through a software algorithm mode, so that convenience and possibility are provided for the development of the subsequent memory function.

Because this patent only adopts four control register can control follow-up read, write, wipe, overerase correction operation, has simplified hardware structure, has cooperated these four control register to have adopted the instruction set of simplification simultaneously, only contains transfer class and bit operation class instruction, and control program transfer class instruction or bit operation class instruction only adopt the operation code of 6 bits can instruct the main operation of memory, has alleviateed the program running pressure yet.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

The memory controller and the flash memory chip provided by the embodiments of the present invention are described in detail, and specific examples are applied to illustrate the principles and the embodiments of the present invention, and the description of the above embodiments is only used to help understand the technical solution and the core idea of the present invention; those of ordinary skill in the art will appreciate that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A memory controller, comprising:

a controller for executing at least one of a main program, a writing algorithm subroutine, an erasing algorithm subroutine, and a reading algorithm subroutine set based on an instruction set in response to a user instruction to generate corresponding execution data;

the control register set is electrically connected with the controller and used for generating corresponding enabling data according to the execution data; and

and the execution circuit is electrically connected with the control register set and used for controlling the read-write operation of the storage unit according to the enabling data.

2. The memory controller of claim 1, wherein the execution circuit comprises:

the high voltage generator is electrically connected with the control register set and used for generating corresponding operation voltages;

the row-column decoder is electrically connected with the control register set and used for generating a corresponding operation address;

the static memory is electrically connected with the controller and the control register set and is used for storing data to be written; and

and the sense amplifier is electrically connected with the control register set and used for reading out the data in the memory unit.

3. The memory controller of claim 2, wherein the control register set comprises:

The read control register is electrically connected with the high voltage generator, the row-column decoder and the sense amplifier and is used for enabling the high voltage generator, the row-column decoder and the sense amplifier to execute the read operation of the memory unit;

the write control register is electrically connected with the high voltage generator, the row-column decoder and the static memory and is used for enabling the high voltage generator, the row-column decoder and the static memory to execute write operation of a storage unit; and

and the erasing control register is electrically connected with the high voltage generator and the row-column decoder and is used for enabling the high voltage generator and the row-column decoder to execute the erasing operation of the memory unit.

4. The memory controller of claim 3, wherein the set of control registers includes an over-erase correction control register electrically coupled to the controller, the over-erase correction control register to control over-erase correction operations of the at least one memory cell.

5. The memory controller of claim 1, wherein the instruction set includes a branch class instruction and a bit operation class instruction, each of the branch class instructions including a 6 bit opcode and an 8 bit instruction address; each of the bit operation class instructions includes a 6 bit opcode and 8 bit register bit select data.

6. The memory controller of claim 5, wherein the 6-bit opcode comprises a 3-bit main opcode and a 3-bit sub opcode.

7. The memory controller of claim 3, wherein the user instruction comprises a read operation instruction;

in response to the read operation instruction, the controller enables the high voltage generator to generate a corresponding read voltage through the read control register, enables the row-column decoder to generate a corresponding read unit address, and enables the sense amplifier to read out data stored in the read unit address based on the read algorithm subroutine.

8. The memory controller of claim 7, wherein the read operation instruction comprises a read command code and a read address code;

in response to the read command code, the controller enables the high voltage generator to generate a corresponding read voltage through the read control register based on the read algorithm subroutine;

in response to the read address code, the controller enables the rank decoder to generate a corresponding read cell address through the read control register based on the read algorithm subroutine;

The controller enables the sense amplifier to read out data stored in the read cell address through the read control register based on the read algorithm subroutine under the supply of the read voltage.

9. The memory controller of claim 2, further comprising a serial interface and a data conversion module, wherein the data conversion module is electrically connected to the output end of the sense amplifier and the serial interface, and the controller enables the data conversion module to convert parallel data output by the sense amplifier into corresponding serial data and output the serial data to the outside through the serial interface.

10. The memory controller of claim 3, wherein the user instruction comprises a write operation instruction;

in response to the write operation instruction, the controller enables the static memory to store data to be written through the write control register based on the write algorithm subroutine, enables the high voltage generator to generate corresponding write voltages, and enables the row-column decoder to generate corresponding write unit addresses so as to transfer the data to be written in the static memory to corresponding storage units.

11. The memory controller of claim 10, wherein the write operation instruction includes a write command code, a write address code, and the data to be written;

in response to the write command code, the controller enables the static memory to store data to be written and enables the high voltage generator to generate a corresponding write voltage through the write control register based on the write algorithm subroutine;

in response to the write address code, the controller enables the row and column decoder to generate a corresponding write unit address via the write control register based on the write algorithm subroutine.

12. The memory controller of claim 3, wherein the user instruction comprises a wipe operation instruction;

in response to the erase operation instruction, the controller enables the high voltage generator to generate a corresponding erase voltage through the erase control register based on the erase algorithm subroutine, and enables the row-column decoder to generate a corresponding erase unit address so as to erase a memory cell corresponding to the erase unit address.

13. The memory controller of claim 12, wherein the erase operation instruction includes an erase command code and an erase address code;

In response to the wipe command code, the controller enables the high voltage generator to generate a corresponding wipe voltage through the wipe control register based on the wipe algorithm subroutine;

in response to the erase address code, the controller enables the row and column decoder to generate a corresponding erase unit address through the erase control register based on the erase algorithm subroutine.

14. The memory controller of claim 4, wherein the erase algorithm subroutine further comprises an over-erase correction subroutine, the controller executing the over-erase correction subroutine on erased memory cells through the over-erase correction control register based on the erase algorithm subroutine in response to the erase operation instruction.

15. A flash memory chip, comprising:

the memory controller of any one of claims 1 to 14; and

and the at least one storage unit is electrically connected with the execution circuit.