CN116302744A - Signal collision verification method, device, equipment and storage medium - Google Patents
Signal collision verification method, device, equipment and storage medium Download PDFInfo
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Abstract
The application discloses a signal conflict verification method, a device, equipment and a storage medium, which relate to the field of chip verification and comprise the following steps: acquiring an internal conflict signal generated when a write/read request terminal accesses an SRAM module to be tested simultaneously; and screening out target signals with low priority from the target signals; judging whether the current target operation corresponding to the target signal is back-pressed or not, if so, accumulating and counting the back-pressed times, monitoring whether the obtained first back-pressing count value reaches a preset threshold value, if so, triggering a preset adjustment flow of the initial mapping relation when the preset signal is at a rising edge, and carrying out an assertion test on whether the preset signal is pulled up and the preset beat number is kept; and if the result of the assertion test is that the result is that the corresponding assertion is not reported by mistake. According to the method and the device, through monitoring the internal signal collision condition in real time, the situation that corresponding operation is executed on the signal with high priority all the time is avoided, the preset control signal is tested in an assertion mode, abnormal information is fed back in time, and the debugging rate of signal collision verification is improved.
Description
Technical Field
The present invention relates to the field of chip verification, and in particular, to a method, apparatus, device, and storage medium for verifying signal collision.
Background
In chip verification, the main work is to perform data comparison and function verification on verified modules. The common check mechanism is to collect data at the output end of the module to be tested SRAM (Static Random Access Memory ) and compare the collected data with the output data of the reference model with consistent functions. Although the check mechanism can meet the verification requirements of most functional modules, for a control complex module, feedback is not timely or even false easily occurs when the function of the concerned test point is abnormal, and meanwhile, the logic debugging efficiency of the SRAM module to be tested is still to be improved.
Disclosure of Invention
Accordingly, the present invention is directed to a method, apparatus, device, and storage medium for verifying signal collision, which can avoid executing corresponding operation on a signal with high priority all the time by monitoring internal signal collision conditions in real time, and test a preset control signal in an assertion manner, and timely feed back abnormal information to improve the debug rate of signal collision verification. The specific scheme is as follows:
in a first aspect, the present application provides a signal collision verification method, including:
acquiring an internal conflict signal generated when a write request end and a read request end access an SRAM module to be tested simultaneously;
determining the priority of each signal in the internal conflict signals by using the initial mapping relation and the access mode corresponding to the signals, and screening out target signals with low priority;
judging whether the current target operation corresponding to the target signal is back-pressed or not, if so, carrying out accumulated statistics on the back-pressed times to obtain a first back-pressing count value;
monitoring whether the first back pressure count value reaches a preset back pressure times threshold value, if so, triggering a preset adjustment flow aiming at the initial mapping relation when a preset control signal is at a rising edge, and carrying out assertion test on whether the preset control signal is pulled up and a preset beat number is kept;
if the result of the assertion test is yes, the preset adjustment flow is characterized to be executed; if the result of the assertion test is negative, corresponding assertion error reporting is carried out.
Optionally, the determining whether the target operation currently corresponding to the target signal is back-pressed includes:
when the target signal is at a high level, judging whether the current target associated signal is at a high level or not; the target associated signal corresponds to the same access mode as the target signal;
and if the current target association signal is at a high level, judging that the target operation corresponding to the target signal is back-pressed.
Optionally, the performing cumulative statistics on the times of the back pressure to obtain a first back pressure count value includes:
accumulating statistics is carried out on the times of the back pressure to be detected through a first counter preset in the verification environment, so as to obtain a first back pressure count value; the verification environment is an environment for verifying the SRAM module to be tested.
Optionally, after the determining whether the target operation corresponding to the target signal is currently back-pressed, the method further includes:
and if not, carrying out zero clearing operation on the first counter, and re-jumping to the step of judging whether the target operation corresponding to the target signal is back-pressed or not.
Optionally, after the accumulated statistics of the times of the back pressure to obtain the first back pressure count value, the method further includes:
monitoring whether the first counter-pressure count value counted by the first counter is consistent with a second counter-pressure count value counted by a second counter in the SRAM module to be tested; the second counter is used for carrying out accumulated statistics on the back pressure times to obtain a second back pressure count value;
if the verification environments are inconsistent, carrying out assertion error reporting through the verification environments;
and if the verification environment is consistent with the verification environment, prohibiting triggering the step of carrying out assertion error reporting through the verification environment.
Optionally, after the monitoring whether the first counter-pressure count value reaches the preset counter-pressure count threshold value, the method further includes:
if not, the step of judging whether the target operation corresponding to the target signal is back-pressed is resumed.
Optionally, the preset adjustment process includes:
and performing a first overturn operation on the initial mapping relation to obtain an overturned mapping relation, performing corresponding target operation in a time period corresponding to the preset beats, and triggering a second overturn operation when the preset control signal is in a falling edge so as to restore the overturned mapping relation to the initial mapping relation.
In a second aspect, the present application provides a signal collision verification apparatus, including:
the conflict signal acquisition module is used for acquiring internal conflict signals generated when the write request end and the read request end access the SRAM module to be tested simultaneously;
the target signal screening module is used for determining the priority of each signal in the internal conflict signals by utilizing the initial mapping relation and the access mode corresponding to the signals and screening out target signals with low priority;
the frequency counting module is used for judging whether the current target operation corresponding to the target signal is back-pressed or not, and if so, carrying out accumulated statistics on the back-pressed frequency to obtain a first back-pressing count value;
the assertion test module is used for monitoring whether the first back pressure count value reaches a preset back pressure times threshold value, if so, triggering a preset adjustment flow aiming at the initial mapping relation when a preset control signal is at a rising edge, and carrying out assertion test on whether the preset control signal is pulled up and a preset beat number is kept;
the assertion error reporting module is used for characterizing that the preset adjustment flow is executed if the assertion test result is yes; if the result of the assertion test is negative, corresponding assertion error reporting is carried out.
In a third aspect, the present application provides an electronic device, including:
a memory for storing a computer program;
and a processor for executing the computer program to implement the aforementioned signal collision verification method.
In a fourth aspect, the present application provides a computer readable storage medium storing a computer program which, when executed by a processor, implements the aforementioned signal collision verification method.
In the application, an internal conflict signal generated when a write request end and a read request end access an SRAM module to be tested simultaneously is obtained; determining the priority of each signal in the internal conflict signals by using the initial mapping relation and the access mode corresponding to the signals, and screening out target signals with low priority; judging whether the current target operation corresponding to the target signal is back-pressed or not, if so, carrying out accumulated statistics on the back-pressed times to obtain a first back-pressing count value; monitoring whether the first back pressure count value reaches a preset back pressure times threshold value, if so, triggering a preset adjustment flow aiming at the initial mapping relation when a preset control signal is at a rising edge, and carrying out assertion test on whether the preset control signal is pulled up and a preset beat number is kept; if the result of the assertion test is yes, the preset adjustment flow is characterized to be executed; if the result of the assertion test is negative, corresponding assertion error reporting is carried out. Therefore, the internal conflict signals generated when the write request end and the read request end access the SRAM module to be tested simultaneously are monitored in real time, accumulated statistics is carried out on the back pressure times corresponding to the target signals with low priority, when the back pressure times reach the preset back pressure times threshold value, the priority of the target signals is correspondingly adjusted by adjusting the preset control signals, and therefore corresponding functional operation is prevented from being executed on the signals with high priority in the initial mapping relation all the time; in addition, the preset control signal is tested in an assertion mode, when the assertion test result is NO, the preset control signal is not pulled up and kept in preset beats according to the expectation, namely the priority of the target signal is not adjusted correspondingly according to the expectation, so that the situation that the currently executed function operation is inconsistent with the expected function operation easily occurs, abnormal information can be fed back in real time through assertion error reporting, and the accuracy rate and the error-removal rate of signal conflict verification are improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a signal collision verification method disclosed in the present application;
FIG. 2 is a schematic diagram of signal collision disclosed in the present application;
FIG. 3 is a flow chart of signal collision verification disclosed herein;
fig. 4 is a schematic structural diagram of a signal collision verification device disclosed in the present application;
fig. 5 is a block diagram of an electronic device disclosed in the present application.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
At present, for a control complex module, when the function of a concerned test point is abnormal, feedback is not timely and even false occurs easily, and meanwhile, the logic debugging efficiency of the SRAM module to be tested is also required to be improved. Therefore, the signal conflict verification method is provided, through monitoring the internal signal conflict condition of the SRAM module to be tested in real time, the situation that corresponding operation is executed on signals with high priority all the time is avoided, the preset control signals are tested in an assertion mode, abnormal information is fed back in time, and the accuracy rate and the debugging rate of the signal conflict verification are improved.
Referring to fig. 1, the embodiment of the invention discloses a signal collision verification method, which comprises the following steps:
and S11, acquiring an internal conflict signal generated when the write request end and the read request end access the SRAM module to be tested simultaneously.
In this embodiment, as shown in fig. 2, in the SRAM chip to be verified, 16 small SRAM regions are divided in total, and each small SRAM region is called a bank (memory bank), i.e., an SRAM module to be tested. Wherein, each clock in one SRAM module to be tested can only perform one operation of reading or writing. When the read request end and the write request end access the SRAM module to be tested simultaneously, a read signal and a write signal are obtained simultaneously, namely when the read signal wvalid and the write signal rvaild exist simultaneously, signal conflict can be generated.
And step S12, determining the priority of each signal in the internal conflict signals by utilizing the initial mapping relation and the access mode corresponding to the signals, and screening out the target signals with low priority.
In this embodiment, when the read signal and the write signal are received at the same time, it is necessary to determine the target signal with low priority from the read signal and the write signal according to the priority configuration of the internal logic. Specifically, an initial mapping relation is built in advance based on access modes and priorities, and different access modes correspond to different priorities, wherein the access modes comprise a reading mode and a writing mode. And determining the priorities corresponding to the read signal and the write signal respectively by using the initial mapping relation and the access modes corresponding to the read signal/write signal respectively, and screening out signals with low priorities from the priorities as target signals. Meanwhile, for the signal with high priority, the corresponding functional operation can be started to be executed. For example, if the priority of the read mode is high and the priority of the write mode is low in the initial mapping relationship, the priority of the read signal and the priority of the write signal are determined by combining the access modes respectively corresponding to the read signal and the write signal, and the write signal is the target signal at the time when the priority of the read signal is low. For the read signal with high priority, the execution of the read function operation corresponding to the read signal can be started.
And S13, judging whether the target operation corresponding to the target signal is back-pressed or not, and if so, carrying out accumulated statistics on the back-pressed times to obtain a first back-pressing count value.
In this embodiment, after determining the target signal, it is further required to determine whether the target operation corresponding to the target signal is currently being back-pressed, that is, whether the target signal is received at this time, but the target operation corresponding to the target signal is not allowed to be performed.
Specifically, when the target signal is received, that is, the target signal is at a high level, whether the current target associated signal is at the high level is further judged; wherein the target associated signal corresponds to the same access pattern as the target signal; if the current target-related signal is high, it is determined that the target operation currently corresponding to the target signal is back-pressed. When the current target-related signal is at a high level, it indicates that the target operation corresponding to the target signal is not allowed to be performed currently, that is, the target operation corresponding to the target signal is back-pressed. If the target operation corresponding to the target signal is back-pressed, accumulating and counting the back-pressed times through a first counter preset in the verification environment to obtain a first back-pressing count value; wherein the initial value of the first counter is 0; the verification environment is an environment for verifying the SRAM module to be tested. It will be appreciated that the first counter in the verification environment is incremented each time a target signal arrives but is not allowed to perform a target operation corresponding to the target signal, to obtain a first backpressure count value.
In this embodiment, if the target signal is at a high level and the current target-related signal is at a low level, it is indicated that the target operation corresponding to the target signal is currently permitted to be performed, that is, the target operation corresponding to the target signal is not currently back-pressed. If not, carrying out zero clearing operation on a first counter preset in the verification environment, and re-jumping to the step of judging whether the target operation corresponding to the target signal is back-pressed or not.
And S14, monitoring whether the first back pressure count value reaches a preset back pressure times threshold value, if so, triggering a preset adjustment flow aiming at the initial mapping relation when a preset control signal is at a rising edge, and carrying out assertion test on whether the preset control signal is pulled up and the preset beat number is kept.
In this embodiment, the first counter-pressure count value counted by the preset first counter in the verification environment is compared with the preset counter-pressure frequency threshold value, and if the first counter-pressure count value does not reach the preset counter-pressure frequency threshold value, the step of determining whether the target operation corresponding to the target signal is currently counter-pressure is performed again. If the first back pressure count value reaches the preset back pressure count threshold, the preset control signal is adjusted through the to-be-tested SRAM module, namely when the preset control signal is at the rising edge, a preset adjustment flow of the initial mapping relation through the to-be-tested SRAM module is triggered, and whether the preset control signal is pulled up and the preset beat number is kept is subjected to assertion test through the verification environment. The preset beats can be set by a user according to the self requirements; the preset adjustment flow comprises the steps of performing a first overturn operation on the initial mapping relation to obtain an overturned mapping relation, performing corresponding target operation in a time period corresponding to the preset beats, and triggering a second overturn operation when the preset control signal is at a falling edge so as to restore the overturned mapping relation to the initial mapping relation. If the preset number of beats is one beat, when the preset control signal is at the rising edge, the corresponding relation between the access mode and the priority in the initial mapping relation is turned over once to obtain a turned mapping relation; and simultaneously, the target operation corresponding to the target signal is executed in a period corresponding to one beat of pull-up. When the time of one beat is over, the preset control signal is automatically pulled down, and meanwhile, when the preset control signal is at the falling edge, the corresponding relation between the access mode and the priority in the mapping relation after the turnover is turned over again, so that the mapping relation after the turnover is restored to the initial mapping relation. In this way, by reversing the mapping relationship between the access pattern and the priority, it is possible to avoid performing the function operation corresponding to the signal having the higher priority in the initial mapping relationship.
In this embodiment, after the accumulated count of the times of the back pressure is performed to obtain the first back pressure count value, monitoring whether the first back pressure count value counted by the first counter is consistent with the second back pressure count value counted by the second counter in the SRAM module to be tested; the second counter is used for carrying out accumulated statistics on the times of the back pressure to obtain a second back pressure count value; if the verification environment is inconsistent, carrying out assertion error reporting through the verification environment; and if the verification environment is consistent, prohibiting triggering the step of carrying out assertion error reporting through the verification environment. It can be appreciated that by comparing the first counter-pressure count value with the second counter-pressure count value, when the first counter-pressure count value is inconsistent with the second counter-pressure count value, a corresponding assertion error can be reported through the verification environment. Therefore, by comparing the first counter-pressure count value in the verification environment with the second counter-pressure count value in the SRAM module to be tested in real time, missing detection and missing report of abnormal conditions can be avoided.
Step S15, if the result of the assertion test is yes, the preset adjustment flow is characterized as being executed; if the result of the assertion test is negative, corresponding assertion error reporting is carried out.
In this embodiment, if the result of the assertion test is yes, it indicates that the preset control signal is pulled up according to the expected situation and the preset number of beats is maintained, and at this time, the currently executed function operation is consistent with the expected function operation; if the result of the assertion test is negative, the fact that the preset control signal is not adjusted according to the expectation is indicated, and corresponding assertion error reporting is carried out at the moment so as to warn the user that an abnormal condition occurs currently, and therefore real-time feedback of abnormal information is achieved.
Therefore, the internal conflict signals generated when the write request end and the read request end access the SRAM module to be tested simultaneously are monitored in real time, accumulated statistics is carried out on the back pressure times corresponding to the target signals with low priority, when the back pressure times reach the preset back pressure times threshold value, the priority of the target signals is correspondingly adjusted by adjusting the preset control signals, and therefore corresponding functional operation is prevented from being executed on the signals with high priority in the initial mapping relation all the time; in addition, the preset control signal is tested in an assertion mode, when the assertion test result is NO, the preset control signal is not pulled up and kept in preset beats according to the expectation, namely the priority of the target signal is not adjusted correspondingly according to the expectation, so that the situation that the currently executed function operation is inconsistent with the expected function operation easily occurs, abnormal information can be fed back in real time through assertion error reporting, and the accuracy rate and the error-removal rate of signal conflict verification are improved.
Referring to fig. 3, the embodiment of the invention discloses a signal collision verification method, which comprises the following steps:
when the write request end and the read request end access the SRAM module to be tested simultaneously, internal conflict signals comprising a write signal wvalid and a read signal rvalid are generated simultaneously, and target signals with low priority can be screened out from the internal conflict signals according to the initial mapping relation between the access modes and the priority and the access modes corresponding to different signals. If the priority of the writing mode in the initial mapping relation is low, the target signal is the writing signal wvalid. When the write signal wvalid is high and the write-related signal write_allowable indicating that the write operation is not allowed to be performed currently is also high, it is determined that the write operation corresponding to the write signal is back-pressed, that is, the write request is present currently but the actual write operation cannot be performed. At this time, the accumulated count of the times of the back pressure is counted by a first counter preset in the verification environment to obtain a first back pressure count value, that is, the first counter in the verification environment is incremented when the write request arrives each time and the write is not allowed. If the write signal wvalid is high and the write associated signal write_allowable is low, it indicates that the current write operation corresponding to the write signal is not back-pressure, at this time, the first counter is cleared, and the above step of determining whether the current write operation corresponding to the write signal is back-pressure is repeated.
After determining that the writing operation corresponding to the writing signal is back-pressed and obtaining the corresponding first back-pressing count value, judging whether the first back-pressing count value reaches the preset back-pressing frequency threshold value, if not, re-jumping to the step of judging whether the writing operation corresponding to the writing signal is back-pressed or not, and continuing to accumulate and count the back-pressing frequency. If so, triggering a preset adjustment flow of the preset control signal through the SRAM module to be tested when the preset control signal priority_ack is at the rising edge, and carrying out assertion test on whether the preset control signal priority_ack is pulled high and kept for one beat through a verification environment. If the result of the assertion test is yes, the currently executed functional operation is indicated to accord with the expected functional operation, if the result of the assertion test is no, the currently executed functional operation is indicated to not accord with the expected functional operation, and corresponding assertion error is carried out. The preset adjustment process includes performing a first inversion operation on the initial mapping relationship when the preset control signal priority_ack is at the rising edge, so as to obtain an inverted mapping relationship, where the priority of the write signal is higher than the priority of the read signal. And performing corresponding writing operation in a period corresponding to the pull-up beat, triggering a second time of turning operation when the preset control signal priority_ack is at the falling edge so as to restore the mapping relation after turning to the initial mapping relation, and re-letting the priority of the read signal be higher than that of the write signal, wherein the first counter in the verification environment can also restart counting.
In addition, after the first counter-pressure count value is obtained, whether the first counter-pressure count value counted by the first counter is consistent with the second counter-pressure count value counted by the second counter in the SRAM module to be tested is also required to be monitored; if the verification environment is inconsistent, carrying out assertion error reporting through the verification environment; and if the verification environment is consistent, prohibiting triggering the step of carrying out assertion error reporting through the verification environment.
Therefore, the internal conflict signals generated when the write request end and the read request end access the SRAM module to be tested simultaneously are monitored in real time, accumulated statistics is carried out on the back pressure times corresponding to the write signals with low priority, when the back pressure times reach the preset back pressure times threshold value, the priority of the write signals is correspondingly adjusted by adjusting the preset control signals, and accordingly corresponding reading function operation is prevented from being executed on the read signals with high priority in the initial mapping relation all the time; in addition, the preset control signal is tested in an assertion mode, and when the assertion test result is negative, abnormal information can be fed back in real time, so that the accuracy and the debugging rate of signal conflict verification are improved.
Referring to fig. 4, an embodiment of the present invention discloses a signal collision verification apparatus, including:
the conflict signal acquisition module 11 is used for acquiring internal conflict signals generated when the write request end and the read request end access the SRAM module to be tested simultaneously;
the target signal screening module 12 is configured to determine a priority of each signal in the internal conflict signals by using an initial mapping relationship and an access mode corresponding to the signals, and screen out a target signal with a low priority;
the number counting module 13 is configured to determine whether a target operation corresponding to the target signal is currently back-pressed, and if so, perform cumulative statistics on the back-pressed number of times to obtain a first back-pressing count value;
an assertion testing module 14, configured to monitor whether the first counter-pressure count value reaches a preset counter-pressure frequency threshold, if so, trigger a preset adjustment flow for the initial mapping relationship when a preset control signal is at a rising edge, and perform an assertion test on whether the preset control signal has been pulled up and a preset beat number is maintained;
the assertion error reporting module 15 is configured to characterize that the preset adjustment flow is executed if the assertion test result is yes; if the result of the assertion test is negative, corresponding assertion error reporting is carried out.
Therefore, the internal conflict signals generated when the write request end and the read request end access the SRAM module to be tested simultaneously are monitored in real time, accumulated statistics is carried out on the back pressure times corresponding to the target signals with low priority, when the back pressure times reach the preset back pressure times threshold value, the priority of the target signals is correspondingly adjusted by adjusting the preset control signals, and therefore corresponding functional operation is prevented from being executed on the signals with high priority in the initial mapping relation all the time; in addition, the preset control signal is tested in an assertion mode, when the assertion test result is NO, the preset control signal is not pulled up and kept in preset beats according to the expectation, namely the priority of the target signal is not adjusted correspondingly according to the expectation, so that the situation that the currently executed function operation is inconsistent with the expected function operation easily occurs, abnormal information can be fed back in real time through assertion error reporting, and the accuracy rate and the error-removal rate of signal conflict verification are improved.
In some specific embodiments, the number statistics module 13 may specifically include:
the level judging unit is used for judging whether the current target associated signal is at a high level or not when the target signal is at the high level; the target associated signal corresponds to the same access mode as the target signal;
and the back pressure judging unit is used for judging that the target operation corresponding to the target signal is back pressure if the target associated signal is at a high level.
In some specific embodiments, the number statistics module 13 may specifically include:
the number counting unit is used for carrying out accumulated statistics on the times of the back pressure to be counted through a first counter preset in the verification environment so as to obtain a first back pressure count value; the verification environment is an environment for verifying the SRAM module to be tested.
In some specific embodiments, the signal collision verification apparatus may further include:
and the counter zero clearing unit is used for carrying out zero clearing operation on the first counter if the counter is not back-pressed, and re-jumping to the step of judging whether the target operation corresponding to the target signal is back-pressed or not.
In some specific embodiments, the signal collision verification apparatus may further include:
the count value monitoring unit is used for monitoring whether the first back pressure count value counted by the first counter is consistent with a second back pressure count value counted by a second counter in the SRAM module to be tested; the second counter is used for carrying out accumulated statistics on the back pressure times to obtain a second back pressure count value;
the assertion error reporting unit is used for reporting assertion error through the verification environment if the assertion error reporting unit is inconsistent;
and the forbidden triggering unit is used for forbidding triggering the step of carrying out assertion error reporting through the verification environment if the verification environments are consistent.
In some specific embodiments, the signal collision verification apparatus may further include:
and the step jumping unit is used for jumping to the step of judging whether the target operation corresponding to the target signal is back-pressed or not again if the target operation is not achieved.
In some specific embodiments, the signal collision verification apparatus may specifically include:
the first overturning unit is used for carrying out first overturning operation on the initial mapping relation to obtain an overturned mapping relation;
and the second overturning unit is used for carrying out corresponding target operation in a time period corresponding to the preset beat number, and triggering second overturning operation when the preset control signal is in a falling edge so as to restore the mapping relationship after overturning to the initial mapping relationship.
Further, the embodiment of the present application further discloses an electronic device, and fig. 5 is a block diagram of the electronic device 20 according to an exemplary embodiment, where the content of the figure is not to be considered as any limitation on the scope of use of the present application.
Fig. 5 is a schematic structural diagram of an electronic device 20 according to an embodiment of the present application. The electronic device 20 may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input output interface 25, and a communication bus 26. Wherein the memory 22 is configured to store a computer program that is loaded and executed by the processor 21 to implement the relevant steps in the signal collision verification method disclosed in any of the foregoing embodiments. In addition, the electronic device 20 in the present embodiment may be specifically an electronic computer.
In this embodiment, the power supply 23 is configured to provide an operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and an external device, and the communication protocol to be followed is any communication protocol applicable to the technical solution of the present application, which is not specifically limited herein; the input/output interface 25 is used for acquiring external input data or outputting external output data, and the specific interface type thereof may be selected according to the specific application requirement, which is not limited herein.
The memory 22 may be a carrier for storing resources, such as a read-only memory, a random access memory, a magnetic disk, or an optical disk, and the resources stored thereon may include an operating system 221, a computer program 222, and the like, and the storage may be temporary storage or permanent storage.
The operating system 221 is used for managing and controlling various hardware devices on the electronic device 20 and computer programs 222, which may be Windows Server, netware, unix, linux, etc. The computer program 222 may further include a computer program that can be used to perform other specific tasks in addition to the computer program that can be used to perform the signal collision verification method performed by the electronic device 20 as disclosed in any of the previous embodiments.
Further, the application also discloses a computer readable storage medium for storing a computer program; wherein the computer program, when executed by a processor, implements the signal collision verification method disclosed previously. For specific steps of the method, reference may be made to the corresponding contents disclosed in the foregoing embodiments, and no further description is given here.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. The software modules may be disposed in Random Access Memory (RAM), memory, read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing has outlined the detailed description of the preferred embodiment of the present application, and the detailed description of the principles and embodiments of the present application has been provided herein by way of example only to facilitate the understanding of the method and core concepts of the present application; meanwhile, as those skilled in the art will have modifications in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (10)
1. A method for signal collision verification, comprising:
acquiring an internal conflict signal generated when a write request end and a read request end access an SRAM module to be tested simultaneously;
determining the priority of each signal in the internal conflict signals by using the initial mapping relation and the access mode corresponding to the signals, and screening out target signals with low priority;
judging whether the current target operation corresponding to the target signal is back-pressed or not, if so, carrying out accumulated statistics on the back-pressed times to obtain a first back-pressing count value;
monitoring whether the first back pressure count value reaches a preset back pressure times threshold value, if so, triggering a preset adjustment flow aiming at the initial mapping relation when a preset control signal is at a rising edge, and carrying out assertion test on whether the preset control signal is pulled up and a preset beat number is kept;
if the result of the assertion test is yes, the preset adjustment flow is characterized to be executed; if the result of the assertion test is negative, corresponding assertion error reporting is carried out.
2. The method of claim 1, wherein determining whether a target operation currently corresponding to the target signal is counter-pressed comprises:
when the target signal is at a high level, judging whether the current target associated signal is at a high level or not; the target associated signal corresponds to the same access mode as the target signal;
and if the current target association signal is at a high level, judging that the target operation corresponding to the target signal is back-pressed.
3. The method of claim 1, wherein the step of accumulating statistics of the number of times of the counter pressure to obtain a first counter pressure count value includes:
accumulating statistics is carried out on the times of the back pressure to be detected through a first counter preset in the verification environment, so as to obtain a first back pressure count value; the verification environment is an environment for verifying the SRAM module to be tested.
4. The method of claim 3, wherein after determining whether a target operation currently corresponding to the target signal is back-pressed, further comprising:
and if not, carrying out zero clearing operation on the first counter, and re-jumping to the step of judging whether the target operation corresponding to the target signal is back-pressed or not.
5. A method of verifying signal collision as defined in claim 3, wherein after the accumulating the number of times of being back-pressed to obtain the first back-pressure count value, further comprising:
monitoring whether the first counter-pressure count value counted by the first counter is consistent with a second counter-pressure count value counted by a second counter in the SRAM module to be tested; the second counter is used for carrying out accumulated statistics on the back pressure times to obtain a second back pressure count value;
if the verification environments are inconsistent, carrying out assertion error reporting through the verification environments;
and if the verification environment is consistent with the verification environment, prohibiting triggering the step of carrying out assertion error reporting through the verification environment.
6. The method of claim 1, wherein after monitoring whether the first counter-pressure count value reaches a preset counter-pressure count threshold, further comprising:
if not, the step of judging whether the target operation corresponding to the target signal is back-pressed is resumed.
7. The method for verifying signal collision according to any one of claims 1 to 6, wherein the preset adjustment procedure includes:
and performing a first overturn operation on the initial mapping relation to obtain an overturned mapping relation, performing corresponding target operation in a time period corresponding to the preset beats, and triggering a second overturn operation when the preset control signal is in a falling edge so as to restore the overturned mapping relation to the initial mapping relation.
8. A signal collision verification apparatus, comprising:
the conflict signal acquisition module is used for acquiring internal conflict signals generated when the write request end and the read request end access the SRAM module to be tested simultaneously;
the target signal screening module is used for determining the priority of each signal in the internal conflict signals by utilizing the initial mapping relation and the access mode corresponding to the signals and screening out target signals with low priority;
the frequency counting module is used for judging whether the current target operation corresponding to the target signal is back-pressed or not, and if so, carrying out accumulated statistics on the back-pressed frequency to obtain a first back-pressing count value;
the assertion test module is used for monitoring whether the first back pressure count value reaches a preset back pressure times threshold value, if so, triggering a preset adjustment flow aiming at the initial mapping relation when a preset control signal is at a rising edge, and carrying out assertion test on whether the preset control signal is pulled up and a preset beat number is kept;
the assertion error reporting module is used for characterizing that the preset adjustment flow is executed if the assertion test result is yes; if the result of the assertion test is negative, corresponding assertion error reporting is carried out.
9. An electronic device, comprising:
a memory for storing a computer program;
a processor for executing the computer program to implement the signal collision verification method of any one of claims 1 to 7.
10. A computer readable storage medium for storing a computer program which when executed by a processor implements a signal collision verification method according to any one of claims 1 to 7.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202310224088.4A CN116302744A (en) | 2023-03-06 | 2023-03-06 | Signal collision verification method, device, equipment and storage medium |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116933702A (en) * | 2023-09-14 | 2023-10-24 | 北京开源芯片研究院 | Verification method, verification device, electronic equipment and readable storage medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116933702A (en) * | 2023-09-14 | 2023-10-24 | 北京开源芯片研究院 | Verification method, verification device, electronic equipment and readable storage medium |
| CN116933702B (en) * | 2023-09-14 | 2023-12-22 | 北京开源芯片研究院 | Verification method, verification device, electronic equipment and readable storage medium |
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