CN112445749A - Signal detection recording method, system, device and medium - Google Patents
Signal detection recording method, system, device and medium Download PDFInfo
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- 238000004590 computer program Methods 0.000 claims description 8
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
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Abstract
The invention discloses a signal detection recording method, which comprises the following steps: the method comprises the steps that a programmable logic device responds to the fact that a signal to be recorded is effectively triggered, and the flag bit of a register corresponding to the signal to be recorded is set; the BMC records log information related to the signal to be recorded corresponding to the register in response to the detection of the flag bit of the register; and resetting the zone bit of the register through the BMC in response to the completion of the recording. The invention also discloses a system, a computer device and a readable storage medium. The scheme provided by the invention realizes the recording and displaying of the rapid change signal through the programmable logic device and the BMC, solves the problem that the key behavior of the system cannot be directly acquired due to slow response of the BMC, effectively records the key event of the system, so as to comprehensively understand the system behavior, facilitate the research and development positioning problem and facilitate the initial positioning problem of a client.
Description
Technical Field
The present invention relates to the field of switches, and in particular, to a signal detection recording method, system, device, and storage medium.
Background
In the switch system, the BMC is an important component of the whole switch design and is used as an independent management controller, and the BMC indicates the running state of the whole switch and whether a key signal is triggered or not is an important component of the BMC design. However, due to the limitation of sampling time, the BMC is only suitable for detecting or recording signals triggered for a long time, and for signals with fast changes, the BMC cannot detect the signals. Therefore, a scheme capable of recording a rapidly changing signal is urgently needed.
Disclosure of Invention
In view of the above, in order to overcome at least one aspect of the above problems, an embodiment of the present invention provides a signal detection recording method, including the following steps:
the method comprises the steps that a programmable logic device responds to the fact that a signal to be recorded is effectively triggered, and the flag bit of a register corresponding to the signal to be recorded is set;
the BMC records log information related to the signal to be recorded corresponding to the register in response to the detection of the flag bit of the register;
and resetting the zone bit of the register through the BMC in response to the completion of the recording.
In some embodiments, the programmable logic device, in response to detecting that the signal to be recorded is effectively triggered, sets a flag bit of a register corresponding to the signal to be recorded, further comprising:
and determining a mode for detecting the signal to be recorded according to the effective trigger type corresponding to the signal to be recorded.
In some embodiments, determining a mode of detecting the signal to be recorded according to an effective trigger type corresponding to the signal to be recorded further includes:
and determining the effective trigger of the signal to be recorded according to the detected falling edge of the signal to be recorded in response to the fact that the signal to be recorded is triggered at a low level.
In some embodiments, determining a mode of detecting the signal to be recorded according to an effective trigger type corresponding to the signal to be recorded further includes:
and determining the effective trigger of the signal to be recorded according to the detected rising edge of the signal to be recorded in response to the fact that the signal to be recorded is triggered at a high level.
In some embodiments, determining a mode of detecting the signal to be recorded according to an effective trigger type corresponding to the signal to be recorded further includes:
and judging whether the signal to be recorded is effectively triggered or not according to the detected number of the pulses of the signal to be recorded in response to the fact that the signal to be recorded is triggered by the pulse number.
In some embodiments, further comprising:
judging the starting state of the current system;
detecting the signal to be recorded with the programmable logic device in response to the system startup.
In some embodiments, in response to detecting that the flag bit of the register is set, the BMC records log information related to the signal to be recorded corresponding to the register, and further includes:
the BMC utilizes I2C to perform data communication with the programmable logic device to detect flag bits of registers in the programmable logic device corresponding to each signal to be recorded respectively.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a signal detection recording system, including:
the programmable logic device module is configured to enable the programmable logic device to respond to the detection that the signal to be recorded is effectively triggered and set the flag bit of the register corresponding to the signal to be recorded;
the BMC module is configured to record log information related to the signal to be recorded corresponding to the register in response to the fact that the BMC detects a flag bit of the register;
a reset module configured to reset the flag bit of the register by the BMC in response to completion of the recording.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer apparatus, including:
at least one processor; and
a memory storing a computer program operable on the processor, wherein the processor executes the program to perform any of the steps of the signal detection recording method as described above.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention also provides a computer-readable storage medium storing a computer program which, when executed by a processor, performs the steps of any one of the signal detection recording methods described above.
The invention has one of the following beneficial technical effects: the scheme provided by the invention realizes the recording and displaying of the rapid change signal through the programmable logic device and the BMC, solves the problem that the key behavior of the system cannot be directly acquired due to slow response of the BMC, effectively records the key event of the system, so as to comprehensively understand the system behavior, facilitate the research and development positioning problem and facilitate the initial positioning problem of a client.
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In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.
Fig. 1 is a schematic flow chart of a signal detection recording method according to an embodiment of the present invention;
fig. 2 is a flow chart of a signal detection recording method according to an embodiment of the present invention;
FIG. 3 is a communication block diagram of a BMC and a programmable logic device provided by an embodiment of the invention;
FIG. 4 is a schematic structural diagram of a signal detection recording system according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a computer device provided in an embodiment of the present invention;
fig. 6 is a schematic structural diagram of a computer-readable storage medium according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.
It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are used for distinguishing two entities with the same name but different names or different parameters, and it should be noted that "first" and "second" are merely for convenience of description and should not be construed as limitations of the embodiments of the present invention, and they are not described in any more detail in the following embodiments.
In the embodiment of the present invention, the key signal (signal to be recorded) may be an indication signal of the CPU to the whole system state, and may be, for example: CATERR #, ERR2, ERR1, ERR0, PLTRST #, therrip #, and the like. Or other rapidly changing signal.
According to an aspect of the present invention, an embodiment of the present invention provides a signal detection recording method, as shown in fig. 1, which may include the steps of:
s1, the programmable logic device responds to the detection that the signal to be recorded is effectively triggered, and sets the flag bit of the register corresponding to the signal to be recorded;
s2, the BMC records log information related to the signal to be recorded corresponding to the register in response to the detection of the flag bit of the register;
and S3, resetting the zone bit of the register through the BMC in response to the recording completion.
The scheme provided by the invention realizes the recording and displaying of the rapid change signal through the programmable logic device and the BMC, solves the problem that the key behavior of the system cannot be directly acquired due to slow response of the BMC, effectively records the key event of the system, so as to comprehensively understand the system behavior, facilitate the research and development positioning problem and facilitate the initial positioning problem of a client.
In some embodiments, as shown in fig. 2, the programmable logic device may be a CPLD or an FPGA, the CPLD/FPGA may cyclically acquire a critical signal state in real time based on a system clock, and then obtain an operating state or a critical signal trigger state of the machine through logic judgment, set or reset a flag bit, the BMC obtains a constant operating state or a critical signal trigger state of the machine through I2C, and after the BMC obtains this information, if the judgment system performs effective triggering, the BMC may record this event and reset the flag bit through I2C so that the CPLD-FPGA detects the setting again. Therefore, after the CPLD/FPGA sets the key signal flag bit register, the register is always in a set state, and the BMC actively resets the register after reading the record.
In the whole life stage of the switch, the CPLD-FPGA rapidly detects the level state of a system and a key signal in real time based on a system clock, judges whether the switch system is triggered by the key signal or not based on the sampled input signal state, and sets a key signal trigger flag bit of a corresponding register when the key signal is triggered; the BMC samples the state of the key signal based on I2C, records that the key event occurs when the key signal trigger flag bit is detected, and resets the key signal flag bit register through I2C.
In some embodiments, in step S1, in response to detecting that the signal to be recorded is effectively triggered, the programmable logic device sets a flag bit of a register corresponding to the signal to be recorded, and further includes:
and S11, determining the mode of detecting the signal to be recorded according to the effective trigger type corresponding to the signal to be recorded.
In some embodiments, S11, determining, according to the valid trigger type corresponding to the signal to be recorded, a manner of detecting the signal to be recorded, further includes:
and determining the effective trigger of the signal to be recorded according to the detected falling edge of the signal to be recorded in response to the fact that the signal to be recorded is triggered at a low level.
In some embodiments, S11, determining, according to the valid trigger type corresponding to the signal to be recorded, a manner of detecting the signal to be recorded, further includes:
and determining the effective trigger of the signal to be recorded according to the detected rising edge of the signal to be recorded in response to the fact that the signal to be recorded is triggered at a high level.
In some embodiments, S11, determining, according to the valid trigger type corresponding to the signal to be recorded, a manner of detecting the signal to be recorded, further includes:
and judging whether the signal to be recorded is effectively triggered or not according to the detected number of the pulses of the signal to be recorded in response to the fact that the signal to be recorded is triggered by the pulse number.
Specifically, the CPLD/FPGA collects the critical signals based on its fast system clock, mainly because the BMC cannot collect the critical signals that change fast. The basic principle is to sample critical signal changing edges based on a fast system clock. Therefore, the CPLD/FPGA can judge whether the signal is effectively triggered or not through the effective trigger type of the key signal. For example, when the key signal is triggered at a low level, it is necessary to determine whether a falling edge of the key signal occurs; when the high level of the key signal is triggered, whether the rising edge of the key signal occurs needs to be judged; when the key signal conveys error information through the number of pulses, the number of pulses needs to be judged. When the key signal is triggered, the key signal flag bit register is set, and the register is always in a set state.
In some embodiments, in step S2, the BMC records log information related to the signal to be recorded corresponding to the register in response to detecting that the flag bit of the register is set, and further includes:
the BMC utilizes I2C to perform data communication with the programmable logic device to detect flag bits of registers in the programmable logic device corresponding to each signal to be recorded respectively.
Specifically, as shown in fig. 3, the BMC and the CPLD/FPGA may perform data communication through I2C, that is, the CPLD/FPGA serves as an I2C communication device end, the BMC serves as an I2C communication Master end, and the BMC may access any open register of the CPLD/FPGA, that is, the BMC samples the key signal flag bit through I2C. When the key signal flag bit is set, the BMC records the trigger event and resets the key event flag bit register of the CPLD/FPGA after recording the trigger of the key event.
In some embodiments, further comprising:
judging the starting state of the current system;
detecting the signal to be recorded with the programmable logic device in response to the system startup.
Specifically, the CPLD/FPGA needs to judge whether the current system is normally started, and only when the current system is in a normal start state, the signal to be recorded is detected.
The invention provides a scheme for realizing a method for recording and displaying key signals by an exchanger system based on a CPLD/FPGA and a BMC, and particularly, the CPLD/FPGA is used for quickly detecting the system and the level state of the key signals in real time based on a system clock, judging whether the exchanger system is related to key signal triggering or not based on the sampled input signal state, and setting the key signal triggering flag bit of a corresponding register when the key signals are triggered; the BMC samples the state of the key signal based on I2C, records that the key event occurs when the key signal trigger flag bit is detected, and resets the key signal flag bit register through I2C. According to the invention, through the CPLD/FPGA and the BMC, the problem that the key behavior of the system cannot be directly acquired due to slow response of the BMC is solved, the key behavior of the system event is effectively recorded, so that the system behavior is comprehensively known, the problem of research and development positioning is facilitated, and the problem of primary positioning of a client is facilitated.
Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a signal detection recording system 400, as shown in fig. 4, including:
a programmable logic device module 401, where the programmable logic device module 401 is configured to enable a programmable logic device to set a flag bit of a register corresponding to a signal to be recorded in response to detecting that the signal to be recorded is effectively triggered;
a BMC module 402, where the BMC module 402 is configured to record log information related to the signal to be recorded corresponding to the register in response to detecting a flag bit of the register by a BMC;
a reset module 403, the reset module 403 configured to reset the flag bit of the register by the BMC in response to the recording being completed.
The scheme provided by the invention realizes the recording and displaying of the rapid change signal through the programmable logic device and the BMC, solves the problem that the key behavior of the system cannot be directly acquired due to slow response of the BMC, effectively records the key event of the system, so as to comprehensively understand the system behavior, facilitate the research and development positioning problem and facilitate the initial positioning problem of a client.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 5, an embodiment of the present invention further provides a computer apparatus 501, comprising:
at least one processor 520; and
the memory 510, the memory 510 stores a computer program 511 that is executable on the processor, and the processor 520 executes the program to perform the steps of any of the above signal detection recording methods.
Based on the same inventive concept, according to another aspect of the present invention, as shown in fig. 6, an embodiment of the present invention further provides a computer-readable storage medium 601, where the computer-readable storage medium 601 stores computer program instructions 610, and the computer program instructions 610, when executed by a processor, perform the steps of any of the above signal detection recording methods.
Finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes of the methods of the above embodiments may be implemented by a computer program to instruct related hardware to implement the methods.
Further, it should be appreciated that the computer-readable storage media (e.g., memory) herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory.
Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.
The foregoing is an exemplary embodiment of the present disclosure, but it should be noted that various changes and modifications could be made herein without departing from the scope of the present disclosure as defined by the appended claims. The functions, steps and/or actions of the method claims in accordance with the disclosed embodiments described herein need not be performed in any particular order. Furthermore, although elements of the disclosed embodiments of the invention may be described or claimed in the singular, the plural is contemplated unless limitation to the singular is explicitly stated.
It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.
The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.
It will be understood by those skilled in the art that all or part of the steps of implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of the embodiments of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.
Claims (10)
1. A signal detection recording method, comprising the steps of:
the method comprises the steps that a programmable logic device responds to the fact that a signal to be recorded is effectively triggered, and the flag bit of a register corresponding to the signal to be recorded is set;
the BMC records log information related to the signal to be recorded corresponding to the register in response to the detection of the flag bit of the register;
and resetting the zone bit of the register through the BMC in response to the completion of the recording.
2. The method of claim 1, wherein a programmable logic device sets a flag bit of a register corresponding to a signal to be recorded in response to detecting that the signal to be recorded is active, further comprising:
and determining a mode for detecting the signal to be recorded according to the effective trigger type corresponding to the signal to be recorded.
3. The method of claim 2, wherein determining a manner of detecting the signal to be recorded according to an effective trigger type corresponding to the signal to be recorded further comprises:
and determining the effective trigger of the signal to be recorded according to the detected falling edge of the signal to be recorded in response to the fact that the signal to be recorded is triggered at a low level.
4. The method of claim 2, wherein determining a manner of detecting the signal to be recorded according to an effective trigger type corresponding to the signal to be recorded further comprises:
and determining the effective trigger of the signal to be recorded according to the detected rising edge of the signal to be recorded in response to the fact that the signal to be recorded is triggered at a high level.
5. The method of claim 2, wherein determining a manner of detecting the signal to be recorded according to an effective trigger type corresponding to the signal to be recorded further comprises:
and judging whether the signal to be recorded is effectively triggered or not according to the detected number of the pulses of the signal to be recorded in response to the fact that the signal to be recorded is triggered by the pulse number.
6. The method of claim 1, further comprising:
judging the starting state of the current system;
detecting the signal to be recorded with the programmable logic device in response to the system startup.
7. The method of claim 1, wherein the BMC records log information associated with the signal to record corresponding to the register in response to detecting that a flag bit of the register is set, further comprising:
the BMC utilizes I2C to perform data communication with the programmable logic device to detect flag bits of registers in the programmable logic device corresponding to each signal to be recorded respectively.
8. A signal detection recording system, comprising:
the programmable logic device module is configured to enable the programmable logic device to respond to the detection that the signal to be recorded is effectively triggered and set the flag bit of the register corresponding to the signal to be recorded;
the BMC module is configured to record log information related to the signal to be recorded corresponding to the register in response to the fact that the BMC detects a flag bit of the register;
a reset module configured to reset the flag bit of the register by the BMC in response to completion of the recording.
9. A computer device, comprising:
at least one processor; and
memory storing a computer program operable on the processor, wherein the processor executes the program to perform the steps of the method according to any of claims 1-7.
10. A computer-readable storage medium, in which a computer program is stored which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1 to 7.
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| CN202011359465.8A CN112445749A (en) | 2020-11-27 | 2020-11-27 | Signal detection recording method, system, device and medium |
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| CN202011359465.8A CN112445749A (en) | 2020-11-27 | 2020-11-27 | Signal detection recording method, system, device and medium |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113127247A (en) * | 2021-04-01 | 2021-07-16 | 山东英信计算机技术有限公司 | Data acquisition method, system, device and medium |
| CN114442988A (en) * | 2022-02-15 | 2022-05-06 | 深圳市航顺芯片技术研发有限公司 | Data display method, data display device, clock display system, clock display device and clock display medium |
-
2020
- 2020-11-27 CN CN202011359465.8A patent/CN112445749A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113127247A (en) * | 2021-04-01 | 2021-07-16 | 山东英信计算机技术有限公司 | Data acquisition method, system, device and medium |
| CN114442988A (en) * | 2022-02-15 | 2022-05-06 | 深圳市航顺芯片技术研发有限公司 | Data display method, data display device, clock display system, clock display device and clock display medium |
| CN114442988B (en) * | 2022-02-15 | 2024-07-02 | 深圳市航顺芯片技术研发有限公司 | Data display method, device, clock display system, equipment and medium |
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