CN116281844A - Wafer-level cavity type packaging structure and preparation method thereof - Google Patents

Abstract

The invention provides a wafer-level cavity type packaging structure and a preparation method thereof, wherein the preparation method comprises the following steps: providing a kovar alloy wafer, and thinning the kovar alloy wafer to a preset thickness; forming at least one blind cavity extending along the thickness direction of the thinned kovar alloy wafer surface, and forming a kovar alloy wall between two adjacent blind cavities; providing a chip wafer with a bonding metal layer formed on the surface, and bonding the bonding metal layer with the kovar alloy wall to form a vacuum cavity between the blind cavity and the chip wafer, wherein the chip wafer in the vacuum cavity is provided with chips. The kovar alloy material is used as the cover plate wafer, a blind cavity can be directly formed by etching, the process of preparing a bonding metal layer on the cover plate wafer is avoided, the process is simple, the cost is low, the shielding performance and the heat dissipation of the product can be obviously improved, and the product yield is improved.

Description

Wafer-level cavity type packaging structure and preparation method thereof

Technical Field

The invention belongs to the technical field of chip wafer level packaging, and particularly relates to a wafer level cavity type packaging structure and a preparation method thereof.

Background

In the integrated circuit chip production process, chip packaging is an important link. Because of the very small feature sizes on the chip, it is difficult for the metal contacts to connect directly with the wires on the circuit board, and it is necessary to establish a connection between the contacts on the chip and the circuit board by packaging techniques. In addition, the chip generally needs to be protected from accidental damage during actual use. In the traditional chip packaging, single chips which are processed and segmented in advance are fixed in a packaging tube shell, contacts on the chips are connected with electric pins on the packaging tube shell through a wire bonding technology, and finally, insulating packaging materials or a capping plate are filled for sealing. With the development of semiconductor manufacturing processes, wafer level packaging (Wafer Lever Packaging, WLP) has been developed to increase the integration and reduce the cost of chip manufacturing, which is a technique in which a whole wafer is subjected to package testing and then cut to obtain individual finished chips, and the packaged chips are almost identical in size to the die. Compared with the traditional shell-and-tube packaging, the wafer-level packaging has smaller chip size and lower manufacturing cost, and is more suitable for small mobile application or high-integration system.

In recent years, microelectromechanical systems (Mico-Electro-Mechanical Systems, MEMS) have been widely used in various fields. Micro-electromechanical system chips are provided with micro-scale mechanical structures and electrodes, so that transmission or sensing of signals such as physical signals, sound signals, light signals, magnetic signals and the like can be realized, and various sensors and drivers such as pressure gauges, accelerometers, gyroscopes, microphones, micromirrors, magnetometers, temperature sensors and the like can be manufactured. The packaging technology of the mems chip references many of the above-mentioned packaging technologies of the integrated circuit chip, and further requirements are additionally put forward on the basis of the above-mentioned packaging technologies. Because the microelectromechanical components are fragile and vulnerable to external contaminants or particles, the microelectromechanical components are typically protected by a cover plate seal with a cavity. The wafer level packaging technology is also suitable for packaging the micro-electromechanical system chip, and generally, the requirement of wafer level sealing is achieved by bonding a cover plate wafer with a cavity and the micro-electromechanical system wafer, and meanwhile, the physical space between the cover plate wafer and the micro-electromechanical system wafer is maintained. At present, the problems of complex processing technology, high cost, fragility, poor heat dissipation and the like exist in preparing the wafer-level cavity type packaging structure.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a wafer level cavity type packaging structure and a method for manufacturing the same, which are used for solving the problems of complex processing technology, high cost, fragility, poor heat dissipation, etc. of the existing wafer level packaging structure with a cavity.

To achieve the above and other related objects, the present invention provides a method for manufacturing a wafer level cavity type package structure, the method comprising:

providing a kovar alloy wafer, and thinning the kovar alloy wafer to a preset thickness;

forming at least one blind cavity extending along the thickness direction of the thinned kovar alloy wafer surface, and forming a kovar alloy wall between two adjacent blind cavities;

providing a chip wafer with a bonding metal layer formed on the surface, and bonding the bonding metal layer on the chip wafer with the kovar alloy wall on the kovar alloy wafer, so that a vacuum cavity is formed between the blind cavity and the chip wafer, and a chip is arranged on the chip wafer in the vacuum cavity.

Optionally, before bonding the bonding metal layer on the chip wafer and the kovar alloy wall on the kovar alloy wafer, thinning the chip wafer to a preset thickness.

Optionally, the blind cavity is formed using a machining process or a wet etching process.

Further, the machining process is laser etching.

Optionally, the method further comprises a dicing step, wherein the chip wafer bonded with the kovar wafer is divided into independent packages.

Optionally, the vacuum cavity is formed by means of intermetallic fusion bonding.

Optionally, a plurality of blind cavities are formed on the surface of the kovar alloy wafer, and the blind cavities are identical or different in shape.

Optionally, at least one pre-cavity is formed on the surface of the kovar alloy wafer, and the pre-cavity is used as a circuit leading-out cavity of the independent package body formed later.

The invention also provides a wafer-level cavity type packaging structure, which can be prepared by adopting the preparation method of the wafer-level cavity type packaging structure, and comprises the following steps: the kovar alloy wafers and the chip wafers are bonded with each other;

forming at least one blind cavity extending along the thickness direction of the kovar alloy wafer on the surface of the kovar alloy wafer, wherein a kovar alloy wall is arranged between two adjacent blind cavities;

a bonding metal layer is formed on the surface of the chip wafer;

the kovar alloy wafer and the chip wafer are bonded with the kovar alloy wall through the bonding metal layer, and a vacuum cavity is formed between the blind cavity and the chip wafer;

and chips are arranged on the chip wafer in the vacuum cavity.

Optionally, the chip wafer is a mems chip wafer.

As described above, the wafer-level cavity type packaging structure and the preparation method thereof have the advantages that the kovar alloy material is used as the cover plate wafer, the blind cavity can be directly etched and formed, the kovar alloy can be used as the bonding material, the process of preparing the bonding metal layer on the cover plate wafer is avoided, the process is simple, and the cost is low; in addition, the kovar alloy has excellent conductive property of metal, stable smaller thermal expansion coefficient and better mechanical strength, the conductive property enables the kovar alloy to have stronger electromagnetic shielding effect, the smaller thermal expansion coefficient enables the kovar alloy not to be deformed easily in the subsequent processing process, the better mechanical strength enables the kovar alloy not to be damaged easily in the subsequent process, and the kovar alloy can thin a cover plate wafer before bonding, so that damage to a chip wafer caused by a thinning process after bonding is avoided, and the product yield is improved; finally, the kovar alloy cover plate can further improve the heat dissipation effect.

Drawings

Fig. 1 to 19 are schematic cross-sectional views of an exemplary wafer level cavity package structure after the completion of each step in the method for manufacturing the same.

Fig. 20 is a schematic cross-sectional view of a chip wafer in the method for manufacturing a wafer level cavity package according to the present invention.

Fig. 21 is a schematic cross-sectional view of a chip wafer with a bonding metal layer formed thereon in the method for manufacturing a wafer level cavity package according to the present invention.

Fig. 22 is a schematic cross-sectional view of a thinned chip wafer in the method for manufacturing a wafer level cavity package according to the present invention.

Fig. 23 is a schematic cross-sectional view of a kovar wafer in the method for manufacturing a wafer level cavity package according to the present invention.

Fig. 24 is a schematic top view of a kovar wafer in the method for manufacturing a wafer level cavity package according to the present invention.

Fig. 25 is a schematic cross-sectional view of a thinned kovar wafer in the method for manufacturing a wafer level cavity package according to the present invention.

Fig. 26 is a schematic cross-sectional structure of a wafer level cavity package structure according to the present invention after forming a blind cavity in a kovar wafer.

Fig. 27 is a schematic top view of a wafer level cavity package structure according to the present invention after forming a blind cavity in a kovar wafer.

Fig. 28 is a schematic cross-sectional structure of a wafer level cavity package structure according to the present invention after bonding a kovar wafer and a chip wafer.

Fig. 29 is a schematic top view of a wafer level cavity package structure according to the present invention after bonding a kovar wafer and a die wafer.

Description of element reference numerals

100. Kovar alloy wafer

101. Blind cavity

102. Kovar alloy wall

103. Vacuum cavity

104. Reserved cavity

201. Chip wafer

202. Front layer structure

203. Bonding metal layer

204. Cutting path

205. Self-contained package

301. Chip wafer

302. Front layer structure

303. First bond metal layer

304. Cover plate wafer

305. Photoresist layer

306. Patterned photoresist layer

307. Photoresist window

308. Blind cavity

309. Seed layer

310. Dry photoresist film

311. Dry photoresist film window

312. Second bonding metal layer

313. Vacuum cavity

314. Cutting path

315. Self-contained package

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 1 to 29. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Fig. 1 to 19 are schematic cross-sectional views of an exemplary wafer level cavity package structure after each step in the method for manufacturing the same. The preparation method comprises the following steps:

as shown in fig. 1 and 2, firstly, as shown in fig. 1, an incoming chip wafer 301 is provided, and a front layer structure 302, such as a bonding pad, a circuit lead-out bonding pad, an electrical isolation layer, etc., of a chip is formed on the surface of the chip wafer 301; as shown in fig. 2, a wafer 301 is metallized by using a stamping process, and a first bonding metal layer 303 is formed at a corresponding position of the front layer structure 302;

as shown in fig. 3, a cover wafer 304 is then provided, which is made of a silicon wafer or a glass wafer, and is covered with a photoresist layer 305 by spin coating or spray coating;

as shown in fig. 4, an exposure step is performed, in which an area to be etched is exposed or shielded on the cover wafer 304 coated with the photoresist layer 305 by using an exposure machine, and a corresponding mask, here, a positive photoresist, is manufactured according to different selected photoresists, and the area to be etched is exposed;

as shown in fig. 5 and 6, fig. 6 is a top view of the photoresist layer of fig. 5, and then a developing step is performed, and the photoresist layer 305 in the area to be etched is removed by chemical reaction using a specific chemical solution, so as to form a patterned photoresist layer 306, and a photoresist window 307 formed on the patterned photoresist layer 306 is subsequently used as an etching window for etching to form a blind cavity;

as shown in fig. 7, a dry etching step is performed, and a vacuum etching machine is used to etch silicon based on the patterned photoresist layer 306 by using a specific gas, so that blind cavities 308 with corresponding depths are etched under the condition that the openings are not changed significantly;

as shown in fig. 8, a photoresist removing step is performed, and the patterned photoresist layer 306 is removed through a chemical reaction, typically by a wet process;

as shown in fig. 9, a seed layer deposition step is performed, and a thin metal layer is deposited on the surface of the cover wafer 304 as a seed layer 309 by using a Physical Vapor Deposition (PVD) method for subsequent electroplating and conduction;

as shown in fig. 10, a film coating step is performed, and a layer of dry photoresist film 310 for exposure is attached to the surface of the cover wafer 304 by vacuum lamination;

as shown in fig. 11, an exposure step is performed, in which an area to be electroplated is exposed or shielded on the dry photoresist film 310 as required by using an exposure machine, and a corresponding mask is manufactured according to different selected photoresists, wherein the area to be etched is exposed by using positive photoresist;

as shown in fig. 12, next, a developing step is performed to remove the dry photoresist film 310 in the region to be etched by chemical reaction using a specific chemical solution, thereby forming a dry photoresist film window 311;

as shown in fig. 13, an electroplating step is performed, wherein the electroplating is performed with the cover wafer 304 as a cathode, so as to fill the dry photoresist film window 311, and a second bonding metal layer 312 is formed in the dry photoresist film window 311;

as shown in fig. 14, a photoresist removing step is performed to remove the dry photoresist film 310 in the electroless plating area by chemical reaction, so as to expose the seed layer 309, thereby facilitating the subsequent removal of the seed layer 309;

as shown in fig. 15, a seed layer removal step is then performed to chemically remove the seed layer 309 from the electroless plated region, forming a second bonding metal layer 312 for use only in subsequent bonding;

as shown in fig. 16, a metal bonding step is performed, and a vacuum cavity is formed by using wafer to wafer under a high temperature and low vacuum condition and using an intermetallic fusion bonding mode, wherein the thickness of the cover plate wafer 304 is generally thicker because alignment and transportation have certain requirements on the thickness and strength of the wafer, and fragments are not easily caused by the thickness and strength of the wafer;

as shown in fig. 17, a front side thinning step is then performed to thin the front side of the cover wafer 304 to a desired thickness using a mechanical grinder;

as shown in fig. 18, a back side thinning step is then performed to thin the chip wafer 301 to a desired thickness using a mechanical grinder;

as shown in fig. 19, a dicing step is finally performed, and dicing is performed along dicing streets 314 using mechanical dicing, resulting in individual packages 315.

The wafer-level cavity type packaging structure is characterized in that the vacuum cavity is formed by silicon or glass, the preparation process is very complex, the cost is high, the wafer-level cavity type packaging structure is fragile and has poor heat dissipation performance, and the formed packaging structure is high in cost, low in efficiency and unstable in quality. Based on this, the embodiment provides a method for manufacturing a wafer-level cavity type packaging structure, which includes the following steps:

s1: providing a kovar alloy wafer, and thinning the kovar alloy wafer to a preset thickness;

s2: forming at least one blind cavity extending along the thickness direction of the thinned kovar alloy wafer surface, and forming a kovar alloy wall between two adjacent blind cavities;

s3: providing a chip wafer with a bonding metal layer formed on the surface, and bonding the bonding metal layer on the chip wafer with the kovar alloy wall on the kovar alloy wafer, so that a vacuum cavity is formed between the blind cavity and the chip wafer, and a chip is arranged on the chip wafer in the vacuum cavity.

According to the preparation method of the wafer-level cavity type packaging structure, the kovar alloy material is used as the cover plate wafer, the blind cavity can be directly formed by etching, the kovar alloy can be used as the bonding material, the process of preparing the bonding metal layer on the cover plate wafer is avoided, and the preparation method is simple in process and low in cost; in addition, the kovar alloy has excellent conductive property of metal, stable smaller thermal expansion coefficient and better mechanical strength, the conductive property enables the kovar alloy to have stronger electromagnetic shielding effect, the smaller thermal expansion coefficient enables the kovar alloy not to be deformed easily in the subsequent processing process, the better mechanical strength enables the kovar alloy not to be damaged easily in the subsequent process, and the kovar alloy can thin a cover plate wafer before bonding, so that damage to a chip wafer caused by a thinning process after bonding is avoided, and the product yield is improved; finally, the kovar alloy cover plate can further improve the heat dissipation effect.

The following describes a method for manufacturing the wafer level cavity package structure of the present embodiment in detail with reference to the specific drawings.

As shown in fig. 23 to 25, step S1 is first performed, as shown in fig. 23 and 24, a kovar wafer 100 is provided, as shown in fig. 25, and thinned to a predetermined thickness.

Here, the thickness of the kovar wafer 100 is reduced according to actual needs, and is specifically selected according to the actual needs, which is not limited herein.

The kovar alloy has excellent mechanical strength, so that the kovar alloy can be thinned to a required thickness before bonding, the risk of damaging chips in a chip wafer during subsequent thinning after bonding with the chip wafer is effectively avoided, and the packaging yield is improved.

As shown in fig. 26 and 27, step S2 is performed to form at least one blind cavity 101 extending along the thickness direction of the thinned kovar wafer 100, and a kovar wall 102 is formed between two adjacent blind cavities 101. The kovar wall 102 serves as a bonding region for subsequent bonding with a chip wafer.

As an example, at least one pre-cavity 104 is formed on the surface of the kovar wafer 100 at the same time of forming the blind cavity 101, and the pre-cavity 104 is used as a circuit outlet cavity of a separate package formed later. Since the blind cavity 101 and the chip wafer will form a vacuum cavity, the chips in the chip wafer are packaged in the vacuum cavity, and the purpose of forming the reserved cavity 104 is to electrically connect the chips packaged in the vacuum cavity with the outside through the reserved cavity 104, the reserved cavity is generally formed at the edge of the kovar alloy wafer in each independent package formed later.

It should be noted that, for ease of understanding, fig. 26 and fig. 27 only show schematic cross-sectional and top view structures of the kovar alloy wafer of one package, and four chips are packaged in the package, so four blind cavities 101 are formed in the kovar alloy wafer 100, four chips may be packaged in the four blind cavities 101, and may be the same or different, a reserved cavity 104 is formed at an edge of the package, and the reserved cavity is communicated with the outside after cutting, so as to realize electrical connection between the chips in the package and the outside. In practice, a plurality of blind cavity 101 structures as shown in fig. 26 and 27 are formed in the kovar alloy wafer 100, and after subsequent bonding and dicing, the formed independent package contains four chips packaged by the four blind cavity structures.

As an example, a plurality of blind cavities 101 are formed on the surface of the kovar alloy wafer 100, and the shapes of the blind cavities 101 may be the same or different, specifically, the blind cavities are set according to the shapes of chips packaged later. The number of the chips packaged in the subsequently formed independent packaging bodies is selected according to actual conditions, and the number of the chips can be one or a plurality of chips; the packaged chips can be the same chip or different chips; the layout mode of the chips in the package is also set according to the actual situation.

By way of example, the depth of the blind cavity 101 is set according to the actual packaging requirements, without undue limitation.

As a preferred example, the blind cavity 101 is formed by adopting a machining process or a wet etching process, and the method can omit the prior complex process of forming grooves by adopting photoetching, dry etching, cleaning and the like, thereby simplifying the process complexity, reducing the manufacturing cost, improving the efficiency and being thinned to be quite thin without deformation because the CTE of the kovar alloy is low in strength. In this embodiment, the blind cavity 101 is preferably formed by laser etching.

As shown in fig. 28, finally, step S3 is performed to provide a die wafer 201 with a bonding metal layer 203 formed on the surface, and bond the bonding metal layer 203 on the die wafer 201 with the kovar wall 102 on the kovar wafer 100, so that a vacuum cavity 103 is formed between the blind cavity 101 and the die wafer 201, and a die is disposed on the die wafer 201 in the vacuum cavity 103.

Due to the good mechanical strength of the kovar alloy, the kovar alloy is not easy to fragment in the alignment and carrying processes.

As shown in fig. 20, a front layer structure 202 is formed on the surface of the chip wafer 201, and the front layer structure 202 includes the bonding pads of the chip, the circuit lead-out bonding pads of the individual packages, and the electrical isolation layer, which are all known in the art, and different chip structures are provided, and are not limited in detail herein.

Here, for ease of understanding, fig. 20 corresponds to the kovar wafer 100 of fig. 26 and 27, and the chip wafer 201 only shows a schematic cross-sectional structure of the chip wafer of one package. In practice, the chip wafer 201 is formed with a plurality of structures as shown in fig. 20, and after subsequent bonding and dicing, the formed independent package contains four chips.

As an example, the vacuum chamber 103 is formed by means of intermetallic fusion bonding using wafer to wafer under a high temperature and low vacuum condition. The kovar alloy is used as a bonding material, so that the kovar alloy can be directly bonded with a bonding metal layer of a chip wafer, a complex manufacturing process of the metal bonding layer on the kovar alloy wafer can be omitted, the process complexity is effectively reduced, and the cost is saved.

As shown in fig. 21, as an example, the die wafer 201 is thinned to a predetermined thickness before the bonding metal layer 203 on the die wafer 201 is bonded to the kovar wall 102 on the kovar wafer 100.

As shown in fig. 29, as an example, the bonding process further includes a step of dividing the chip wafer 201 bonded with the kovar wafer 100 into individual packages 205 along dicing streets 204.

As shown in fig. 28, the present embodiment also provides a wafer level cavity package structure, which may be manufactured by the above-mentioned manufacturing method. The beneficial effects that this packaging structure can reach can please see above-mentioned preparation method, and the following is not repeated, and this packaging structure includes: bonded kovar wafer 100 and chip wafer 201;

at least one blind cavity 101 extending along the thickness direction of the kovar alloy wafer 100 is formed on the surface of the kovar alloy wafer 100, and a kovar alloy wall 102 is arranged between two adjacent blind cavities 101;

a bonding metal layer 203 is formed on the surface of the chip wafer 201;

the kovar alloy wafer 100 and the chip wafer 201 are bonded with the kovar alloy wall 102 through the bonding metal layer 203, and a vacuum cavity 103 is formed between the blind cavity 101 and the chip wafer 201;

the chip wafer 201 in the vacuum chamber 103 is provided with chips.

By way of example, the die wafer 201 is a MEMS die wafer.

In summary, the wafer-level cavity type packaging structure and the preparation method thereof provided by the invention have the advantages that the kovar alloy material is used as the cover plate wafer, the blind cavity can be directly formed by etching, the kovar alloy can be used as the bonding material, the process of preparing the bonding metal layer on the cover plate wafer is avoided, the process is simple, and the cost is low; in addition, the kovar alloy has excellent conductive property of metal, stable smaller thermal expansion coefficient and better mechanical strength, the conductive property enables the kovar alloy to have stronger electromagnetic shielding effect, the smaller thermal expansion coefficient enables the kovar alloy not to be deformed easily in the subsequent processing process, the better mechanical strength enables the kovar alloy not to be damaged easily in the subsequent process, and the kovar alloy can thin a cover plate wafer before bonding, so that damage to a chip wafer caused by a thinning process after bonding is avoided, and the product yield is improved; finally, the kovar alloy cover plate can further improve the heat dissipation effect. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (10)

1. The preparation method of the wafer-level cavity type packaging structure is characterized by comprising the following steps of:

providing a kovar alloy wafer, and thinning the kovar alloy wafer to a preset thickness;

forming at least one blind cavity extending along the thickness direction of the thinned kovar alloy wafer surface, and forming a kovar alloy wall between two adjacent blind cavities;

providing a chip wafer with a bonding metal layer formed on the surface, and bonding the bonding metal layer on the chip wafer with the kovar alloy wall on the kovar alloy wafer, so that a vacuum cavity is formed between the blind cavity and the chip wafer, and a chip is arranged on the chip wafer in the vacuum cavity.

2. The method for manufacturing a wafer level cavity package according to claim 1, wherein: and before bonding the bonding metal layer on the chip wafer and the kovar alloy wall on the kovar alloy wafer, thinning the chip wafer to a preset thickness.

3. The method for manufacturing a wafer level cavity package according to claim 1, wherein: and forming the blind cavity by adopting a machining process or a wet etching process.

4. The method for manufacturing a wafer level cavity package of claim 3, wherein: the machining process is laser etching.

5. The method of claim 1, further comprising dicing the die wafer bonded with the kovar wafer into individual packages.

6. The method for manufacturing a wafer level cavity package according to claim 1, wherein: and forming the vacuum cavity by adopting an intermetallic fusion bonding mode.

7. The method for manufacturing a wafer level cavity package according to claim 1, wherein: and a plurality of blind cavities are formed on the surface of the kovar alloy wafer, and the shapes of the blind cavities are the same or different.

8. The method for manufacturing a wafer level cavity package according to claim 1, wherein: the kovar alloy wafer surface is also provided with at least one reserved cavity which is used as a circuit leading-out cavity of the independent package body formed later.

9. The utility model provides a wafer level cavity formula packaging structure which characterized in that, packaging structure includes: the kovar alloy wafers and the chip wafers are bonded with each other;

forming at least one blind cavity extending along the thickness direction of the kovar alloy wafer on the surface of the kovar alloy wafer, wherein a kovar alloy wall is arranged between two adjacent blind cavities;

a bonding metal layer is formed on the surface of the chip wafer;

the kovar alloy wafer and the chip wafer are bonded with the kovar alloy wall through the bonding metal layer, and a vacuum cavity is formed between the blind cavity and the chip wafer;

and chips are arranged on the chip wafer in the vacuum cavity.

10. The wafer level cavity package of claim 9, wherein: the chip wafer is a micro-electro-mechanical system chip wafer.

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