CN116264756A - Electronic device with conductive through hole array substrate - Google Patents

Abstract

The invention discloses an electronic device with a conductive through hole array substrate, which comprises a conductive through hole array substrate, an upper conductive layer and a lower conductive layer. The substrate has a plurality of inner conductive vias and has upper and lower surfaces. The upper conductive layer comprises an upper grounding conductive trace and an upper signal conductive pad which are arranged on the upper surface. The upper grounding conductive trace is electrically connected to the plurality of grounding conductive vias and has an upper hollowed-out portion exposing an upper surface of the portion. The upper signal conductive pad is arranged on the upper surface exposed by the upper hollowed-out part and is electrically connected with the signal conductive through hole. The lower conductive layer comprises a lower grounding conductive trace and a lower signal conductive pad which are arranged on the lower surface. The lower grounding conductive trace is electrically connected to the grounding conductive through holes and has a lower hollowed-out portion exposing a lower surface of the portion. The lower signal conductive pad is arranged on the lower surface exposed by the lower hollowed-out part and is electrically connected with the signal conductive through hole.

Description

Electronic device with conductive through hole array substrate

Technical Field

The present invention relates to an electronic device having a conductive via array substrate including conductive vias (via) arranged in an array.

Background

The electronic device may have a substrate with conductive vias for electrically connecting one or more electrical components mounted thereon. The conductive via provides a conductive path for transmitting an electrical signal to an electrical component electrically connected thereto.

In recent years, the demand for high frequency transmission in a shorter period of time has increased significantly. It is well known that when the impedances on the signal paths do not match, signal reflection is caused, resulting in signal distortion, affecting signal integrity. These situations become more severe in high frequency signal systems.

Disclosure of Invention

In view of the above, an object of the present invention is to provide an electronic device with a conductive via array substrate, which can be applied to the transmission of high-frequency signals.

An embodiment of the invention provides an electronic device with a conductive via array substrate, which comprises a conductive via array substrate, an upper conductive layer and a lower conductive layer. The conductive via array substrate is provided with a plurality of inner conductive vias. The inner layer conductive via includes a plurality of ground conductive vias, at least one signal conductive via, and a plurality of floating conductive vias. The conductive via array substrate has an upper surface and a lower surface. The upper conductive layer includes an upper ground conductive trace and at least one upper signal conductive pad. The upper ground conductive trace is disposed on the upper surface. The upper ground conductive trace is electrically connected to at least a plurality of ground conductive vias. The upper grounding conductive trace is provided with at least one upper hollowed-out part. The upper hollowed-out part exposes part of the upper surface. The upper signal conducting pad is arranged on the upper surface exposed by the upper hollowed-out part. The upper signal conductive pad is electrically connected to the signal conductive via. The lower conductive layer includes a lower ground conductive trace and at least one lower signal conductive pad. The lower ground conductive trace is disposed on the lower surface. The lower ground conductive trace is electrically connected to at least a plurality of ground conductive vias. The lower grounding conductive trace is provided with at least one lower hollowed-out part. The lower hollowed-out part exposes part of the lower surface. The lower signal conducting pad is arranged on the lower surface exposed by the lower hollowed-out part. The lower signal conductive pad is electrically connected to the signal conductive via. The floating conductive via is electrically isolated from the upper conductive layer and the lower conductive layer to be electrically floating.

According to the electronic device with the conductive via array substrate of the embodiment of the invention, signals can be transmitted in the up-down direction through the upper signal conductive pad, the signal conductive via and the lower signal conductive pad. When the electrical element is configured on the conductive via array substrate through the upper signal conductive pad or the lower signal conductive pad, the floating conductive via is electrically insulated from the upper conductive layer and the lower conductive layer to be electrically floating, so that the impedance of the electronic device can be matched with the electrical element, the signal reflection amount in the signal transmission process can be reduced, and the signal distortion and attenuation can be further reduced.

The foregoing description of the invention and the following description of embodiments are provided to illustrate and explain the spirit and principles of the invention and to provide a further explanation of the invention as claimed.

Drawings

FIG. 1 is a schematic perspective view of an electronic device with a conductive via array substrate according to an embodiment of the invention;

FIG. 2 is a schematic side cross-sectional view of the electronic device of FIG. 1 with a conductive via array substrate;

FIG. 3 is a schematic side view of an electronic device with a conductive via array substrate according to another embodiment of the invention;

FIG. 4 is a schematic side view of an electronic device with a conductive via array substrate according to another embodiment of the invention;

FIG. 5 is a schematic side view of an electronic device with a conductive via array substrate according to another embodiment of the invention;

FIG. 6 is a schematic top view of an electronic device with a conductive via array substrate according to another embodiment of the invention;

FIG. 7 is a schematic top view of an electronic device with a conductive via array substrate according to another embodiment of the invention;

FIG. 8 is a schematic top view of an electronic device with a conductive via array substrate according to another embodiment of the invention;

FIG. 9 is a schematic top view of an electronic device with a conductive via array substrate according to another embodiment of the invention;

fig. 10 is a schematic top view of an electronic device with a conductive via array substrate according to another embodiment of the invention.

Symbol description

1,2,3,4, 5a,6,7,8: electronic device

10,20,30,40,50,60,70,80: conductive via array substrate

100 core layer

101,201,301,401,501,601,701,801 upper surface

102,202,302,402: lower surface

11,21,31,41,51,61,71,81: inner layer conductive vias

111,211,311,411,511,611,711,811 grounding conductive vias

112,212,312,412,512,612,712,812 Signal conductive vias

113,213,313,413,513,613,713,813 Floating conductive vias

12,22,32,42,52,62,72,82: upper conductive layer

120,220,320,420,520,620,720,820 upper hollowed-out part

121,221,321,421,521,621,721,821 an upper ground conductive trace

122,222,322,422a,422b,522,622,722,822: upper signal conductive pad

13,23,33,43 lower conductive layer

130,230,330,430: lower hollowed-out portion

131,231,331,431 lower ground conductive trace

132,232,332,432a,432b lower signal conductive pad

24,34 upper outer laminate

241,341 upper outer layer conductive via

25,35 upper external contact

36 lower outer laminate

361 lower outer conductive via

37 lower external contact

91 chip

92 solder

Center point C

Detailed Description

The detailed features and advantages of the embodiments of the present invention will be set forth in the detailed description that follows, so that those skilled in the art will readily understand the technical disclosure of the embodiments of the present invention and practice the same, and will readily understand the objects and advantages associated with the present invention by those skilled in the art based on the disclosure, claims, and drawings herein. The following examples are presented to illustrate the aspects of the invention in further detail, but are not intended to limit the scope of the invention in any way.

In the present specification, the dimensions, proportions, angles and the like may be exaggerated for the purpose of explanation, but the present invention is not limited thereto. Various modifications are possible without departing from the gist of the present invention. The vertical and horizontal directions mentioned in the description of the embodiments and the drawings are for illustration, not for limitation of the present invention.

Please refer to fig. 1 and 2. Fig. 1 is a schematic perspective view of an electronic device with a conductive via array substrate according to an embodiment of the invention. Fig. 2 is a schematic side view of the electronic device with the array substrate of fig. 1.

As shown in fig. 1 and 2, in the present embodiment, an electronic device 1 with a conductive via array substrate includes a conductive via array substrate 10, an upper conductive layer 12 and a lower conductive layer 13. The conductive via array substrate 10 includes a core layer 100 and a plurality of inner conductive vias 11. The core layer 100 is made of a semiconductor and a non-conductive material. Specifically, the material of the core layer 100 is selected from silicon, gallium, germanium, gallium nitride and epoxy. The plurality of inner layer conductive vias 11 extend through the core layer 100 and are arranged in a rectangular array. Each inner conductive via 11 is solid. The outer diameter of each inner layer conductive via 11 is 5 to 100 μm. The center-to-center spacing of adjacent ones of the plurality of inner-layer conductive vias 11 is on the order of microns. The inner conductive via 11 includes a plurality of ground conductive vias 111, a plurality of signal conductive vias 112, and a plurality of floating conductive vias 113. The floating conductive via 113 is electrically insulated from the upper conductive layer 12 and the lower conductive layer 13 to be electrically floating.

The conductive via array substrate 10 has an upper surface 101 and a lower surface 102. The upper conductive layer 12 includes an upper ground conductive trace 121 and an upper signal conductive pad 122. The upper ground conductive trace 121 is disposed on the upper surface 101. The upper ground conductive trace 121 is electrically connected to the plurality of ground conductive vias 111. The upper ground trace 121 has an upper hollow portion 120. The upper hollowed-out portion 120 exposes a portion of the upper surface 101. In other words, the upper hollowed-out portion 120 does not cover part of the upper surface 101. The upper signal conductive pad 122 is disposed on the upper surface 101 exposed by the upper hollow portion 120. In other words, the upper signal conductive pad 122 is disposed on the upper surface 101 of the portion not covered by the upper hollow portion 120. The upper signal conductive pads 122 are electrically connected to the plurality of signal conductive vias 112 in a one-to-many manner. In other words, the upper signal conductive pad 122 is electrically connected to at least two signal conductive vias 112. The upper signal conductive pad 122 and the upper ground conductive trace 121 are spaced apart from each other so that the upper signal conductive pad 122 is electrically isolated from the upper ground conductive trace 121.

The lower conductive layer 13 includes a lower ground conductive trace 131 and a lower signal conductive pad 132. The lower ground conductive trace 131 is disposed on the lower surface 102. The lower ground conductive trace 131 is electrically connected to the plurality of ground conductive vias 111. The lower ground conductive trace 131 has a lower hollowed-out portion 130. The lower hollowed-out portion 130 exposes a portion of the lower surface 102. The lower signal conductive pad 132 is disposed on the lower surface 102 exposed by the lower hollow portion 130. The lower signal conductive pads 132 are electrically connected to the plurality of signal conductive vias 112 in a one-to-many manner. The lower signal conductive pad 132 and the lower ground conductive trace 131 are spaced apart from each other, so the lower signal conductive pad 132 is electrically insulated from the lower ground conductive trace 131.

In the present embodiment, the upper and lower hollowed-out portions 120 and 130 expose the floating conductive via 113. In other words, the upper and lower hollowed-out portions 120 and 130 do not cover the floating conductive via 113. The number and density of floating conductive vias 113 affects the impedance of the signal as it propagates through the upper signal conductive pad 122, the signal conductive via 112, and the lower signal conductive pad 132.

In this embodiment, the shape of the upper hollowed-out portion 120 is the same as the shape of the lower hollowed-out portion 130, and is square. Moreover, the size of the upper hollowed-out portion 120 is the same as the size of the lower hollowed-out portion 130. All of the ground conductive vias 111 are electrically connected to the upper ground conductive trace 121 and the lower ground conductive trace 131. But is not limited thereto. In other embodiments, the shape or size of the upper hollow portion 120 and the shape or size of the lower hollow portion 130 may be designed differently for impedance matching. Furthermore, in other embodiments, the ground conductive via 111 may also be electrically connected to only the upper ground conductive trace 121 or only the lower ground conductive trace 131.

In the present embodiment, the shape of the upper signal conductive pad 122 and the shape of the lower signal conductive pad 132 are the same, and are all circular. Also, the size of the upper signal conductive pad 122 is the same as the size of the lower signal conductive pad 132. All of the signal conductive vias 112 are electrically connected to the upper signal conductive pad 122 and the lower signal conductive pad 132.

In the present embodiment, as the size of the upper signal conductive pad 122 is smaller and the size of the upper hollowed-out portion 120 is larger, the equivalent impedance near the upper signal conductive pad 122 is larger. When the size of the upper signal conductive pad 122 is larger and the size of the upper hollowed-out portion 120 is smaller, the equivalent impedance near the upper signal conductive pad 122 is smaller.

Moreover, as the size of the lower signal conductive pad 132 is smaller and the size of the lower hollowed-out portion 130 is larger, the equivalent impedance near the lower signal conductive pad 132 is larger. When the size of the lower signal conductive pad 132 is larger and the size of the lower hollowed-out portion 130 is smaller, the equivalent impedance near the lower signal conductive pad 132 is smaller.

Furthermore, in other embodiments, a plurality of electronic devices 1 having conductive via array substrates may be arranged in an array and connected to each other. Adjacent electronic devices 1 with conductive via array substrates may share an upper ground conductive trace 121 with each other and may share a lower ground conductive trace 131 with each other.

Please refer to fig. 3. Fig. 3 is a schematic side view of an electronic device with a conductive via array substrate according to another embodiment of the invention.

As shown in fig. 3, in the present embodiment, the electronic device 2 with a conductive via array substrate includes a conductive via array substrate 20, an upper conductive layer 22, a lower conductive layer 23, an upper outer layer 24, and a plurality of upper external contacts 25. The conductive via array substrate 20 has a plurality of inner conductive vias 21. The inner layer conductive via 21 includes a plurality of ground conductive vias 211, a plurality of signal conductive vias 212, and a plurality of floating conductive vias 213. The floating conductive via 213 is electrically insulated from the upper conductive layer 22 and the lower conductive layer 23 to be electrically floating.

The conductive via array substrate 20 has an upper surface 201 and a lower surface 202. The upper conductive layer 22 includes an upper ground conductive trace 221 and a plurality of upper signal conductive pads 222. The upper ground conductive trace 221 is disposed on the upper surface 201. The upper ground conductive trace 221 is electrically connected to the plurality of ground conductive vias 211. The upper ground conductive trace 221 has a plurality of upper hollowed-out portions 220 to form a grid shape. The number of the plurality of upper signal conductive pads 222 is smaller than the number of the plurality of upper hollowed-out portions 220. Each upper signal conductive pad 222 is disposed on the upper surface 201 exposed by each upper hollow portion 220. Therefore, the upper surface 201 exposed by at least one of the plurality of upper hollowed-out portions 220 lacks the upper signal conductive pad 222. Each upper signal conductive pad 222 is electrically connected to the plurality of signal conductive vias 212 in a one-to-many fashion. The upper signal conductive pad 222 and the upper ground conductive trace 221 are spaced apart from each other so that the upper signal conductive pad 222 is electrically isolated from the upper ground conductive trace 221. The upper hollowed-out portion 220 exposes the floating conductive via 213.

The lower conductive layer 23 includes a lower ground conductive trace 231 and a plurality of lower signal conductive pads 232. The lower ground conductive trace 231 is disposed on the lower surface 202. The lower ground conductive trace 231 is electrically connected to the plurality of ground conductive vias 211. The lower ground conductive trace 231 has a plurality of lower hollowed-out portions 230 to form a grid shape. The number of the plurality of lower signal conductive pads 232 is the same as the number of the plurality of lower hollowed-out portions 230. Each of the lower signal conductive pads 232 is disposed on the lower surface 202 exposed by each of the lower hollow portions 230. Each of the lower signal conductive pads 232 is electrically connected to the plurality of signal conductive vias 212 in a one-to-many manner. The lower signal conductive pad 232 and the lower ground conductive trace 231 are spaced apart from each other, so the lower signal conductive pad 232 is electrically insulated from the lower ground conductive trace 231. The lower hollowed-out portion 230 exposes the floating conductive via 213.

In this embodiment, the shape and size of the upper hollowed-out portion 220 are the same as the shape and size of the lower hollowed-out portion 230. All of the ground conductive vias 211 are electrically connected to the upper ground conductive trace 221 and the lower ground conductive trace 231. The shape and size of the upper signal conductive pad 222 is different from the shape and size of the lower signal conductive pad 232. Of the plurality of signal conductive vias 212, some of the signal conductive vias 212 are electrically connected to both the upper signal conductive pad 222 and the lower signal conductive pad 232, and other of the signal conductive vias 212 are electrically connected to only the lower signal conductive pad 232.

In this embodiment, the upper outer layer 24 has a plurality of upper outer layer conductive vias 241. The upper outer layer plate 24 covers the upper conductive layer 22 and the conductive via array substrate 20. Each upper outer layer conductive via 241 is electrically connected to each upper signal conductive pad 222. A plurality of upper outer contacts 25 are disposed on the upper outer plate 24. The plurality of upper external contacts 25 are electrically connected to the plurality of upper outer conductive vias 241.

As shown in fig. 3, the chip 91 may be electrically connected to the upper external contacts 25 of the electronic device 2 via solder 92. The lower signal conductive pads 232 of the electronic device 2 may be electrically connected to other electronic components via solder 92.

Please refer to fig. 4. Fig. 4 is a schematic side view of an electronic device with a conductive via array substrate according to another embodiment of the invention.

As shown in fig. 4, in the embodiment, the electronic device 3 with a conductive via array substrate includes a conductive via array substrate 30, an upper conductive layer 32, a lower conductive layer 33, an upper outer layer 34, a plurality of upper outer contacts 35, a lower outer layer 36 and a plurality of lower outer contacts 37. The conductive via array substrate 30 has a plurality of inner conductive vias 31. The inner conductive via 31 includes a plurality of ground conductive vias 311, a plurality of signal conductive vias 312, and a plurality of floating conductive vias 313. The floating conductive via 313 is electrically isolated from the upper conductive layer 32 and the lower conductive layer 33 to be electrically floating.

The conductive via array substrate 30 has an upper surface 301 and a lower surface 302. The upper conductive layer 32 includes an upper ground conductive trace 321 and a plurality of upper signal conductive pads 322. The upper ground conductive trace 321 is disposed on the upper surface 301. The upper ground conductive trace 321 is electrically connected to the plurality of ground conductive vias 311. The upper ground conductive trace 321 has a plurality of upper hollowed-out portions 320 to form a grid shape. The number of the plurality of upper signal conductive pads 322 is three times the number of the plurality of upper hollowed-out portions 320. Three upper signal conductive pads 322 are disposed on the upper surface 301 exposed by one upper hollow portion 320. Each upper signal conductive pad 322 is electrically connected to each signal conductive via 312 in a one-to-one manner. The upper signal conductive pad 322 and the upper ground conductive trace 321 are spaced apart from each other, so the upper signal conductive pad 322 is electrically insulated from the upper ground conductive trace 321. The upper hollowed-out portion 320 exposes the floating conductive via 313.

The lower conductive layer 33 includes a lower ground conductive trace 331 and a plurality of lower signal conductive pads 332. The lower ground conductive trace 331 is disposed on the lower surface 302. The lower ground conductive trace 331 is electrically connected to the plurality of ground conductive vias 311. The lower ground conductive trace 331 has a plurality of lower hollowed-out portions 330 and has a grid shape. The number of the plurality of lower signal conductive pads 332 is the same as the number of the plurality of lower hollowed-out portions 330. Each of the lower signal conductive pads 332 is disposed on the lower surface 302 exposed by each of the lower hollowed-out portions 330. The respective lower signal conductive pads 332 are electrically connected to the respective signal conductive vias 312 in a one-to-one manner. The lower signal conductive pad 332 and the lower ground conductive trace 331 are spaced apart from each other so that the lower signal conductive pad 332 is electrically isolated from the lower ground conductive trace 331. The lower hollowed-out portion 330 exposes the floating conductive via 313.

In this embodiment, the shape and size of the upper hollow portion 320 are the same as those of the lower hollow portion 330. All of the ground conductive vias 311 are electrically connected to the upper ground conductive trace 321 and the lower ground conductive trace 331. The number of upper signal conductive pads 322 is different from the number of lower signal conductive pads 332. Of the plurality of signal conductive vias 312, some signal conductive vias 312 are electrically connected to both the upper signal conductive pad 322 and the lower signal conductive pad 332, and other signal conductive vias 312 are electrically connected to only the upper signal conductive pad 322.

In the present embodiment, the upper outer layer 34 has a plurality of upper outer layer conductive vias 341. The upper outer layer 34 covers the upper conductive layer 32 and the conductive via array substrate 30. Each upper outer conductive via 341 is electrically connected to each upper signal conductive pad 322. A plurality of upper outer pair of contacts 35 are provided on the upper outer laminate 34. The plurality of upper external contacts 35 are electrically connected to the plurality of upper outer conductive vias 341.

The lower outer layer plate 36 has a plurality of lower outer layer conductive vias 361. The lower outer layer plate 36 covers the lower conductive layer 33 and the conductive via array substrate 30. Each lower outer conductive via 361 is electrically connected to each lower signal conductive pad 332. A plurality of lower outer pair of contacts 37 are provided on the lower outer plate 36. Each lower pair of external contacts 37 is electrically connected to each lower outer conductive via 361.

As shown in fig. 4, the chip 91 may be electrically connected to the upper external contacts 35 of the electronic device 3 via solder 92. The lower pair of external contacts 37 of the electronic device 3 may be electrically connected to other electronic components via solder 92.

Please refer to fig. 5. Fig. 5 is a schematic side view of an electronic device with a conductive via array substrate according to another embodiment of the invention.

As shown in fig. 5, in the present embodiment, the electronic device 4 with a conductive via array substrate includes a conductive via array substrate 40, an upper conductive layer 42 and a lower conductive layer 43. The conductive via array substrate 40 has a plurality of inner conductive vias 41. The inner layer conductive via 41 includes a plurality of ground conductive vias 411, a plurality of signal conductive vias 412, and a plurality of floating conductive vias 413. The floating conductive via 413 is electrically isolated from the upper conductive layer 42 and the lower conductive layer 43 to be electrically floating.

The conductive via array substrate 40 has an upper surface 401 and a lower surface 402. The upper conductive layer 42 includes an upper ground conductive trace 421, an upper signal conductive pad 422a, and an upper signal conductive pad 422b. The upper ground conductive trace 421 is disposed on the upper surface 401. The upper ground conductive trace 421 is electrically connected to the plurality of ground conductive vias 411. The upper ground conductive trace 421 has a plurality of upper hollowed-out portions 420 to form a grid shape. The upper signal conductive pad 422a and the upper signal conductive pad 422b have a variety of different sizes or shapes. The upper signal conductive pad 422a is disposed on the upper surface 401 exposed by the upper hollow portion 420. The upper signal conductive pads 422a are electrically connected to one signal conductive via 412 in a one-to-one manner. The upper signal conductive pad 422b is disposed on the upper surface 401 exposed by the other upper hollow portion 420. The upper signal conductive pad 422b is electrically connected to the plurality of signal conductive vias 412 in a one-to-many manner. The upper signal conductive pad 422a and the upper signal conductive pad 422b are spaced apart from the upper ground conductive trace 421, so that the upper signal conductive pad 422a and the upper signal conductive pad 422b are electrically isolated from the upper ground conductive trace 421. The upper hollowed-out portion 420 exposes the floating conductive via 413.

The lower conductive layer 43 includes a lower ground conductive trace 431, a lower signal conductive pad 432a, and a lower signal conductive pad 432b. The lower ground conductive trace 431 is disposed on the lower surface 402. The lower ground conductive trace 431 is electrically connected to the plurality of ground conductive vias 411. The lower ground conductive trace 431 has a plurality of lower hollowed-out portions 430 to form a grid shape. The lower signal conductive pad 432a and the lower signal conductive pad 432b have a variety of different sizes or shapes. The lower signal conductive pad 432a is disposed on the lower surface 402 exposed by the lower hollow portion 430. The lower signal conductive pads 432a are electrically connected to one signal conductive via 412 in a one-to-one manner. The lower signal conductive pad 432b is disposed on the lower surface 402 exposed by the other lower hollow portion 430. The lower signal conductive pads 432b are electrically connected to the plurality of signal conductive vias 412 in a one-to-many manner. The lower signal conductive pad 432a and the lower signal conductive pad 432b are spaced apart from the lower ground conductive trace 431 such that the lower signal conductive pad 432a and the lower signal conductive pad 432b are electrically isolated from the lower ground conductive trace 431. The lower hollowed-out portion 430 exposes the floating conductive via 413.

In this embodiment, the shape and size of the upper hollow portion 420 are the same as those of the lower hollow portion 430. All of the ground conductive vias 411 are electrically connected to the upper ground conductive trace 421 and the lower ground conductive trace 431. The shape or size of the upper signal conductive pad 422b is different from the shape or size of the lower signal conductive pad 432b. Of the plurality of signal conductive vias 412, one signal conductive via 412 is electrically connected to both the upper signal conductive pad 422a and the lower signal conductive pad 432a, some signal conductive vias 412 are electrically connected to both the upper signal conductive pad 422b and the lower signal conductive pad 432b, and other signal conductive vias 412 are electrically connected to only the upper signal conductive pad 422b.

The embodiments of fig. 6-10 all describe electronic devices that are symmetrical up and down. The electronic device is described below by a top view, and a description of lower side elements of the electronic device is omitted.

Please refer to fig. 6. Fig. 6 is a schematic top view of an electronic device with a conductive via array substrate according to another embodiment of the invention.

As shown in fig. 6, in the present embodiment, the electronic device 5 with a conductive via array substrate includes a conductive via array substrate 50 and an upper conductive layer 52. The conductive via array substrate 50 has a plurality of inner conductive vias 51. The inner conductive via 51 includes a plurality of ground conductive vias 511, a plurality of signal conductive vias 512, and a plurality of floating conductive vias 513. The floating conductive via 513 is electrically isolated from the upper conductive layer 52 to be electrically floating.

The upper conductive layer 52 includes an upper ground conductive trace 521 and an upper signal conductive pad 522. The upper ground conductive trace 521 is disposed on the upper surface 501 of the conductive via array substrate 50. The upper ground conductive trace 521 is electrically connected to the plurality of ground conductive vias 511. The upper signal conductive pad 522 is disposed on the upper surface 501 exposed by the upper hollow portion 520 of the upper ground conductive trace 521. The upper signal conductive pads 522 are electrically connected to the plurality of signal conductive vias 512 in a one-to-many manner. The upper signal conductive pad 522 and the upper ground conductive trace 521 are spaced apart from each other so that the upper signal conductive pad 522 is electrically isolated from the upper ground conductive trace 521. The upper hollowed-out portion 520 exposes the floating conductive via 513.

In this embodiment, the upper hollowed portion 520 has a regular hexagon shape, and the upper signal conductive pad 522 has a circular shape. The upper hollow portion 520 has a center point C. The inner conductive vias 51 are arranged radially about the center point C and pass through the centers of the sides of the regular hexagon.

Please refer to fig. 7. Fig. 7 is a schematic top view of an electronic device with a conductive via array substrate according to another embodiment of the invention.

As shown in fig. 7, in the present embodiment, the electronic device 5a with the conductive via array substrate includes a plurality of electronic devices 5 shown in fig. 6. In the present embodiment, the electronic devices 5 are arranged in a honeycomb-like manner and connected to each other. Adjacent electronic devices 5 may share an upper ground conductive trace 521 with each other.

Please refer to fig. 8. Fig. 8 is a schematic top view of an electronic device with a conductive via array substrate according to another embodiment of the invention.

As shown in fig. 8, in the present embodiment, the electronic device 6 with a conductive via array substrate includes a conductive via array substrate 60 and an upper conductive layer 62. The conductive via array substrate 60 has a plurality of inner conductive vias 61. The inner conductive via 61 includes a plurality of ground conductive vias 611, a plurality of signal conductive vias 612, and a plurality of floating conductive vias 613. The floating conductive via 613 is electrically isolated from the upper conductive layer 62 to be electrically floating.

The upper conductive layer 62 includes an upper ground conductive trace 621 and an upper signal conductive pad 622. The upper ground conductive trace 621 is disposed on the upper surface 601 of the conductive via array substrate 60. The upper ground conductive trace 621 is electrically connected to the plurality of ground conductive vias 611. The upper signal conductive pad 622 is disposed on the upper surface 601 exposed by the upper hollowed-out portion 620 of the upper ground conductive trace 621. The upper signal conductive pad 622 is electrically connected to the plurality of signal conductive vias 612 in a one-to-many fashion. The upper signal conductive pad 622 and the upper ground conductive trace 621 are spaced apart from each other so that the upper signal conductive pad 622 is electrically isolated from the upper ground conductive trace 621. The upper hollowed-out portion 620 exposes the floating conductive via 613.

In this embodiment, the upper hollowed-out portion 620 has a regular hexagon shape, and the upper signal conductive pad 622 has a circular shape. The upper hollow 620 has a center point C. The inner conductive vias 61 are arranged radially about the center point C and pass through the end points of the corners of the regular hexagon.

Please refer to fig. 9. Fig. 9 is a schematic top view of an electronic device with a conductive via array substrate according to another embodiment of the invention.

As shown in fig. 9, in the present embodiment, the electronic device 7 with a conductive via array substrate includes a conductive via array substrate 70 and an upper conductive layer 72. The conductive via array substrate 70 has a plurality of inner conductive vias 71. The inner conductive via 71 includes a plurality of ground conductive vias 711, a plurality of signal conductive vias 712, and a plurality of floating conductive vias 713. The floating conductive via 713 is electrically isolated from the upper conductive layer 72 to be electrically floating.

The upper conductive layer 72 includes an upper ground conductive trace 721 and an upper signal conductive pad 722. The upper ground conductive trace 721 is disposed on the upper surface 701 of the conductive via array substrate 70. The upper ground conductive trace 721 is electrically connected to the plurality of ground conductive vias 711. The upper signal conductive pad 722 is disposed on the upper surface 701 exposed by the upper hollow portion 720 of the upper ground conductive trace 721. The upper signal conductive pads 722 are electrically connected to the plurality of signal conductive vias 712 in a one-to-many fashion. The upper signal conductive pad 722 and the upper ground conductive trace 721 are spaced apart from each other so that the upper signal conductive pad 722 is electrically isolated from the upper ground conductive trace 721. The upper hollowed-out portion 720 exposes the floating conductive via 713.

In this embodiment, the upper hollowed portion 720 has a regular hexagon shape, and the upper signal conductive pad 722 has a circular shape. The inner conductive vias 71 are arranged in a triangular array.

Please refer to fig. 10. Fig. 10 is a schematic top view of an electronic device with a conductive via array substrate according to another embodiment of the invention.

As shown in fig. 10, in the present embodiment, the electronic device 8 with a conductive via array substrate includes a conductive via array substrate 80 and an upper conductive layer 82. The conductive via array substrate 80 has a plurality of inner conductive vias 81. The inner conductive via 81 includes a plurality of ground conductive vias 811, a plurality of signal conductive vias 812, and a plurality of floating conductive vias 813. The floating conductive via 813 is electrically isolated from the upper conductive layer 82 to be electrically floating.

The upper conductive layer 82 includes an upper ground conductive trace 821 and two upper signal conductive pads 822. The upper ground conductive trace 821 is disposed on the upper surface 801 of the conductive via array substrate 80. The upper ground conductive trace 821 is electrically connected to a plurality of ground conductive vias 811. The two upper signal conductive pads 822 are disposed on the upper surface 801 exposed by an upper hollowed portion 820 of the upper ground conductive trace 821. The upper hollowed-out portion 820 may be rectangular in shape. Each of the upper signal conductive pads 822 is electrically connected to the plurality of signal conductive vias 812 in a one-to-many manner. The upper signal conductive pad 822 and the upper ground conductive trace 821 are spaced apart from each other so that the upper signal conductive pad 822 is electrically isolated from the upper ground conductive trace 821. The upper hollowed-out portion 820 exposes the floating conductive via 813. Two upper signal pads 822 may be used to transmit differential signals.

In summary, in the electronic device with the array substrate having the conductive vias according to the embodiment of the invention, the signals can be transmitted in the vertical direction through the upper signal conductive pad, the signal conductive via and the lower signal conductive pad. When the electrical element is configured on the conductive via array substrate through the upper signal conductive pad or the lower signal conductive pad, the floating conductive via is electrically insulated from the upper conductive layer and the lower conductive layer to be electrically floating, so that the impedance of the electronic device can be matched with the electrical element, the signal reflection amount in the signal transmission process can be reduced, and the signal distortion and attenuation can be further reduced.

Claims (20)

1. An electronic device with a conductive via array substrate, comprising:

the circuit comprises a conductive through hole array substrate, a plurality of floating conductive through holes and a plurality of insulating layers, wherein the conductive through hole array substrate is provided with a plurality of inner-layer conductive through holes, the inner-layer conductive through holes comprise a plurality of grounding conductive through holes, at least one signal conductive through hole and a plurality of floating conductive through holes, and the conductive through hole array substrate is provided with an upper surface and a lower surface;

an upper conductive layer comprising:

the upper grounding conductive trace is arranged on the upper surface and is electrically connected with at least a plurality of grounding conductive through holes, and the upper grounding conductive trace is provided with at least one upper hollowed-out part which exposes part of the upper surface; and

at least one upper signal conducting pad arranged on the upper surface exposed by the at least one upper hollowed-out part, wherein the at least one upper signal conducting pad is electrically connected with the at least one signal conducting through hole; and

a lower conductive layer comprising:

the lower grounding conductive trace is arranged on the lower surface and is electrically connected with at least a plurality of grounding conductive through holes, and the lower grounding conductive trace is provided with at least one lower hollowed-out part which exposes part of the lower surface; and

at least one lower signal conducting pad arranged on the lower surface exposed by the at least one lower hollow part, and electrically connected with the at least one signal conducting through hole; wherein the method comprises the steps of

The floating conductive vias are electrically isolated from the upper conductive layer and the lower conductive layer to be electrically floating.

2. The electronic device of claim 1, wherein the number of the at least one upper hollowed-out portion, the number of the at least one lower hollowed-out portion and the at least one lower signal conductive pad are respectively plural, and the upper surface exposed by at least one of the upper hollowed-out portions lacks the at least one upper signal conductive pad.

3. The electronic device of claim 1, further comprising an upper outer layer plate having at least one upper outer layer conductive via, the upper outer layer plate covering the upper conductive layer and the conductive via array substrate, the at least one upper outer layer conductive via electrically connected to the at least one upper signal conductive pad.

4. The electronic device of claim 3, further comprising a lower outer layer plate having at least one lower outer layer conductive via, the lower outer layer plate covering the lower conductive layer and the conductive via array substrate, the at least one lower outer layer conductive via electrically connected to the at least one lower signal conductive pad.

5. The electronic device of claim 4, further comprising at least one upper outer contact disposed on the upper outer layer plate, the at least one upper outer contact electrically connected to the at least one upper outer layer conductive via, and at least one lower outer contact disposed on the lower outer layer plate, the at least one lower outer contact electrically connected to the at least one lower outer layer conductive via.

6. The electronic device of claim 1, wherein the shape and size of the at least one upper hollowed-out portion is the same as the shape and size of the at least one lower hollowed-out portion, and all of the ground conductive vias are electrically connected to the upper ground conductive trace and the lower ground conductive trace.

7. The electronic device of claim 1, wherein the shape and size of the at least one upper signal conductive pad is the same as the shape and size of the at least one lower signal conductive pad, the number of the at least one signal conductive via is a plurality of signal conductive vias, and all of the signal conductive vias electrically connect the at least one upper signal conductive pad and the at least one lower signal conductive pad.

8. The electronic device of claim 1, wherein the shape or size of the at least one upper signal conductive pad is different from the shape or size of the at least one lower signal conductive pad, the number of the at least one signal conductive via is plural, at least one of the signal conductive vias is electrically connected to the at least one upper signal conductive pad and the at least one lower signal conductive pad at the same time, and at least one other of the signal conductive vias is electrically connected to only one of the at least one upper signal conductive pad and the at least one lower signal conductive pad.

9. The electronic device of claim 1, wherein the number of the at least one upper signal conductive pads, the number of the at least one upper hollow portion, the number of the at least one lower signal conductive pads, and the number of the at least one lower hollow portion are all plural, the upper signal conductive pads are respectively disposed on the upper surfaces exposed by the upper hollow portions, the upper signal conductive pads have plural different sizes or shapes, the lower signal conductive pads are respectively disposed on the lower surfaces exposed by the lower hollow portions, and the lower signal conductive pads have plural different sizes or shapes.

10. The electronic device of claim 1, wherein the inner conductive vias are arranged in an array.

11. The electronic device of claim 1, wherein the shape of the at least one upper hollowed-out portion or the shape of the at least one lower hollowed-out portion is regular hexagon and has a center point, and the inner conductive vias are radially arranged with the center point as a center and pass through the center of each side of the regular hexagon or each corner of the regular hexagon.

12. The electronic device of claim 1, wherein the number of the at least one upper signal conductive pads, the number of the at least one lower signal conductive pads and the number of the at least one signal conductive vias are all plural, the number of the at least one upper hollowed-out portion and the number of the at least one lower hollowed-out portion are all one, the upper signal conductive pads are disposed on the upper surface exposed by the upper hollowed-out portion, the lower signal conductive pads are disposed on the lower surface exposed by the lower hollowed-out portion, and each upper signal conductive pad is electrically connected to each lower signal conductive pad through at least one of the signal conductive vias.

13. The electronic device of claim 1, wherein the shape of the at least one upper hollowed-out portion and the shape of the at least one lower hollowed-out portion are rectangular or regular hexagonal.

14. The electronic device of claim 1, wherein the shape of the at least one upper signal conductive pad and the shape of the at least one lower signal conductive pad are circular.

15. The electronic device of claim 1, wherein each of the inner conductive vias is solid.

16. The electronic device of claim 1, wherein the at least one signal conductive via is plural in number, and the at least one upper signal conductive pad or the at least one lower signal conductive pad is electrically connected to the signal conductive vias in one-to-plural fashion.

17. The electronic device of claim 1, wherein each of the inner conductive vias has an outer diameter of 5-100 microns.

18. The electronic device of claim 1, wherein the center-to-center spacing of the inner conductive vias is on the order of microns.

19. The electronic device of claim 1, wherein the core layer of the conductive via array substrate is made of a material selected from the group consisting of a semiconductor and a non-conductive material.

20. The electronic device of claim 1, wherein the core layer of the conductive via array substrate is made of a material selected from the group consisting of silicon, gallium, germanium, gallium nitride and epoxy.

Images