CN116264211A - Semiconductor package and method of manufacturing the same - Google Patents

Semiconductor package and method of manufacturing the same Download PDF

Info

Publication number
CN116264211A
CN116264211A CN202111646276.3A CN202111646276A CN116264211A CN 116264211 A CN116264211 A CN 116264211A CN 202111646276 A CN202111646276 A CN 202111646276A CN 116264211 A CN116264211 A CN 116264211A
Authority
CN
China
Prior art keywords
chip
layer
semiconductor package
stack
electrically connected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111646276.3A
Other languages
Chinese (zh)
Inventor
陈柏老
卢仲德
吴承德
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Powerchip Technology Corp
Original Assignee
Powerchip Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powerchip Technology Corp filed Critical Powerchip Technology Corp
Publication of CN116264211A publication Critical patent/CN116264211A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

The invention discloses a semiconductor package and a manufacturing method thereof, wherein the semiconductor package comprises a chip stacking structure. The chip stacking structure comprises a chip stack, a molding through hole and a connecting terminal. The chip stack includes a plurality of chip structures stacked. Each chip structure comprises a chip, a supporting layer and a rewiring layer. The supporting layer is arranged on the side edge of the chip. The rewiring layer is arranged on the chip and the supporting layer. The rewiring layer is electrically connected to the chip. The molded via is disposed in at least a portion of the plurality of rewiring layers and at least a portion of the plurality of support layers. The molded via is electrically connected to the plurality of rewiring layers. The connection terminal is electrically connected to the molded through hole.

Description

Semiconductor package and method of manufacturing the same
Technical Field
The present invention relates to a semiconductor structure and a method of manufacturing the same, and more particularly, to a semiconductor package and a method of manufacturing the same.
Background
In the packaging process of integrated circuits, semiconductor chips may be stacked to form a three-dimensional (3D) semiconductor package. However, how to further prevent the chip from being damaged in the manufacturing process, reduce the manufacturing cost, and improve the electrical performance of the semiconductor package is a goal of continuous efforts at present.
Disclosure of Invention
The invention provides a semiconductor package and a manufacturing method thereof, which can prevent a chip from being damaged in a manufacturing process, reduce manufacturing cost and improve electrical performance of the semiconductor package.
The invention provides a semiconductor package, which comprises a chip stacking structure. The chip stacking structure includes a chip stack, a through mold via (through mold via), and a connection terminal. The chip stack includes a plurality of chip structures stacked. Each chip structure includes a chip, a support layer, and a redistribution layer (redistribution layer, RDL). The supporting layer is arranged on the side edge of the chip. The rewiring layer is arranged on the chip and the supporting layer. The rewiring layer is electrically connected to the chip. The molded via is disposed in at least a portion of the plurality of rewiring layers and at least a portion of the plurality of support layers. The molded via is electrically connected to the plurality of rewiring layers. The connection terminal is electrically connected to the molded through hole.
In an embodiment of the invention, in the semiconductor package, the supporting layer may surround the chip.
In accordance with an embodiment of the present invention, in the semiconductor package described above, the molding via may penetrate at least a portion of the plurality of redistribution layers and at least a portion of the plurality of support layers.
In an embodiment of the invention, the semiconductor package further includes a substrate and an encapsulant. The chip stacking structure is arranged on the substrate. The chip stacking structure can be electrically connected to the substrate through the connection terminal. The encapsulant covers the chip stack.
The invention provides a manufacturing method of a semiconductor package, which comprises the following steps. Forming a chip stacking structure. The method for forming the chip stack structure may include the following steps. Forming a chip stack. The chip stack includes a plurality of chip structures stacked. Each chip structure comprises a chip, a supporting layer and a rewiring layer. The supporting layer is arranged on the side edge of the chip. The rewiring layer is arranged on the chip and the supporting layer. The rewiring layer is electrically connected to the chip. A molded via is formed in at least a portion of the plurality of redistribution layers and at least a portion of the plurality of support layers. The molded via is electrically connected to the plurality of rewiring layers. Connection terminals are formed on the molded through holes. The connection terminal is electrically connected to the molded through hole.
In accordance with an embodiment of the present invention, in the method for manufacturing a semiconductor package, the method for forming a chip structure may include the following steps. At least one chip is disposed on a first carrier. The chip may have opposite first and second sides. The first surface of the chip can face the first carrier. A layer of support material is formed overlying the chip. And removing part of the supporting material layer and part of the chip to form a first chip layer and thinning the chip. The first chip layer may include a chip and a supporting layer. The first chip layer is transferred from the first carrier plate to the second carrier plate. The second surface of the chip can face the second carrier. A redistribution layer is formed on a first side of the first chip layer to form a second chip layer, wherein the second chip layer may include at least one chip structure.
According to an embodiment of the present invention, the method for manufacturing a semiconductor package further includes the following steps. And separating the second chip layer from the second carrier plate. The plurality of second chip layers are stacked to form a first chip layer stack. The first chip layer stack may include at least one chip stack.
In accordance with an embodiment of the present invention, the method for manufacturing a semiconductor package may further include the following steps. A molded via is formed in the first chip layer stack. Connection terminals are formed on the molded through holes, and a second chip layer stack is formed. The second chip layer stack may include at least one chip stack structure.
In accordance with an embodiment of the present invention, the method for manufacturing a semiconductor package may further include the following steps. And cutting and manufacturing the second chip layer stack.
In accordance with an embodiment of the present invention, the method for manufacturing a semiconductor package may further include the following steps. The chip stack structure is disposed on the substrate. The chip stacking structure can be electrically connected to the substrate through the connection terminal. An encapsulant covering the chip stack structure is formed.
Based on the above, in the semiconductor package and the manufacturing method thereof according to the present invention, the supporting layer can be used to support and protect the chip, so as to prevent the chip from being damaged during the manufacturing process. In addition, the stacked chips are electrically connected by molding the through holes, so that the wire bonding (wire bonding process) manufacturing process and the bump manufacturing process (bumping) can be reduced, and the manufacturing cost is further reduced. In addition, the stacked chips are electrically connected by the molding through holes, so that the circuit length can be shortened and the heterojunction can be reduced, and the electrical performance of the semiconductor package can be improved.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIGS. 1A-1K are schematic diagrams illustrating a manufacturing process of a semiconductor package according to some embodiments of the invention;
FIG. 2 is a schematic cross-sectional view of a semiconductor package according to other embodiments of the present invention;
FIG. 3 is a schematic cross-sectional view of a semiconductor package according to other embodiments of the present invention;
fig. 4 is a schematic cross-sectional view of a semiconductor package according to other embodiments of the present invention.
Symbol description
10,20,30,40 semiconductor package
100 substrate
102, pad
104,108,114 adhesive layer
106 supporting material layer
106a supporting layer
110 re-wiring layer
112 alignment mark
116 molding through holes
118 connecting terminal
120 substrate
122 connecting terminal
124 envelope body
C1, C2 carrier plate
CL1, CL2 chip layer
CS1 chip Structure
CS2 chip Stack
CS3 chip Stacking Structure
DB wafer cutter
S1, first side
S2 second surface
SL1, SL2 chip layer stack
Detailed Description
The following examples are set forth in detail in connection with the accompanying drawings, but are not intended to limit the scope of the invention. For ease of understanding, like components will be described with like reference numerals throughout the following description. Moreover, the drawings are for illustrative purposes only and are not drawn to scale. In addition, features in the perspective view, features in the top view, and features in the cross-section are not drawn to the same scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
Fig. 1A is a schematic perspective view of a stage of a method of manufacturing a semiconductor package according to some embodiments of the invention. Referring to fig. 1A, a wafer W may be diced into a plurality of chips 100. For example, the wafer W may be diced by the wafer dicing blade DB, but the invention is not limited thereto. In addition, the wafer W may be polished before dicing the wafer W, whereby the chip 100 may be thinned, and the size of the chip 100 may be reduced. In the present embodiment, the chip 100 may be a dynamic random access memory (dynamic random access memory, DRAM) chip, but the invention is not limited thereto. The chip 100 may have a first surface S1 and a second surface S2 opposite to each other. The first surface S1 and the second surface S2 may be one of the front surface and the back surface of the chip 100 and the other. In the present embodiment, the first surface S1 may be a front surface of the chip 100, and the second surface S2 may be a back surface of the chip. In addition, the chip 100 may have at least one pad (pad) 102 on the first surface S1. In the present embodiment, the number of the pads 102 is taken as a plurality of examples, but the number of the pads 102 is not limited to the number shown in the figure. As long as the number of pads 102 is at least one, and is within the scope of the present invention.
Fig. 1B is a schematic perspective view of a stage of a method of manufacturing a semiconductor package according to some embodiments of the invention. Referring to fig. 1B, at least one chip 100 may be disposed on a carrier C1. The first surface S1 (e.g., front surface) of the chip 100 may face the carrier C1. The chip 100 may be a good die (KGD). In some embodiments, the chip 100 is disposed on the carrier board C1, for example, by adhering the first surface S1 (e.g., front surface) of the chip 100 to the carrier board C1 through the adhesive layer 104. In addition, the carrier C1 may be a panel type (panel type) carrier or a wafer type (wafer type) carrier. In the present embodiment, the carrier board C1 is a panel type carrier board. In the present embodiment, the number of chips 100 provided on the carrier board C1 is exemplified by a plurality of chips, but the number of chips 100 provided on the carrier board C1 is not limited to the number shown in the figure. As long as the number of chips 100 provided on the carrier board C1 is at least one, i.e., it is within the scope of the present invention.
Fig. 1C is a schematic perspective view of a stage of a method of manufacturing a semiconductor package according to some embodiments of the invention. Referring to fig. 1C, a support material layer 106 covering the chip 100 may be formed. The material of the support material layer 106 is, for example, a molding compound (molding compound).
Fig. 1D is a schematic perspective view of a stage of a method of manufacturing a semiconductor package according to some embodiments of the invention. Referring to fig. 1D, a portion of the support material layer 106 and a portion of the chip 100 may be removed to form a chip layer CL1 and thin the chip 100. The chip layer CL1 may include the chip 100 and the supporting layer 106a. The method for removing the portion of the supporting material layer 106 and the portion of the chip 100 is, for example, performing a polishing process on the supporting material layer 106 and the chip 100. Since the supporting layer 106a can be used to support and protect the chip 100, the chip 100 is prevented from being damaged during the polishing process, and the chip 100 can be polished to a thinner thickness.
Fig. 1E is a schematic perspective view of a stage of a method of manufacturing a semiconductor package according to some embodiments of the invention. Referring to fig. 1E, the chip layer CL1 can be transferred from the carrier C1 to the carrier C2. The second surface S2 (e.g., the back surface) of the chip 100 may face the carrier C2. In some embodiments, the method of transferring the chip layer CL1 from the carrier C1 to the carrier C2 may first adhere the carrier C2 to the second surface S2 (e.g., the back surface) of the chip 100 through the adhesive layer 108, and then remove the adhesive layer 104 and the carrier C1 on the first surface S1 (e.g., the front surface) of the chip 100.
Fig. 1F is a schematic top view of a stage of a method of manufacturing a semiconductor package according to some embodiments of the invention. Referring to fig. 1F, a redistribution layer 110 may be formed on a first surface S1 (e.g., a front surface) of the chip layer CL1 to form a chip layer CL2. In some embodiments, the alignment mark 112 may be formed simultaneously in the fabrication process of forming the redistribution layer 110. In a subsequent manufacturing process, the alignment mark 112 may be used for alignment to improve the manufacturing process accuracy. In addition, the alignment mark 112 may be used as a cutting mark in a cutting process performed later. The chip layer CL2 may include at least one chip structure CS1. In the present embodiment, the chip layer CL2 is exemplified as including a plurality of chip structures CS1, but the number of chip structures CS1 in the chip layer CL2 is not limited to the number shown in the figure. As long as the chip layer CL2 includes at least one chip structure CS1, i.e. it is within the scope of the invention. In other embodiments, when the chip layer CL2 includes only one chip structure CS1, the chip layer CL2 is the chip structure CS1.
The chip structure CS1 includes a chip 100, a supporting layer 106a, and a redistribution layer 110. The support layer 106a is disposed on a side of the chip 100. In some embodiments, support layer 106a may surround chip 100. The redistribution layer 110 is disposed on the chip 100 and the support layer 106a. The redistribution layer 110 is electrically connected to the chip 100. For example, the redistribution layer 110 may be electrically connected to the pads 102 of the chip 100. In addition, the chip structure CS1 may further include an alignment mark 112. The alignment mark 112 may be located at a corner of the chip structure CS1, but the invention is not limited thereto.
In some embodiments, a protective layer (not shown) may be formed between the re-wiring layer 110 and the chip 100, between the re-wiring layer 110 and the support layer 106a, and between the alignment mark 112 and the chip 100, and a description thereof is omitted herein for the sake of simplifying the drawings. In some embodiments, another protective layer (not shown) covering the re-wiring layer 110 and the alignment mark 112 may be formed, and the description thereof is omitted herein for the sake of simplifying the drawings.
Fig. 1G is a schematic perspective view of a stage of a method of manufacturing a semiconductor package according to some embodiments of the invention. Referring to fig. 1G, the chip layer CL2 and the carrier C2 can be separated. For example, the chip layer CL2 can be separated from the carrier C2 by removing the adhesive layer 108.
Then, a plurality of chip layers CL2 may be stacked to form a chip layer stack SL1. Thereby, the chip stack CS2 can be formed. The chip stack CS2 includes a plurality of chip structures CS1 stacked. The chip layer stack SL1 may include at least one chip stack CS2. In the present embodiment, the chip layer stack SL1 is exemplified as including a plurality of chip stacks CS2, but the number of chip stacks CS2 in the chip layer stack SL1 is not limited to the number shown in the figure. As long as the chip layer stack SL1 comprises at least one chip stack CS2, i.e. it is within the scope covered by the present invention. In other embodiments, when the chip layer stack SL1 includes only one chip stack CS2, the chip layer stack SL1 itself is the chip stack CS2. In some embodiments, stacked chip layers CL2 may be secured together by adhesive layer 114. That is, the chip stack CS2 may further include an adhesive layer 114 between the stacked chip structures CS1. In some embodiments, the first sides S1 (e.g., front sides) of the plurality of chips 100 in the chip stack CS2 may face in the same direction.
Fig. 1H is a schematic top view of a stage of a method of manufacturing a semiconductor package according to some embodiments of the invention. Referring to fig. 1H, a molding via 116 may be formed in the chip layer stack SL1. For example, molded vias 116 are formed in at least a portion of the plurality of redistribution layers 110 and at least a portion of the plurality of support layers 106a (fig. 1K). The molded via 116 may extend through at least a portion of the plurality of redistribution layers 110 and at least a portion of the plurality of support layers 106a (fig. 1K). The molded via 116 is electrically connected to the plurality of redistribution layers 110 (fig. 1K). In the present embodiment, the molding holes 116 are exemplified as penetrating through all the redistribution layers 110 and all the support layers 106a, but the invention is not limited thereto. It is within the scope of the present invention that the molded via 116 be disposed such that the molded via 116 is electrically connected to the plurality of redistribution layers 110.
In some embodiments, the method of forming the molding via 116 may include the following steps. First, a protective film (not shown) may be formed on the chip layer stack SL1. Next, a laser drilling process may be performed on the chip layer stack SL1 to form an opening (not shown) through at least a portion of the plurality of re-wiring layers 110 and at least a portion of the plurality of support layers 106a. In the present embodiment, the openings penetrate through all the redistribution layers 110 and all the support layers 106a, but the present invention is not limited thereto. In addition, the opening may also penetrate the protective film and the adhesive layer 114 in fig. 1G. Then, a conductive layer (not shown) filling the opening may be formed. The material of the conductive layer is copper, for example. The conductive layer is formed by, for example, electroless plating, electroplating, or a combination thereof. Next, the protective film may be removed, whereby the conductive layer located outside the opening may be removed, forming the molded via 116.
Fig. 1I is a schematic perspective view of a stage of a method of manufacturing a semiconductor package according to some embodiments of the invention. Referring to fig. 1I, connection terminals 118 may be formed on the molding via 116 to form a chip layer stack SL2. The connection terminal 118 is electrically connected to the molded through hole 116. Thereby, the chip stack structure CS3 can be formed. In the present embodiment, the second surface S2 (e.g. the back surface) of the chip 100 may be faced upward, and then the connection terminal 118 electrically connected to the molding through hole 116 is formed, that is, the connection terminal 118 may be adjacent to the second surface S2 (e.g. the back surface) of the chip 100, but the invention is not limited thereto. In other embodiments, the first surface S1 (e.g., front surface) of the chip 100 may be first turned upward, and then the connection terminals 118 electrically connected to the molding through holes 116 are formed, i.e., the connection terminals 118 may be adjacent to the first surface S1 (e.g., front surface) of the chip 100. The chip stack structure CS3 includes a chip stack CS2, a molding through hole 116, and a connection terminal 118. The chip layer stack SL2 may include at least one chip stack structure CS3. In the present embodiment, the chip layer stack SL2 is exemplified as including a plurality of chip stack structures CS3, but the number of the chip stack structures CS3 in the chip layer stack SL2 is not limited to the number shown in the drawing. As long as the chip layer stack SL2 comprises at least one chip stack structure CS3, it is within the scope of the present invention. In other embodiments, when the chip layer stack SL2 includes only one chip stack structure CS3, the chip layer stack SL2 itself is the chip stack structure CS3. The connection terminals 118 may be bumps (e.g., solder balls), but the invention is not limited thereto.
Fig. 1J is a schematic perspective view of a stage of a method of manufacturing a semiconductor package according to some embodiments of the invention. Referring to fig. 1J, a dicing process may be performed on the chip layer stack SL2. Thereby, the chip layer stack SL2 can be cut into a plurality of chip stack structures CS3 separated from each other. For example, the chip layer stack SL2 may be diced by a wafer dicing blade DB, but the invention is not limited thereto. In other embodiments, when the chip layer stack SL2 includes only one chip stack structure CS3, the dicing process may be performed on the chip layer stack SL2 to reduce the size of the chip stack structure CS3. In other embodiments, when the chip layer stack SL2 includes only one chip stack structure CS3, the dicing process may not be performed on the chip layer stack SL2.
Fig. 1K is a schematic cross-sectional view of a stage of a method of manufacturing a semiconductor package according to some embodiments of the invention. In fig. 1K, the pad 102 is omitted to simplify the drawing. Referring to fig. 1K, the chip stack structure CS3 may be disposed on the substrate 120. The chip stack structure CS3 may be electrically connected to the substrate 120 through the connection terminal 118. The substrate 120 may be a package substrate. In some embodiments, the package substrate may include a base, a re-wiring layer, a dielectric layer, and a via (via), but the invention is not limited thereto. The material of the base of the substrate 120 may be silicon (e.g., monocrystalline silicon or polycrystalline silicon), glass, an organic material, a ceramic, a composite material, or a combination thereof. In addition, a connection terminal 122 may be provided at the bottom of the substrate 120, whereby the substrate 120 may be electrically connected with other electronic components. The connection terminals 122 may be bumps (e.g., solder balls), but the invention is not limited thereto.
Next, an encapsulant 124 covering the chip stack structure CS3 may be formed. The encapsulant 124 may be used to protect the chip stack CS3. In addition, the encapsulant 124 may be positioned on the substrate 120. The material of the encapsulant 124 is, for example, a molding compound.
Hereinafter, the semiconductor package 10 of the present embodiment will be described with reference to fig. 1K. In addition, although the method of forming the semiconductor package 10 is described by way of example, the present invention is not limited thereto.
Referring to fig. 1K, the semiconductor package 10 includes a chip stack structure CS3. The chip stack structure CS3 includes a chip stack CS2, a through mold via 116 (through mold via), and a connection terminal 118. The chip stack CS2 includes a plurality of chip structures CS1 stacked. In addition, the chip stack CS2 may further include an adhesive layer 114. The adhesive layer 114 is disposed between the stacked chip structures CS1. Each chip structure CS1 includes a chip 100, a support layer 106a, and a redistribution layer 110. The support layer 106a is disposed on a side of the chip 100. In some embodiments, support layer 106a may surround chip 100. The redistribution layer 110 is disposed on the chip 100 and the support layer 106a. The redistribution layer 110 is electrically connected to the chip 100. In addition, the chip structure CS1 may further include an alignment mark 112 (fig. 1H). The alignment mark 112 may be located at a corner of the chip structure CS1, but the invention is not limited thereto. The molded via 116 is disposed in at least a portion of the plurality of redistribution layers 110 and at least a portion of the plurality of support layers 106a. The molded via 116 is electrically connected to the plurality of redistribution layers 110. The molded via 116 may extend through at least a portion of the plurality of redistribution layers 110 and at least a portion of the plurality of support layers 106a. In the present embodiment, the molding holes 116 are exemplified as penetrating through all the redistribution layers 110 and all the support layers 106a, but the invention is not limited thereto. It is within the scope of the present invention that the molded via 116 be disposed such that the molded via 116 is electrically connected to the plurality of redistribution layers 110. The connection terminal 118 is electrically connected to the molded through hole 116. In the present embodiment, the connection terminal 118 may be adjacent to the second surface S2 (e.g. the back surface) of the chip 100, and the second surface S2 (e.g. the back surface) of the chip 100 faces the substrate 120, but the invention is not limited thereto.
In addition, the semiconductor package 10 further includes a substrate 120, an encapsulant 124, and connection terminals 122. The chip stack structure CS3 is disposed on the substrate 120. The chip stack structure CS3 may be electrically connected to the substrate 120 through the connection terminal 118. The encapsulant 124 covers the chip stack CS3. The connection terminal 122 is disposed at the bottom of the substrate 120.
In addition, materials, detailed configurations, forming methods and functions of the components of the semiconductor package 10 are described in detail in the above embodiments, and will not be repeated here.
As can be seen from the above embodiments, in the semiconductor package 10 and the manufacturing method thereof, the supporting layer 106a can be used to support and protect the chip 100, so that the chip 100 can be prevented from being damaged during the manufacturing process. In addition, the stacked chips 100 are electrically connected by the molding through holes 116, so that the wire bonding process and the bump process can be reduced, thereby reducing the manufacturing cost. In addition, the stacked chips 100 are electrically connected by the molding through holes 116, which shortens the circuit length and reduces the heterojunction, thereby improving the electrical performance of the semiconductor package 10.
Fig. 2 is a schematic cross-sectional view of a semiconductor package according to further embodiments of the present invention. Referring to fig. 1K and 2, the semiconductor package 20 of fig. 2 differs from the semiconductor package 10 of fig. 1K as follows. In the semiconductor package 20 of fig. 2, the connection terminals 118 are adjacent to the first side S1 (e.g., front side) of the chip 100, and the first side S1 (e.g., front side) of the chip 100 faces the substrate 120. In addition, the same members in the semiconductor package 20 and the semiconductor package 10 are denoted by the same reference numerals, and the same or similar contents in the semiconductor package 20 and the semiconductor package 10 can be referred to the description of the semiconductor package 10 in the above embodiment, and will not be described here.
Fig. 3 is a schematic cross-sectional view of a semiconductor package according to further embodiments of the present invention.
Referring to fig. 2 and 3, the semiconductor package 30 of fig. 3 differs from the semiconductor package 20 of fig. 2 as follows. In the semiconductor package 30 of fig. 3, the molding through-hole 116 penetrates only a portion of the plurality of support layers 106a. In addition, the same members in the semiconductor package 30 and the semiconductor package 20 are denoted by the same reference numerals, and the same or similar contents in the semiconductor package 30 and the semiconductor package 20 can be referred to the description of the above embodiment for the semiconductor package 20, and will not be described here.
Fig. 4 is a schematic cross-sectional view of a semiconductor package according to further embodiments of the present invention.
Referring to fig. 3 and 4, the semiconductor package 40 of fig. 4 is different from the semiconductor package 30 of fig. 3 as follows. In the semiconductor package 40 of fig. 4, the encapsulant 124 is ground to expose the second side S2 (e.g., the back side) of the chip 100 in the chip stack structure CS3. In this way, the second surface S2 (e.g., the back surface) of the chip 100 is exposed, thereby providing better heat dissipation capability. In addition, the same components in the semiconductor package 40 and the semiconductor package 30 are denoted by the same symbols, and the same or similar contents in the semiconductor package 40 and the semiconductor package 30 can be referred to the description of the semiconductor package 30 in the above embodiment, and will not be described here.
In summary, in the semiconductor package and the method for manufacturing the same of the above embodiments, the semiconductor package includes the supporting layer and the molding through hole, so as to prevent the chip from being damaged during the manufacturing process, reduce the manufacturing cost, and improve the electrical performance of the semiconductor package.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified and altered by persons skilled in the art without departing from the spirit and scope of the invention.

Claims (10)

1. A semiconductor package comprising a chip stack structure, wherein the chip stack structure comprises:
a chip stack comprising a plurality of chip structures stacked, wherein each of the chip structures comprises:
a chip;
the support layer is arranged on the side edge of the chip; and
a rewiring layer disposed on the chip and the supporting layer and electrically connected to the chip;
a molded via disposed in at least a portion of the plurality of rewiring layers and at least a portion of the plurality of support layers and electrically connected to the plurality of rewiring layers; and
and a connection terminal electrically connected to the molding through hole.
2. The semiconductor package of claim 1, wherein the support layer surrounds the die.
3. The semiconductor package of claim 1, wherein the molded via extends through at least a portion of the plurality of redistribution layers and at least a portion of the plurality of support layers.
4. The semiconductor package of claim 1, further comprising:
a substrate, wherein the chip stack structure is disposed on the substrate, and the chip stack structure is electrically connected to the substrate through the connection terminal; and
and the encapsulation body covers the chip stacking structure.
5. A method of manufacturing a semiconductor package, comprising forming a chip stack structure, wherein the method of forming the chip stack structure comprises:
forming a chip stack, wherein the chip stack comprises a plurality of chip structures stacked, and each of the chip structures comprises:
a chip;
the support layer is arranged on the side edge of the chip; and
a rewiring layer disposed on the chip and the supporting layer and electrically connected to the chip; forming a molded via in at least a portion of the plurality of redistribution layers and at least a portion of the plurality of support layers, wherein the molded via is electrically connected to the plurality of redistribution layers; and
a connection terminal is formed on the molded through hole, wherein the connection terminal is electrically connected to the molded through hole.
6. The method of manufacturing a semiconductor package according to claim 5, wherein the method of forming the chip structure comprises:
at least one chip is arranged on a first carrier plate, wherein the chip is provided with a first surface and a second surface which are opposite, and the first surface of the chip faces the first carrier plate;
forming a layer of support material covering the chip;
removing a part of the supporting material layer and a part of the chip to form a first chip layer and thinning the chip, wherein the first chip layer comprises the chip and the supporting layer;
transferring the first chip layer from the first carrier plate to a second carrier plate, wherein the second face of the chip faces the second carrier plate; and
the rewiring layer is formed on the first face of the first chip layer, and a second chip layer is formed, wherein the second chip layer comprises at least one chip structure.
7. The method of manufacturing a semiconductor package according to claim 6, further comprising:
separating the second chip layer from the second carrier plate; and
stacking a plurality of the second chip layers to form a first chip layer stack, wherein the first chip layer stack comprises at least one of the chip stacks.
8. The method of manufacturing a semiconductor package according to claim 7, further comprising:
forming the molded via in the first chip layer stack; and
the connection terminals are formed on the molded through holes to form a second chip layer stack, wherein the second chip layer stack includes at least one of the chip stack structures.
9. The method of manufacturing a semiconductor package according to claim 8, further comprising:
and cutting and manufacturing the second chip layer stack.
10. The method of manufacturing a semiconductor package according to claim 5, further comprising:
disposing the chip stack structure on the substrate, wherein the chip stack structure is electrically connected to the substrate through the connection terminal; and
and forming an encapsulation body covering the chip stacking structure.
CN202111646276.3A 2021-12-15 2021-12-30 Semiconductor package and method of manufacturing the same Pending CN116264211A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
TW110146876 2021-12-15
TW110146876A TWI781009B (en) 2021-12-15 2021-12-15 Semiconductor package and manufacturing method thereof

Publications (1)

Publication Number Publication Date
CN116264211A true CN116264211A (en) 2023-06-16

Family

ID=85475753

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111646276.3A Pending CN116264211A (en) 2021-12-15 2021-12-30 Semiconductor package and method of manufacturing the same

Country Status (2)

Country Link
CN (1) CN116264211A (en)
TW (1) TWI781009B (en)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11296052B2 (en) * 2017-09-30 2022-04-05 Intel Corporation TSV-less die stacking using plated pillars/through mold interconnect
US11616026B2 (en) * 2020-01-17 2023-03-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US11710669B2 (en) * 2020-05-25 2023-07-25 International Business Machines Corporation Precision thin electronics handling integration

Also Published As

Publication number Publication date
TWI781009B (en) 2022-10-11
TW202326959A (en) 2023-07-01

Similar Documents

Publication Publication Date Title
US11456251B2 (en) Semiconductor structure, package structure, and manufacturing method thereof
US8093711B2 (en) Semiconductor device
KR100871382B1 (en) Through silicon via stack package and method for manufacturing of the same
EP1471571B1 (en) Semiconductor device and manufacturing method thereof
US7425464B2 (en) Semiconductor device packaging
US8207617B2 (en) Electrical connections for multichip modules
US20120034777A1 (en) Through Hole Vias at Saw Streets Including Protrusions or Recesses for Interconnection
US20120168935A1 (en) Integrated circuit device and method for preparing the same
KR20180027679A (en) Semiconductor package and method of fabricating the same
KR100886706B1 (en) Stack package and manufacturing method of the same
US11309283B2 (en) Packaging structure and manufacturing method thereof
US20240038732A1 (en) Semiconductor packages and methods of manufacturing the semiconductor packages
US10529693B2 (en) 3D stacked dies with disparate interconnect footprints
US20080197473A1 (en) Chip holder with wafer level redistribution layer
US11545469B2 (en) Semiconductor package and manufacturing method thereof
CN213936169U (en) Secondary plastic package packaging structure
KR20020024624A (en) Stack package of chip size level and manufacturing method thereof
CN112151457A (en) Packaging structure, manufacturing method thereof and electronic equipment
CN116264211A (en) Semiconductor package and method of manufacturing the same
CN115376931A (en) Manufacturing method of three-dimensional system single chip and three-dimensional system single chip
US11469219B1 (en) Dual die semiconductor package and manufacturing method thereof
US20240055400A1 (en) Substrate for vertically assembled semiconductor dies
CN109786362B (en) External fan crystal grain laminated structure without welding pad and manufacturing method thereof
US9761535B1 (en) Interposer, semiconductor package with the same and method for preparing a semiconductor package with the same
KR20230172743A (en) Semiconductor package and method of manufacturing the semiconductor package

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination