CN116263480A - Method for realizing variable resistor in chip test - Google Patents
Method for realizing variable resistor in chip test Download PDFInfo
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- CN116263480A CN116263480A CN202111532510.XA CN202111532510A CN116263480A CN 116263480 A CN116263480 A CN 116263480A CN 202111532510 A CN202111532510 A CN 202111532510A CN 116263480 A CN116263480 A CN 116263480A
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- 238000012360 testing method Methods 0.000 title claims abstract description 43
- 238000000034 method Methods 0.000 title claims abstract description 16
- 238000001514 detection method Methods 0.000 claims abstract description 22
- 238000002955 isolation Methods 0.000 claims abstract description 10
- 239000003990 capacitor Substances 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 3
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
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Abstract
The method for realizing the variable resistor in the chip test is characterized in that a chip pin end of a chip to be tested is used as a relay node, a first path of the relay node is grounded through a first resistor, a second path of the relay node is connected with a positive end of a variable voltage source through a second resistor, a negative end of the variable voltage source is grounded, a third path of the variable voltage source is connected with an epitaxial voltage detection end of the chip pin through a low-pass filter isolation circuit, the combination of the variable voltage source, the first resistor and the second resistor can be used for generating an equivalent resistor of the variable resistor required in the chip test, and the chip pin epitaxial voltage detection end formed by the low-pass filter isolation circuit prevents the interference of a detection instrument on pins during pin voltage detection and prevents parasitic capacitance of some test elements from affecting the internal stability of the chip.
Description
Technical Field
The invention relates to a variable resistance technology used for chip test, in particular to a method for realizing a variable resistance in chip test.
Background
The chip includes a plurality of pins distributed around the chip, the pins being connections leading from the inside of the integrated circuit to peripheral circuits, each pin having a function definition for developing the chip application, and the implementation of the pin function being dependent on its corresponding chip internal parameters. Whether the parameters in the chip can meet the requirements or not needs to be tested through pins (such as FB pins or pins FB). Some tests require that resistors with different resistance values (for example, from R1 to Rn, or a resistor network consisting of R1 to Rn) are externally connected at the pins, and whether each resistor is connected or not is controlled by a switch or a relay. Fig. 2 is a schematic diagram of a resistor network structure used in a chip test in the prior art. As shown in fig. 2, the chip part illustrates the connection relationship between a plurality of PMOS transistors and an amplifier circuit or a comparator circuit, the negative input terminal (-) of the amplifier is connected with the reference voltage terminal Vref, and the positive input terminal (+) of the amplifier and the drain electrode of the PMOS transistor with the gate connected with the output terminal of the amplifier are both connected with the chip pin terminal FB. The chip pin terminal FB is connected with a variable resistance network, the variable resistance network is a parallel circuit formed by R1 to Rn, one end of R1 to one end of Rn are grounded, and the other end of R1 to the other end of Rn are connected to the chip pin terminal FB through a first switch K1 to an nth switch Kn in a one-to-one mode. When the chip FB pin is required to be connected with a plurality of resistors with different resistance values to test some parameters in the chip, the FB relay can be connected with a plurality of test boards, and the different resistors are switched through the relay. However, if the resistance value of the resistor is relatively large, a plurality of relays are connected, so that the complexity of the test board is increased, and on the other hand, too many devices are connected on the FB, which may affect the stability of the inner loop of the circuit.
Disclosure of Invention
Aiming at the defects or shortcomings in the prior art, the invention provides a method for realizing a variable resistor in chip test.
The technical scheme of the invention is as follows:
the method for realizing the variable resistor in the chip test is characterized by comprising the step of taking a chip pin end of a chip to be tested as a relay node, wherein a first path of the relay node is grounded through a first resistor, a second path of the relay node is connected with a positive end of a variable voltage source through a second resistor, a negative end of the variable voltage source is grounded, and a third path of the relay node is connected with an epitaxial voltage detection end of the chip pin through a low-pass filter isolation circuit.
The combination of the variable voltage source, the first resistor, and the second resistor is used to produce an equivalent resistance to the variable resistor required in the chip test.
The low-pass filtering isolation circuit comprises a third resistor, one end of the third resistor is connected with the relay node, the other end of the third resistor is respectively connected with one end of a first capacitor and one end of a fourth resistor, the other end of the first capacitor is grounded, and the other end of the fourth resistor is connected with the chip pin epitaxial voltage detection end.
Let the voltage of chip pin epitaxial voltage detection end be VFB, the voltage of variable voltage source be Vtest, the resistance of first resistance is R1, the resistance of second resistance is R2, then the resistance RFB of the required variable resistance in the chip test is confirmed by following formula:
let the voltage of chip pin epitaxial voltage detection end be VFB, the resistance of the required variable resistance in the chip test be RFB, the resistance of first resistance be R1, the resistance of second resistance be R2, then the voltage Vtest of variable voltage source is confirmed through following formula:
the invention has the following technical effects: the invention relates to a method for realizing variable resistor in chip test, which uses the chip pin end of the tested chip as a relay node, wherein the first path of the relay node is grounded through a first resistor, the second path is connected with the positive end of a variable voltage source through a second resistor, the negative end of the variable voltage source is grounded, and the third path is connected with the chip pin epitaxial voltage detection end through a low-pass filter isolation circuit, so that the combination of the variable voltage source, the first resistor and the second resistor is used for generating the equivalent resistor of the variable resistor required in the chip test, and the chip pin epitaxial voltage detection end formed by the low-pass filter isolation circuit prevents the interference of a detection instrument on pins during pin voltage detection, and prevents parasitic capacitance of some test elements from affecting the internal stability of the chip.
Drawings
FIG. 1 is a schematic diagram of a structure formed by implementing a method for implementing a variable resistor in a chip test according to the present invention. In fig. 1, a chip part illustrates a connection relationship between a plurality of PMOS transistors and an amplifier circuit or a comparator circuit, a negative input terminal (-) of the amplifier is connected with a reference voltage terminal Vref, and a positive input terminal (+) of the amplifier and a drain electrode of the PMOS transistor with a gate electrode connected with an output terminal of the amplifier are both connected with a chip pin terminal FB.
Fig. 2 is a schematic diagram of a resistor network structure used in a chip test in the prior art. In fig. 2, the connection relation between a plurality of PMOS transistors and an amplifier circuit or a comparator circuit is illustrated in the chip part, the negative input terminal (-) of the amplifier is connected with the reference voltage terminal Vref, and the positive input terminal (+) of the amplifier and the drain electrode of the PMOS transistor with the gate electrode connected with the output terminal of the amplifier are both connected with the chip pin terminal FB.
The reference numerals are listed below: vref—a reference voltage terminal; FB-chip pin end; R1-Rn-first to nth resistors, n being a positive integer; K1-Kn-first to nth switches; VFB-chip pin epitaxial voltage detection end; c1-a first capacitance; vtest-variable voltage source (variable resistor for forming different resistance values in chip test).
Detailed Description
The invention will be described with reference to the accompanying drawings (fig. 1).
FIG. 1 is a schematic diagram of a structure formed by implementing a method for implementing a variable resistor in a chip test according to the present invention. Referring to fig. 1, a method for implementing a variable resistor in a chip test includes taking a chip pin FB of a chip to be tested as a relay node, where a first path of the relay node is grounded through a first resistor R1, a second path of the relay node is connected to a positive terminal (+) of a variable voltage source Vtest through a second resistor R2, a negative terminal (-) of the variable voltage source Vtest is grounded, and a third path of the relay node is connected to a chip pin epitaxial voltage detection terminal VFB through a low-pass filter isolation circuit. The combination of the variable voltage source Vtest, the first resistor R1, and the second resistor B2 is used to generate an equivalent resistor RFB of the variable resistor required in the chip test.
The low-pass filtering isolation circuit comprises a third resistor R3, one end of the third resistor R3 is connected with the relay node, the other end of the third resistor R3 is respectively connected with one end of a first capacitor C1 and one end of a fourth resistor R4, the other end of the first capacitor C1 is grounded, and the other end of the fourth resistor R4 is connected with the chip pin epitaxial voltage detection end VFB.
Let the voltage of chip pin epitaxial voltage detection end be VFB, the voltage of variable voltage source be Vtest, the resistance of first resistance is R1, the resistance of second resistance is R2, then the resistance RFB of the required variable resistance in the chip test is confirmed by following formula:
let the voltage of chip pin epitaxial voltage detection end be VFB, the resistance of the required variable resistance in the chip test be RFB (RFB is FB point equivalent resistance), the resistance of first resistance be R1, the resistance of second resistance be R2, then the voltage Vtest of variable voltage source is confirmed by following formula:
in some chip testing processes, multiple different resistance values may be required to test the chip, and multiple resistance values are difficult to realize during batch testing. By the invention, the testing program can realize any resistance value by testing the VFB voltage and setting a Vtest voltage. R3, R4 and C1 play a role in filtering and isolating, so that on one hand, interference of a detecting instrument on an FB pin during VFB voltage detection is prevented, and on the other hand, parasitic capacitance added into C1 and some test elements is prevented from affecting internal stability.
By adopting the invention to test some parameters in the chip, on one hand, the complexity of the test board is not required to be increased, and on the other hand, too many devices are not required to be connected on the FB, so that adverse effects on the stability of an inner loop of a chip circuit are avoided, and the effectiveness of testing the parameters in the chip is improved.
What is not described in detail in the present specification belongs to the prior art known to those skilled in the art. It is noted that the above description is helpful for a person skilled in the art to understand the present invention, but does not limit the scope of the present invention. Any and all such equivalent substitutions, modifications and/or deletions as may be made without departing from the spirit and scope of the invention.
Claims (5)
1. The method for realizing the variable resistor in the chip test is characterized by comprising the step of taking a chip pin end of a chip to be tested as a relay node, wherein a first path of the relay node is grounded through a first resistor, a second path of the relay node is connected with a positive end of a variable voltage source through a second resistor, a negative end of the variable voltage source is grounded, and a third path of the relay node is connected with an epitaxial voltage detection end of the chip pin through a low-pass filter isolation circuit.
2. The method of claim 1, wherein the combination of the variable voltage source, the first resistor, and the second resistor is used to generate an equivalent resistance of the variable resistor required in the chip test.
3. The method for implementing a variable resistor in a chip test according to claim 1, wherein the low-pass filter isolation circuit includes a third resistor, one end of the third resistor is connected to the relay node, the other end of the third resistor is connected to one end of a first capacitor and one end of a fourth resistor, the other end of the first capacitor is grounded, and the other end of the fourth resistor is connected to the chip pin epitaxial voltage detection end.
4. The method for implementing the variable resistor in the chip test according to claim 1, wherein the voltage of the chip pin epitaxial voltage detection terminal is VFB, the voltage of the variable voltage source is Vtest, the resistance of the first resistor is R1, and the resistance of the second resistor is R2, and the resistance RFB of the variable resistor required in the chip test is determined by the following formula:
5. the method for implementing a variable resistor in a chip test according to claim 1, wherein the voltage at the chip pin epitaxial voltage detection terminal is VFB, the resistance of the variable resistor required in the chip test is RFB, the resistance of the first resistor is R1, and the resistance of the second resistor is R2, and the voltage Vtest of the variable voltage source is determined by the following formula:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111532510.XA CN116263480A (en) | 2021-12-15 | 2021-12-15 | Method for realizing variable resistor in chip test |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202111532510.XA CN116263480A (en) | 2021-12-15 | 2021-12-15 | Method for realizing variable resistor in chip test |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116879723A (en) * | 2023-09-04 | 2023-10-13 | 上海灵动微电子股份有限公司 | Universal chip test board |
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2021
- 2021-12-15 CN CN202111532510.XA patent/CN116263480A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116879723A (en) * | 2023-09-04 | 2023-10-13 | 上海灵动微电子股份有限公司 | Universal chip test board |
| CN116879723B (en) * | 2023-09-04 | 2023-11-21 | 上海灵动微电子股份有限公司 | Universal chip test board |
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