CN116261770A - 选择性低温外延沉积处理 - Google Patents

选择性低温外延沉积处理 Download PDF

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CN116261770A
CN116261770A CN202180059332.5A CN202180059332A CN116261770A CN 116261770 A CN116261770 A CN 116261770A CN 202180059332 A CN202180059332 A CN 202180059332A CN 116261770 A CN116261770 A CN 116261770A
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antimony
layers
containing precursor
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drain regions
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吴贞莹
阿布舍克·杜贝
黃奕樵
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Applied Materials Inc
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Abstract

本文描述一种用于外延层的选择性形成的方法。在该方法中，沉积外延层以在水平全环绕栅极(hGAA结构)周围形成源极和漏极区域。该方法包括共同流动氯化的含硅前驱物、含锑前驱物和n型掺杂前驱物的组合。得到的源极和漏极区域被从hGAA结构的晶体纳米片或纳米线选择性地生长而优于从非晶体栅极结构和介电层选择性地生长。源极和漏极区域主要沿<110>方向生长。

Description

选择性低温外延沉积处理
背景
技术领域
本公开内容的实施方式一般涉及用于形成半导体装置的方法。更具体而言，本申请涉及用于水平全环绕栅极(horizontal gate all around；hGAA)装置结构的外延沉积方法。
背景技术
随着晶体管装置的特征大小继续缩小以实现更大的电路密度和更高的性能，需要改良晶体管装置结构以改良静电耦合并且降低负面效应，诸如寄生电容和截止状态泄漏(off-stage leakage)。晶体管装置结构的范例包括平面结构、鳍式场效应晶体管(FinFET)结构和水平全环绕栅极(hGAA)结构。hGAA装置结构包括以堆叠的构造悬置的(suspended)并且由源极/漏极区域连接的数个晶格匹配的沟道(channel)。
然而，与hGAA结构相关联的挑战包括在低温下n沟道金属氧化物半导体(NMOS)源极/漏极区域的形成。在低温下形成NMOS源极/漏极区域的传统方式导致前驱物不相容和选择性损失。传统方式亦利用分开的蚀刻和沉积步骤，这增加了装置生产的成本。然而，提高NMOS源极/漏极区域的形成的温度可能提高掺杂物在整个hGAA结构中的扩散速率，并且需要更长的加速(ramp up)/降速(ramp down)时间。
因此，需要一种在hGAA结构上以较低温度形成NMOS源极/漏极区域并且没有额外蚀刻操作的方法。
发明内容
本公开内容一般包括用于在半导体结构上形成源极/漏极区域的方法。更具体而言，本公开内容的实施方式包括一种形成半导体装置的方法。这种形成半导体装置的方法包括：在基板上形成多重材料层，其中该多重材料层包括以交替图案布置的多个晶体第一层(crystalline first layer)以和多个非晶体第二层(non-crystalline secondlayer)。在该基板的所述多个晶体第一层上选择性地形成源极区域和漏极区域，其中形成的该源极区域和该漏极区域含有大于约5x1020原子/cm3的锑浓度。形成该源极区域和该漏极区域的步骤进一步包含以下步骤：流动氯化的含硅前驱物；与该氯化的含硅前驱物共同流动(co-flow)含锑前驱物；与该氯化的含硅前驱物和该含锑前驱物共同流动n型掺杂前驱物；和加热该基板至小于约550℃的温度。
在另一实施方式中，描述了一种半导体装置。这种半导体装置包括多重材料层(multi-material layer)。该多重材料层包括：多个第一层，包含晶体硅材料；以及多个第二层，包含金属材料和在该金属材料的外表面上的高k材料。该多个第二层与该多个第一层以交替图案布置。这种半导体装置进一步包括源极区域和漏极区域。该源极区域和该漏极区域为外延层，并且包括硅材料、锑掺杂物和n型掺杂物。
在又一实施方式中，描述了一种形成半导体装置的方法。这种形成半导体装置的方法包括：主要沿<110>方向在基板上选择性地生长源极区域和漏极区域。该源极区域和该漏极区域含有大于约5x1020原子/cm3的锑浓度。选择性地生长该源极区域和该漏极区域的步骤进一步包括以下步骤：使氯化的含硅前驱物流入具有该基板的处理腔室中；使含锑前驱物与该氯化的含硅前驱物共同流入(co-flowed into)该处理腔室中；使磷掺杂前驱物与该氯化的含硅前驱物和该含锑前驱物共同流入该处理腔室中；以及在该氯化的含硅前驱物、该含锑前驱物和该磷掺杂前驱物的流动期间，加热该基板至小于约550℃的温度。
附图说明
以此方式可详细理解本公开内容以上所述的特征，以上简要概述的本公开内容的更特定的描述可通过参考实施方式而获得，这些实施方式中的一些实施方式图示于附图中。然而，应注意的是，附图仅图示范例实施方式，因此不应被视为对本公开内容的范围的限制，可认可其他等同有效的实施方式。
图1根据一个实施方式，图示hGAA结构的示意性等距视图。
图2A-图2C根据一个实施方式，图示图1的hGAA结构的示意性截面图。
图3根据一个实施方式，图示形成图1和图2A-图2C的hGAA结构的方法。
为了促进理解，已尽可能地使用相同的参考数字代表各附图中共有的相同元件。可预期的是，一个实施方式的元件和特征可有益地并入其他实施方式而无须进一步说明。
具体实施方式
本公开内容一般涉及一种用于形成半导体装置的方法。提供了一种在水平全环绕栅极(hGAA)装置结构之中外延沉积n沟道金属氧化物半导体(NMOS)源极/漏极区域的方法。在小于约550℃的温度执行这种方法。这种方法包括使用氯化的含硅前驱物、含锑前驱物和含磷前驱物。
氯化的含硅前驱物被用来随着外延层被形成而连续地蚀刻外延层，并且随着外延层被沉积至超晶格结构上而改进外延层的选择性。外延层仅形成在超晶格结构的晶体部分上，并且不在氧化或非晶体表面上。含锑前驱物降低了沉积外延层所处的温度并且提高了在超晶格结构的晶体部分上外延层的生长速率。含磷前驱物以磷掺杂外延层，并且使外延层能够更好地粘附至超晶格结构的晶体部分。
已显示的是，外延层相对于超晶格结构的暴露的晶体表面的生长速率随着外延层中添加不同浓度的锑而改变。在本文所述的实施方式中，外延层中锑的浓度为大于约5x1020原子/cm3，并且主要沿<110>方向生长。已经显示，锑浓度造成沿<110>方向的主要晶体生长。主要沿<110>方向的晶体生长减少了超晶格结构上外延层的切刻(faceting)。用于沿<111>方向的生长速率的先前方法由于切刻而在生长方面受限。
图1根据一个实施方式，图示了水平全环绕栅极(hGAA)结构100的示意性等距视图。hGAA结构100包括用在hGAA结构100中的多重材料层105，该多重材料层105具有交替的第一层106和第二层108，有间隔件110形成于第二层108中。hGAA结构100利用多重材料层105作为源极114a和漏极114b与栅极结构112之间的纳米线(例如，沟道)。如图1中多重材料层105的截面图中所显示，形成于第二层108每一层的(例如)底部(或端部)处的纳米线间隔件110帮助管理第二层108与源极/漏极114a、114b之间的界面，以便减少寄生电容和维持最小装置泄漏。
hGAA结构100包括设置于基板102的顶表面103上的该多重材料层105，该多重材料层105诸如设置于基板102上设置的可选材料层104的顶上。在其中不存在可选材料层104的实施方式中，该多重材料层105直接形成于基板102上。
基板102可为诸如晶体硅(例如，Si<100>或Si<111>)、氧化硅、应变硅、硅锗、锗、掺杂的或未掺杂的多晶硅、掺杂的或未掺杂的硅晶片和图案化或未图案化的绝缘体上硅(SOI)晶片、碳掺杂的氧化硅、氮化硅、掺杂的硅、锗、砷化镓、玻璃或蓝宝石之类的材料。基板102可具有各种尺寸，诸如200mm、300mm、450mm或其他直径，并且可为矩形或正方形面板。除非另外说明，本文所述的范例在具有200mm直径、300mm直径或450mm直径的基板上进行。
在一个范例中，可选材料层102为绝缘材料。绝缘材料的适合的范例可包括氧化硅材料、氮化硅材料、氮氧化硅材料或任何适合的绝缘材料。或者，可选材料层104可为包括如所需的导电材料或非导电材料的任何适合的材料。多重材料层105包括至少一对层，每一对层包含第一层106和第二层108。尽管图1中描绘的范例显示了四对和第一层106覆盖，但每一对层包括第一层106和第二层108(交替的对，每一对层包含第一层106和第二层108)。额外的第一层106被设置作为多重材料层105的顶部。这些对的数量可基于不同处理的需求而变化，以具有需要的额外的第一层106或第二层108或者不具有额外的第一层106或第二层108。在一个实施方案中，每个单个第一层106的厚度可在约
Figure BDA0004113654540000041
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Figure BDA0004113654540000042
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Figure BDA0004113654540000043
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Figure BDA0004113654540000045
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之间的总厚度。
第一层106每一层都为晶体层，诸如单晶的、多晶的、或者单晶硅层。使用外延沉积处理形成第一层106。或者，第一层106为掺杂的硅层，包括p型掺杂的硅层或n型掺杂的层。适合的p型掺杂物包括B掺杂物、Al掺杂物、Ga掺杂物、In掺杂物或类似物。适合的n型掺杂物包括N掺杂物、P掺杂物、As掺杂物、Sb掺杂物或类似物。在又一范例中，第一层106为III-V族材料，例如GaAs层。
第二层108为非晶体材料层。在一些实施方式中，第二层108为含Ge层，诸如SiGe层、Ge层、或其他适合的层。或者，第二层108为掺杂的硅层，包括p型掺杂的硅层或n型掺杂的层。在又一范例中，第二层108为III-V族材料，诸如GaAs层。在再一范例中，第一层106为硅层且第二层108为一种金属材料，有高k材料涂布在该金属材料的外表面上。高k材料的适合的范例包括二氧化铪(HfO2)、二氧化锆(ZrO2)、氧化硅酸铪(HfSiO4)、氧化铪铝(HfAlO)、氧化硅酸锆(ZrSiO4)、二氧化钽(TaO2)、氧化铝、铝掺杂的二氧化铪、铋锶钛(BST)或铂锆钛(PZT)等等。在一个特定实施方案中，涂层为二氧化铪(HfO2)层。在一些实施方式中，第二层108为类似于栅极结构112的材料，以形成在第一层106周围的环绕栅极(wraparoundgate)。
间隔件110每一个都相邻于第二层108的端部形成，并且可被视为第二层108的一部分。间隔件110为介电间隔件或气隙。间隔件110可通过以下方式形成：使用蚀刻前驱物蚀刻掉第二层108每一层的一部分，以在第二层108每一层的端部处形成凹部。间隔件110相邻于第二层108每一层形成在这些凹部中。衬垫层(未显示)在沉积间隔件110之前可被额外地沉积于这些凹部之中。间隔件110由介电材料形成，并且分开形成为第一层106的纳米线或纳米片每一个。在一些实施方式中，间隔件110被选择为含硅材料，这种材料可减少hGAA纳米线结构中栅极与源极/漏极结构之间的寄生电容，这种材料诸如是低K材料。含硅材料或低K材料可为氮化硅、氧化硅、氮氧化硅、碳化硅、碳氧化硅、碳氮化硅、掺杂的硅层或其他适合的材料，诸如从应用材料公司可取得的Black
Figure BDA0004113654540000051
材料。
在一个实施方式中，间隔件110为低k材料(例如，介电常数小于4)或含氧化硅/氮化硅/碳化硅的材料。在其他的实施方式中，间隔件110为气隙。
栅极结构112设置于多重材料层105之上和周围。根据一个实施方式，栅极结构112包括栅极电极层，并且可额外包括栅极介电层、栅极间隔件和掩模层。栅极结构112的栅极电极层包括多晶硅层或以多晶硅层覆盖的金属层。栅极电极层可包括金属氮化物(诸如，氮化钛(TiN)、氮化钽(TaN)或氮化钼(MoNx))、金属碳化物(诸如碳化钽(TaC)或碳化铪(HfC))、金属氮碳化物(诸如TaCN)、金属氧化物(诸如氧化钼(MoOx))、金属氮氧化物(诸如氧氮化钼(MoOxNy))、金属硅化物(诸如硅化镍)或以上的组合。栅极电极层设置于多重材料层105的顶上和周围。
栅极介电层可选地可设置于栅极电极层下方和多重材料层105下方。可选的栅极介电层可包括硅氧化物(SiOx)，可通过热氧化第一层106或和/或第二层108的一层或更多层而形成，或通过任何适合的沉积处理形成。用于形成栅极介电层的适合的材料包括氧化硅、氮化硅、氮氧化物、金属氧化物，诸如氧化铪(HfO2)、氧化铪锆(HfZrOx)、氧化铪硅(HfSiOx)、氧化铪钛(HfTiOx)、氧化铪铝(HfAlOx)、以及以上的组合和多层。栅极间隔件形成于栅极电极层的侧壁上。每个栅极间隔件包括氮化物部分和/或氧化物部分。掩模层形成于栅极电极层的顶上，并且可包括氮化硅。
本文描述了在hGAA结构100上的锑掺杂的源极/漏极区域114a、114b的成分和形成。
图2A-图2C根据一个实施方式，图示了图1的hGAA结构100的形成的示意性截面图。使用图3的方法300形成hGAA结构100。本文所述的hGAA结构100为n沟道金属氧化物半导体(NMOS)装置。因此，在hGAA结构100之中的掺杂物为n型掺杂物，诸如磷、砷、锑或以上的任意组合。根据一个实施方式，掺杂物包括磷(P)。
关于图1所述的多重材料层105和栅极结构112在第一操作302期间形成于基板102和可选材料层104上。在第一操作302之后，hGAA结构100类似于图2A中的结构。多重材料层105和栅极结构112的组合在本文可描述为膜堆叠物(film-stack)。在第一操作期间，多重材料层105是如下形成的：使用多个沉积操作来形成多个交替的第一层106和第二层108。回蚀刻(etch back)第二层108的一部分，并且形成间隔件110。
栅极结构112形成在多重材料层105周围。在一些实施方式中，栅极结构112的栅极电极层是与多重材料层105之中第二层108每一层的材料类似的材料。栅极结构112和第二层108在第一层106每层周围形成环绕栅极。第一层106充当设置于环绕栅极之中的纳米线或纳米片。在形成源极/漏极区域之后，第一层106用作源极/漏极区域之间的沟道。
在第一操作302期间形成膜堆叠物之后，如图2B中所示于第二操作304期间形成锑掺杂的源极/漏极区域114a、114b。在第二操作302期间，沉积气体混合物被引入处理腔室中以沉积锑掺杂的源极/漏极区域114a、114b。如图2B中所示，锑掺杂的源极/漏极区域114a、114b被沉积于多重材料层105之中的第一层106每一层和基板102上。锑掺杂的源极/漏极区域114a、114b具有从约1nm至约10nm的范围的厚度。通过外延沉积处理沉积锑掺杂的源极/漏极区域114a、114b，这种外延沉积处理诸如是在外延沉积腔室之中的选择性外延沉积处理。在本文所示的实施方式中，锑掺杂的源极/漏极区域114a、114b被沉积在由晶体材料(诸如Si)制成的基板102的暴露的部分和第一层106上，并且锑掺杂的源极/漏极区域114a、114b未被沉积在由介电材料制成的间隔件110或栅极结构112上。沉积处理可在以下条件下进行：在从约1torr至约600torr(诸如从约200torr至约300torr)的范围的腔室压强，和在小于约550℃(诸如小于约500℃，诸如小于约450℃)的沉积温度(基板的温度)。
使氯化的硅前驱物和含锑(Sb)前驱物共同流入处理腔室中。氯化的硅前驱物包括具有硅和氯两者的前驱物，诸如二氯硅烷(SiCl2H2)(DCS)、三氯硅烷(SiCl3H)(TCS)或这些的任意混合物。在一些实施方式中，使用DCS和TCS的混合物。DCS和TCS的混合物包括处于约1：10至约10：1的比例的DCS与TCS之比的混合物。在一些实施方式中，当DCS存在时已显示TCS仅生长锑掺杂的源极/漏极区域114a、114b，并且当DCS并未一起共同流动时不会形成锑掺杂的源极/漏极区域114a、114b或以显著减少的速率形成锑掺杂的源极/漏极区域114a、114b。已显示DCS提高了锑掺杂的源极/漏极区域114a、114b的生长速率。在一些实施方式中，可以有其他适合的氯化的含硅前驱物。氯化的硅前驱物使得能够生长锑掺杂的源极/漏极区域114a、114b。随着锑掺杂的源极/漏极区域114a、114b生长，未进行回蚀刻操作。已显示氯化的硅前驱物之中的氯改进了外延层的晶体生长而并无额外的回蚀刻处理。氯化的含硅前驱物可具有从约1sccm至约1000sccm的范围的流量，诸如1sccm至约500sccm，或10sccm至约1000sccm。在本文所述的实施方式中，DCS或TCS每种的流量具有从约1sccm至约1000sccm的范围的流量，诸如1sccm至约500sccm，或10sccm至约1000sccm。
含锑前驱物包括以下的一种或组合：
Figure BDA0004113654540000071
(stibine；SbH3)、三氯化锑(SbCl3)、四氯化锑(SbCl4)、五氯化锑(SbCl5)、三苯基锑((C6H5)3Sb)、三氢化锑(SbH3)、三氧化二锑(Sb2O3)、五氧化二锑(Sb2O5)、三氟化锑(SbF3)、三溴化锑(SbBr3)、三碘化锑(antimonytriiodide；Sbl3)、五氟化锑(SbF5)、三乙基锑(C6H15Sb)(TESb)和三甲基锑(TMSb)。在本文所述的实施方式中，使用TESb。含锑前驱物可具有从约0.1sccm至约100sccm的范围的流量。在一些实施方式中，诸如氮气(N2)或氢气(H2)之类的载气可与氯化的含硅前驱物和含砷前驱物一起流动。在本文所述的操作中，没有额外的蚀刻剂与含半导体前驱物和含锑前驱物一起流动以进行选择性的回蚀刻。
在锑掺杂的源极/漏极区域114a、114b中过度点缺陷(excessive point defect)的量可通过改变处理条件而得到控制，这些处理条件诸如是这些前驱物的分压、这些前驱物的比例、处理温度和/或层厚度。在锑掺杂的源极/漏极区域114a、114b中过度点缺陷的量可控制Sb原子扩散至多重材料层105的第一层106中。在锑掺杂的源极/漏极区域114a、114b的沉积期间，Sb原子可扩散至多重材料层105的第一层106中。使用含P前驱物将P掺杂物添加至锑掺杂的源极/漏极区域114a、114b。含P前驱物同时流动至氯化的含硅前驱物和含锑前驱物两者。锑掺杂的源极/漏极区域114a、114b的电阻率为约0.8mΩ·cm，而P掺杂的锑掺杂的半导体层的电阻率进一步减少至约0.5mΩ·cm至约0.6mΩ·cm。在本文所述的范例中，含P前驱物为磷化氢(PH3)。
使氯化的含硅前驱物、含砷前驱物和含P前驱物每一种同时共同流入处理腔室中。使氯化的含硅前驱物、含砷前驱物和含P前驱物每一种共同流入改进了锑掺杂的源极/漏极区域114a、114b的导电性，并且使得沉积温度能够小于550℃。在一些实施方式中，含P前驱物为通用的n型掺杂物前驱物。在本文所述的实施方式中，流入处理腔室中的氯化的含硅前驱物与含砷前驱物、与含P前驱物之比为约5：1：5至约20：1：20。如本文所述，氯化的含硅前驱物与含砷前驱物、与含P前驱物之比可为DCS和TCS与TESb、与PH3之比。
沉积的锑掺杂的源极/漏极区域114a、114b具有大于约5x1020原子/cm3的锑浓度，诸如大于约1x1021原子/cm3，诸如大于约2x1021原子/cm3。在沉积的锑掺杂的源极/漏极区域114a、114b之中磷掺杂物浓度为约1x1020原子/cm3至约5x1021原子/cm3。，锑掺杂的源极/漏极区域114a、114b的低温沉积进一步降低了锑迁移到多重材料层105和基板的其他部分中的迁移，因为锑扩散可造成性能的劣化。
在锑掺杂的源极/漏极区域114a、114b之中锑掺杂物的浓度改变锑掺杂的源极/漏极区域114a、114b的生长速率。已发现的是，在锑掺杂物的较低浓度的条件下或在没有锑掺杂物的共同流动的实施方式中，在小于550℃的温度下的锑掺杂的源极/漏极区域114a、114b的沉积速率大幅降低。在一些实施方式中，已发现相较于没有任何含锑前驱物的处理，锑掺杂的源极/漏极区域114a、114b之中锑的浓度以超过两倍的生长速率提高了沉积速率。在一些实施方式中，在没有含锑前驱物和氯化的含硅前驱物两者的同时共同流动的情况下，在小于550℃的温度下，锑掺杂的源极/漏极区域114a、114b的生长速率在基板的晶体位置和非晶体位置两者上接近为零。含锑前驱物之中的锑易于(act to)降低第一层106的表面活化能，使得形成锑掺杂的源极/漏极区域114a、114b。锑掺杂的源极/漏极区域114a、114b的生长速率对晶体结构是高度选择性的，使得在第一层106上锑掺杂的源极/漏极区域114a、114b的生长速率大于在间隔件110和栅极结构112上锑掺杂的源极/漏极区域114a、114b的生长速率的约100倍，例如大于该生长速率的约150倍。在一些实施方式中，锑掺杂的源极/漏极区域114a、114b的生长速率为约10埃/分钟至约20埃/分钟。
在本文所述的处理期间，锑掺杂的源极/漏极区域114a、114b的生长速率主要沿着<110>方向，使得沿着<110>方向的锑掺杂的源极/漏极区域114a、114b的生长速率比沿<100>或<111>方向任一方向的生长速率高出大于50％，诸如比沿<100>或<111>方向任一方向的生长速率高出大于100％。沿<110>方向相较于<100>或<111>方向的高的生长速率减少了锑掺杂的源极/漏极区域114a、114b的切刻，并且允许锑掺杂的源极/漏极区域114a、114b从第一层106的表面的连续生长。
锑掺杂的源极/漏极区域114a、114b的选择性沉积和锑掺杂的源极/漏极区域114a、114b的方向性生长速率在间隔件110与锑掺杂的源极/漏极区域114a、114b之间形成间隙111。间隙111为气隙，并且将间隔件110和锑掺杂的源极/漏极区域114a、114b分开，以进一步将间隔件110与源极/漏极116a、116b隔离。在第一层106与锑掺杂的源极/漏极区域114a、114b之间的接触电阻为约0.3mΩ-·cm2至约3mΩ-·cm2。
在一些实施方式中，在第一处理腔室中进行锑掺杂的源极/漏极区域114a、114b的沉积，并且在第二处理腔室中进行以P对锑掺杂的源极/漏极区域114a、114b的掺杂。在其他实施方式中，锑掺杂的源极/漏极区域114a、114b的形成和锑掺杂的源极/漏极区域114a、114b的掺杂是在一个腔室中进行的。
在第二操作304之后，进行热处置hGAA结构100的第三操作306。hGAA结构的热处置为尖峰退火(spike anneal)处理。尖峰退火处理在约900℃至约1200℃的温度下进行约1秒至约30秒的时间。由于Sb原子的大尺寸的缘故，Sb原子不会以P掺杂物相同的速率扩散。尖峰退火的短时段因此抑制了Sb原子扩散，同时使得一些P掺杂物能在第一层106中扩散以形成如图2C中所示的多重材料层105的第一层106的掺杂区域120。
由于第二和第三操作的温度保持低于约550℃，减少了掺杂物的扩散和多重材料层105的翘曲(warpage)。
在锑掺杂的源极/漏极区域114a、114b形成之后，可选地可以在hGAA结构100之上沉积覆盖层(未显示)。覆盖层为含硅层，并且沉积在锑掺杂的源极/漏极区域114a、114b和间隔件110每个的顶上，使得覆盖层填充间隙111。
尽管以上涉及本公开内容的实施方式，但可在不悖离本公开内容的基本范围的情况下设计本公开内容的其他和进一步实施方式，并且本公开内容的范围通过随附的权利要求书来确定。

Claims (20)

1.一种形成半导体装置的方法，包括以下步骤：
在基板上形成多重材料层，其中所述多重材料层包括以交替图案布置的多个晶体第一层和多个非晶体第二层；和
在所述基板的所述多个晶体第一层上选择性地形成源极区域和漏极区域，其中形成的所述源极区域和所述漏极区域含有大于约5x1020原子/cm3的锑浓度，形成所述源极区域和所述漏极区域的步骤进一步包含以下步骤：
流动氯化的含硅前驱物；
与所述氯化的含硅前驱物共同流动含锑前驱物；
与所述氯化的含硅前驱物和所述含锑前驱物共同流动n型掺杂前驱
物；和
加热所述基板至小于约550℃的温度。
2.如权利要求1所述的方法，其中所述n型掺杂前驱物为含磷前驱物。
3.如权利要求1所述的方法，其中在所述源极区域和所述漏极区域之中的所述锑浓度为大于约2x1021原子/cm3。
4.如权利要求1所述的方法，其中在所述多个晶体第一层上所述源极区域和所述漏极区域的生长速率大于在所述多个非晶体第二层上的生长速率的约50倍。
5.如权利要求4所述的方法，其中所述多个非晶体第二层进一步包括设置在所述多个非晶体第二层外部部分上的介电间隔件。
6.如权利要求5所述的方法，其中在所述源极区域和所述漏极区域的选择性形成期间，相邻于所述多个非晶体第二层形成多个间隙。
7.如权利要求1所述的方法，其中所述氯化的含硅前驱物为二氯硅烷和三氯硅烷的一种或组合。
8.如权利要求7所述的方法，其中所述含锑前驱物为以下一种或组合：
Figure FDA0004113654530000021
三氯化锑、四氯化锑、五氯化锑、三苯基锑、三氢化锑、三氧化二锑、五氧化二锑、三氟化锑、三溴化锑、三碘化锑、五氟化锑、三乙基锑和三甲基锑。
9.如权利要求8所述的方法，其中所述含锑前驱物为三乙基锑。
10.一种半导体装置，包括：
多重材料层，包括：
多个第一层，包括晶体硅材料；和
多个第二层，包括金属材料和在所述金属材料的外表面上的高k材料，所述多个第二层与所述多个第一层以交替图案布置；
源极区域；和
漏极区域，其中所述源极区域和所述漏极区域为外延层，并且包括硅材料、锑掺杂物和n型掺杂物。
11.如权利要求10所述的半导体装置，其中所述n型掺杂物为以下一种或组合：氮、磷、砷或锑。
12.如权利要求11所述的半导体装置，其中所述n型掺杂物为磷。
13.如权利要求10所述的半导体装置，其中所述锑掺杂物具有大于约5x1020原子/cm3的浓度。
14.如权利要求10所述的半导体装置，其中所述多个第二层每层为栅极结构的一部分。
15.如权利要求10所述的半导体装置，其中介电间隔件形成在所述多个第二层的所述外端上。
16.如权利要求10所述的半导体装置，其中所述多个第一层形成纳米片或纳米线。
17.一种形成半导体装置的方法，包括以下步骤：
沿主要是<110>方向在基板上选择性地生长源极区域和漏极区域，其中所述源极区域和所述漏极区域含有大于约5x1020原子/cm3的锑浓度，选择性地生长所述源极区域和所述漏极区域的步骤进一步包括以下步骤：
使氯化的含硅前驱物流入具有所述基板的处理腔室中；
使含锑前驱物与所述氯化的含硅前驱物共同流入所述处理腔室中；
使磷掺杂前驱物与所述氯化的含硅前驱物和所述含锑前驱物共同流入所述处理腔室中；和
在所述氯化的含硅前驱物、所述含锑前驱物和所述磷掺杂前驱物的流动期间，加热所述基板至小于约550℃的温度。
18.如权利要求17所述的方法，其中多重材料层设置于基板上，并且所述多重材料层包括以交替图案布置的多个晶体第一层和多个非晶体第二层，所述源极区域和所述漏极区域在所述多个晶体第一层上被选择性地生长。
19.如权利要求17所述的方法，其中所述氯化的含硅前驱物为二氯硅烷和三氯硅烷的一种或组合，并且所述含锑前驱物为三乙基锑。
20.如权利要求17所述的方法，其中所述源极区域和所述漏极区域的生长速率为约10埃/分钟至约20埃/分钟。
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