CN116259607A - Semiconductor test structure and forming method thereof - Google Patents

Semiconductor test structure and forming method thereof Download PDF

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Publication number
CN116259607A
CN116259607A CN202111458694.XA CN202111458694A CN116259607A CN 116259607 A CN116259607 A CN 116259607A CN 202111458694 A CN202111458694 A CN 202111458694A CN 116259607 A CN116259607 A CN 116259607A
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tested
dielectric
ring
dielectric layer
annular
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韩兆翔
范伟海
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/2601—Apparatus or methods therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/564—Details not otherwise provided for, e.g. protection against moisture

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  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

A semiconductor test structure and a method of forming the same, wherein the semiconductor test structure comprises: a substrate; an interlayer dielectric layer on the substrate; a structure to be tested located in the interlayer dielectric layer; the annular structure is positioned in the interlayer dielectric layer, the annular structure surrounds the structure to be detected, the top surface of the annular structure is flush with the top surface of the structure to be detected, and the bottom surface of the annular structure is lower than the bottom surface of the structure to be detected; and an opening in the annular structure, the opening extending through the annular structure in a direction perpendicular to a top surface of the annular structure. The semiconductor test structure reduces the intrusion of water vapor around the test part and improves the authenticity and accuracy of the electromigration test result.

Description

Semiconductor test structure and forming method thereof
Technical Field
The present disclosure relates to semiconductor manufacturing technology, and more particularly, to a semiconductor test structure and a method for forming the same.
Background
In the reliability test of the semiconductor package level, an Electromigration (EM) test judges the reliability of a semiconductor test part by detecting the occurrence of voids (void) or protrusions (hillock) of the semiconductor test part under the action of an electric field.
In the electromigration test, after being cut and packaged, the semiconductor test component enters a tester for testing. However, the semiconductor test part has a certain exposure time from dicing to testing, and in this process, the electromigration performance of the semiconductor test part is deteriorated due to the fact that external moisture easily invades the semiconductor test part, thereby seriously affecting the authenticity and accuracy of the electromigration test.
Currently, only in some advanced process technologies below 28 nm, moisture intrusion can be prevented by creating a totally enclosed guard ring structure around the entire semiconductor test part, and such semiconductor test structures are expensive to manufacture. In addition, for the preparation technology of semiconductor test structures in general manufacturing processes, the problem that the semiconductor test components are invaded by water vapor still cannot be solved, so that the authenticity and accuracy of electromigration test are affected.
Disclosure of Invention
The invention solves the technical problem of providing a semiconductor test structure and a forming method thereof, which reduces the invasion of water vapor around a semiconductor test part and improves the authenticity and accuracy of electromigration test.
In order to solve the above technical problems, the present invention provides a semiconductor test structure, comprising: a substrate; an interlayer dielectric layer on the substrate; a structure to be tested located in the interlayer dielectric layer; the annular structure is positioned in the interlayer dielectric layer, the annular structure surrounds the structure to be detected, the top surface of the annular structure is flush with the top surface of the structure to be detected, and the bottom surface of the annular structure is lower than the bottom surface of the structure to be detected; and an opening in the annular structure, the opening extending through the annular structure in a direction perpendicular to a top surface of the annular structure.
Optionally, the structure to be tested includes a structure to be tested.
Optionally, a test ring structure located between the structure to be tested and the annular structure, the test ring structure surrounding the structure to be tested.
Optionally, the to-be-tested line structure includes an inner layer to-be-tested line structure and an outer layer to-be-tested line structure located on the surface of the inner layer to-be-tested line structure.
Optionally, the material of the inner layer to-be-tested line structure comprises copper; the constituent materials of the outer layer to-be-tested line structure comprise one or a combination of tantalum and tantalum nitride. .
Optionally, the number of the ring structures is equal to 1 or 2.
Alternatively, when the number of the annular structures is equal to 2, the annular structures are arranged in a concentric surrounding structure.
Optionally, the annular structure includes a connection ring and a virtual ring located on a top surface of the connection ring, the top surface of the virtual ring is flush with the top surface of the structure to be tested, and the bottom surface of the virtual ring is flush with the bottom surface of the structure to be tested.
Optionally, the material of the ring structure comprises copper.
Optionally, the interlayer dielectric layer includes: a first dielectric structure located on the substrate, a second dielectric structure located on the first dielectric structure, and a third dielectric structure located on the second dielectric structure; the structure to be tested and the annular structure are located in the second medium structure.
Optionally, the second medium structure includes: the first dielectric layer is arranged on the first dielectric structure, the second dielectric layer is arranged on the first dielectric layer, and the top surface of the first dielectric layer is higher than the bottom surface of the annular structure.
Optionally, the material of the first dielectric structure includes a low-k material or an ultra-low-k material; the material of the first dielectric layer comprises a low-k material or an ultra-low-k material; the material of the second dielectric layer comprises a low-k material or an ultra-low-k material; the k value of the low-k material is less than 3, and the k value of the ultra-low-k material is less than 2.5.
Optionally, the material of the first barrier layer includes nitride.
Optionally, the semiconductor test structure further includes: and the electrical interconnection structure is positioned in the first dielectric structure and is electrically connected with the structure to be tested.
Optionally, the third medium structure includes: a second barrier layer on the second dielectric structure and a third dielectric layer on the second barrier layer, wherein the bottom surface of the second barrier layer is flush with the top surface of the annular structure.
Optionally, the material of the second barrier layer includes nitride.
Optionally, the material of the third dielectric layer includes a low-k material or an ultra-low-k material; the k value of the low-k material is less than 3, and the k value of the ultra-low-k material is less than 2.5.
Optionally, the semiconductor test structure further includes: and the electrical interconnection structure is positioned in the third dielectric layer and is electrically connected with the structure to be tested.
Optionally, the substrate includes a base, a device layer on the base, and an interconnect layer connecting the device layer.
Correspondingly, the invention also provides a method for forming the semiconductor test structure, which comprises the following steps: providing a substrate; the method comprises the steps of forming an interlayer dielectric layer, a structure to be tested located in the interlayer dielectric layer and an annular structure located in the interlayer dielectric layer on a substrate, wherein the annular structure surrounds the structure to be tested, the top surface of the annular structure is flush with the top surface of the structure to be tested, the bottom surface of the annular structure is lower than the bottom surface of the structure to be tested, an opening is formed in the annular structure, and the opening penetrates through the annular structure along the direction perpendicular to the top surface of the annular structure.
Optionally, the interlayer dielectric layer includes: a first dielectric structure located on the substrate, a second dielectric structure located on the first dielectric structure, and a third dielectric structure located on the second dielectric structure; the structure to be tested and the annular structure are located in the second medium structure.
Optionally, the forming method of the interlayer dielectric layer, the structure to be tested and the annular structure includes: forming a first dielectric structure on the substrate; forming a second medium structure on the first medium structure, and the structure to be tested and the annular structure which are positioned in the second medium structure; and forming a third medium structure on the second medium structure, the structure to be tested and the annular structure.
Optionally, the second medium structure includes: the first dielectric layer is arranged on the first dielectric structure, the second dielectric layer is arranged on the first dielectric layer, and the bottom surface of the annular structure is lower than the top surface of the first dielectric layer.
Optionally, the third medium structure includes: a second barrier layer on the second dielectric structure and a third dielectric layer on the second barrier layer, wherein the bottom surface of the second barrier layer is flush with the top surface of the annular structure.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
in the semiconductor test structure, the annular structure surrounds the structure to be tested, the top surface of the annular structure is flush with the top surface of the structure to be tested, and the bottom surface of the annular structure is lower than the bottom surface of the structure to be tested. Therefore, the annular structure surrounds the peripheral side surfaces of the structure to be tested, the annular structure blocks water vapor which invades from the side surfaces of the structure to be tested in the interlayer dielectric layer, the influence on electromigration performance of the structure to be tested due to the invasion of the water vapor is reduced, and the authenticity and accuracy of electromigration test results are improved. In addition, the annular structure is purposefully added to the water vapor sensitive test part, and a totally-enclosed protection structure does not need to be established around all the test parts, so that the preparation cost is saved, and the universality of the preparation process is improved. In addition, in the chemical mechanical polishing process in the preparation process of the semiconductor test structure, the annular structure is better in rigidity and larger in surface area, and can provide better mechanical support for the structure to be tested from all directions around, so that the polishing effect of the chemical mechanical polishing process is improved, and the situation that cracks appear in the semiconductor test structure in the process of receiving cutting is effectively reduced.
Further, the number of the ring structures is equal to 1 or 2. By increasing the number of the annular structures, a multi-layer blocking structure can be formed around the structure to be tested, so that the situation that external water vapor invades the structure to be tested from the side face is better reduced, and the authenticity and accuracy of an electromigration test result are further improved.
In the preparation method of the semiconductor test structure, the annular structure surrounding the structure to be tested is formed, the top surface of the annular structure is flush with the top surface of the structure to be tested, and the bottom surface of the annular structure is lower than the bottom surface of the structure to be tested, so that water vapor invaded from the side surface of the structure to be tested is blocked, the influence of the water vapor invasion on electromigration performance of the structure to be tested is reduced, and the authenticity and accuracy of electromigration test results are improved.
Drawings
FIGS. 1 and 2 are schematic diagrams of an embodiment of a semiconductor test structure;
FIGS. 3-7 are schematic diagrams illustrating a semiconductor test structure forming process according to an embodiment of the invention;
fig. 8 and 9 are schematic diagrams illustrating a process of forming a semiconductor test structure according to another embodiment of the present invention.
Detailed Description
As described in the background, in some prior art processes, moisture intrusion can be prevented by creating a fully enclosed guard ring structure around the entire semiconductor test part, and such semiconductor test structures are expensive to manufacture. In addition, for the preparation technology of semiconductor test structures in general manufacturing processes, the problem that the semiconductor test components are invaded by water vapor still cannot be solved, so that the authenticity and accuracy of electromigration test are affected.
Fig. 1 and 2 are schematic structural diagrams of an embodiment of a semiconductor test structure, fig. 1 is a top view of fig. 2 along a P direction, and fig. 2 is a schematic sectional structural diagram of fig. 1 along an AA' direction.
Referring to fig. 1 and 2, the semiconductor test structure includes: the structure to be tested 100, wherein the structure to be tested 100 comprises a copper layer 104 and a tantalum layer 105 positioned on the surface of the copper layer 104; a plurality of virtual lines 101 positioned outside the structure to be tested 100, wherein the virtual lines 101 are placed in parallel with the structure to be tested 100; an upper barrier layer 106 located above the structure to be tested 100, wherein a bottom surface of the upper barrier layer 106 contacts a top surface of the structure to be tested 100; a lower barrier layer 107 located under the structure to be tested 100, wherein a top surface of the lower barrier layer 107 is lower than a bottom surface of the structure to be tested 100; an interlayer dielectric layer 103 located between the upper barrier layer 106 and the lower barrier layer 107.
It should be noted that the top view shown in fig. 1 does not include upper barrier layer 106 and lower barrier layer 107 for ease of understanding.
In electromigration testing, the semiconductor test structure has a certain exposure time from dicing to testing. In this process, the water vapor in the external environment enters the interlayer dielectric layer 103, and since the side surface and the bottom surface of the structure to be tested 100 are in contact with the interlayer dielectric layer 103, the water vapor that invades from the side surface of the interlayer dielectric layer 103 is easy to diffuse to the side surface and the bottom surface of the structure to be tested 100. The tantalum layer 105 on the surface of the structure to be tested 100 is oxidized after being contacted with water vapor, so that the interface scattering between the copper layer 104 and the tantalum layer 105 is enhanced, and the electromigration performance of the whole structure to be tested 100 is deteriorated. In addition, when water vapor passes through the tantalum layer 105 and then enters the copper layer 104, the copper layer 104 is oxidized, a compact structure of metallic copper is damaged, a loose copper oxide structure is formed, electrons are more easily migrated, and thus the electromigration performance of the whole structure 100 to be tested is poor, and the authenticity and accuracy of the electromigration test are affected.
In order to solve the above problems, the present invention provides a semiconductor test structure, which includes a ring structure surrounding the structure to be tested, wherein the ring structure blocks water vapor from entering the structure to be tested from the side surface of the structure to be tested, thereby greatly reducing the influence of water vapor invasion on the performance of the structure to be tested and improving the authenticity and accuracy of the electromigration test result.
In order to solve the problems, the invention provides a method for forming a semiconductor test structure, which forms a ring-shaped structure surrounding a structure to be tested, so that the ring-shaped structure blocks water vapor which invades the structure to be tested from the side surface of the structure to be tested, thereby greatly reducing the influence of water vapor invasion on the performance of the structure to be tested and improving the authenticity and accuracy of an electromigration test result.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 6 are schematic structural diagrams illustrating a semiconductor test structure forming process according to an embodiment of the invention.
Referring to fig. 3, a substrate 260 is provided; a first dielectric structure 251 is formed over the substrate 260.
In this embodiment, the material of the substrate 260 is a semiconductor material. Specifically, the material of the substrate 260 includes silicon. In other embodiments, the substrate 260 may comprise silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), or the like.
In other embodiments, the substrate includes a base, a device layer on the base, and an interconnect layer connecting the device layers.
In this embodiment, the constituent material of the first dielectric structure 251 includes a low-k material or an ultra-low-k material; the k value of the low-k material is less than 3, and the k value of the ultra-low-k material is less than 2.5. The forming process of the first dielectric structure 251 includes chemical vapor deposition or physical vapor deposition.
Referring to fig. 4 and 5, fig. 4 is a cross-sectional view along BB 'of fig. 5, fig. 5 is a top view along X' of fig. 4, a second dielectric structure 252 is formed on the first dielectric structure 251, and the structure under test 200 and the ring-shaped structure 201 are located in the second dielectric structure 252, the ring-shaped structure 201 surrounds the structure under test 200, the top surface of the ring-shaped structure 201 is flush with the top surface of the structure under test 200, the bottom surface of the ring-shaped structure 201 is lower than the bottom surface of the structure under test 200, an opening 204 is formed in the ring-shaped structure 201, and the opening 204 penetrates through the ring-shaped structure 201 along a direction perpendicular to the top surface of the ring-shaped structure 201.
In this embodiment, the second medium structure 252 includes: a first barrier layer 221, a first dielectric layer 231 on the first barrier layer 221, and a second dielectric layer 232 on the first dielectric layer 231.
In this embodiment, the method for forming a semiconductor test structure further includes: a test ring structure 205 is formed within the second dielectric structure 252 between the structure under test 200 and the ring structure 201, the test ring structure 205 surrounding the structure under test 200.
In this embodiment, the ring structure 201 includes a connection ring 207 and a virtual ring 206 located on a top surface of the connection ring 207.
The forming method of the second dielectric structure 252, the ring-shaped structure 201, the structure to be tested 200 and the test ring structure 205 includes: forming the first barrier layer 221 on the first dielectric structure 251; forming a first dielectric layer 231 on the first barrier layer 221; forming a first annular trench penetrating the first dielectric layer 231 and the first barrier layer 221 in the first dielectric layer 231 and the first barrier layer 221, wherein the first annular trench exposes the top surface of the first dielectric structure 251; forming a connection ring 207 within the first annular groove; forming a second dielectric layer 232 on the connection ring 207 and the first dielectric layer 231; forming a second annular groove, a third annular groove and a first channel in the second dielectric layer 232, wherein the second annular groove is positioned on the connecting ring, the first channel is positioned at the center of a region surrounded by the second annular groove, and the third annular groove is positioned between the first channel and the second annular groove; forming a structure to be tested 200 filling the first channel in the first channel; forming a virtual ring 206 in the second annular groove, wherein the bottom surface of the virtual ring 206 is in contact with the top surface of the connecting ring 207, an opening 204 is formed in an annular structure 201 formed by the connecting ring 207 and the virtual ring 206, and the opening 204 penetrates through the annular structure 201 along the direction perpendicular to the top surface of the annular structure 201; a test ring structure 205 filling the third annular trench is formed in the third annular trench.
In this embodiment, the constituent material of the first barrier layer 221 includes nitride. The first barrier layer 221 is formed by a process including chemical vapor deposition or physical vapor deposition.
The first dielectric layer 231 includes a low-k material or an ultra-low-k material; the k value of the low-k material is less than 3, and the k value of the ultra-low-k material is less than 2.5. The forming process of the first dielectric layer 231 includes chemical vapor deposition or physical vapor deposition. The second dielectric layer 232 is made of a low-k material or an ultra-low-k material; the second dielectric layer 232 is formed by a process including chemical vapor deposition or physical vapor deposition.
The forming step of the first annular groove comprises the following steps: forming a first photoresist pattern layer (not shown) on the surface of the first dielectric layer 231; the first dielectric layer 231 and the first barrier layer 221 are etched using the first photoresist pattern layer as a mask until the top surface of the first dielectric structure 251 is exposed, thereby forming a first annular trench penetrating the first dielectric layer 231 and the first barrier layer 221.
In this embodiment, the process of etching the first dielectric layer 231 and the first barrier layer 221 is an anisotropic dry etching process.
In this embodiment, the formation process of the connection ring 207 includes chemical vapor deposition or physical vapor deposition. The material of construction of the connection ring 207 includes copper.
In this embodiment, the bottom surface of the connecting ring 207 is lower than the top surface of the first barrier 221. In other embodiments, the connecting ring bottom surface is flush with the top surface of the first barrier layer.
In this embodiment, the forming steps of the second annular groove, the third annular groove, and the first channel include: forming a second photoresist pattern layer (not shown) on the surface of the second dielectric layer 232; and etching the second dielectric layer 232 by using the second photoresist pattern layer as a mask, thereby forming a second annular groove, a third annular groove and a first channel penetrating the second dielectric layer 232, wherein the second annular groove exposes the top surface of the connection ring 207 and the top surface of the first dielectric layer 231, and the third annular groove and the first channel expose the top surface of the first dielectric layer 231.
In this embodiment, the process of etching the second dielectric layer 232 is an anisotropic dry etching process.
In this embodiment, the forming process of the dummy ring 206 includes chemical vapor deposition or physical vapor deposition. The dummy ring 206 is comprised of a material comprising copper.
Because the virtual ring 206 and the connection ring 207 are located in different layers, the preparation processes of the virtual ring 206 and the connection ring 207 are the same or different, and the materials of the virtual ring 206 and the connection ring 207 are the same or different, so that the ring structure 201 can be applied to more test structures of semiconductor devices, and meanwhile, the preparation process of the ring structure 201 can be more flexible, thereby expanding the application range of the formation method of the semiconductor test structure.
In this embodiment, the structure to be tested 200 includes a structure to be tested, and specifically, the structure to be tested is a metal interconnect line. The to-be-tested line structure comprises an inner-layer to-be-tested line structure (not shown) and an outer-layer to-be-tested line structure (not shown) positioned on the surface of the inner-layer to-be-tested line structure.
The forming steps of the structure to be tested 200 include: forming an outer-layer to-be-tested line structure covering the side wall and the bottom surface of the first channel in the first channel; and forming an inner layer to-be-measured line structure filled in the first channel on the surface of the outer layer to-be-measured line structure, thereby forming the to-be-measured structure 200.
The material of the inner layer to-be-measured line structure comprises copper, and the material of the outer layer to-be-measured line structure comprises tantalum. Because tantalum has good conductivity and capability of blocking other atoms, and tantalum has good inertness to copper, an outer layer to-be-measured line structure formed by tantalum is covered on the surface of an inner layer to-be-measured line structure formed by copper, so that the outer layer to-be-measured line structure is used as a blocking layer to block copper diffusion, and the to-be-measured structure 200 has good electrical performance. In other embodiments, the constituent materials of the outer-layer under-test line structure include tantalum nitride or a combination of tantalum and tantalum nitride.
In this embodiment, the length of the structure under test 200 ranges from 300 micrometers to 500 micrometers, and the width of the structure under test 200 ranges from 0.1 micrometers to 5 micrometers.
In this embodiment, the pattern of the virtual ring 206 projected on the top surface of the substrate 260 in the ring structure 201 is denoted as a virtual ring projection pattern, the virtual ring projection pattern is a rectangular ring, and the rectangular ring width range of the virtual ring projection pattern includes 0.1 micrometer to 5 micrometers. The pattern projected by the structure under test 200 on the top surface of the substrate 260 is surrounded by the virtual ring projected pattern.
In this embodiment, the top surface of the virtual ring 206 is flush with the top surface of the structure under test 200, and the bottom surface of the virtual ring 206 is flush with the bottom surface of the structure under test 200.
In this embodiment, the pattern of the ring structure 201 projected by the connection ring 207 on the top surface of the substrate 260 is denoted as a connection ring projection pattern, the connection ring projection pattern is a rectangular ring, and the connection ring 207 projection pattern is located within the range of the virtual ring 206 projection pattern. The rectangular ring width range of the connecting ring projection pattern comprises 0.1-5 microns, and the rectangular ring width of the connecting ring projection pattern is smaller than that of the virtual ring projection pattern.
In other embodiments, the patterns projected on the surface of the substrate by the virtual ring and the connection ring comprise a circular ring, and the pattern projected on the surface of the substrate by the structure to be tested is positioned at the center of the circular ring.
In this embodiment, the ring-shaped structure 201 formed by the connection ring 207 and the virtual ring 206 surrounds the structure to be tested 200, the top surface of the ring-shaped structure 201 is flush with the top surface of the structure to be tested 200, and the bottom surface of the ring-shaped structure 201 is lower than the bottom surface of the structure to be tested 200.
In this embodiment, the number of the annular structures 201 is equal to 2, each annular structure 201 is arranged in a concentric surrounding structure, each annular structure 201 jointly surrounds the structure to be measured 200, the structure to be measured 200 is located at the center of the concentric surrounding structure, and the projection of each annular structure 201 on the top surface of the substrate 260 is a rectangular ring.
In other embodiments, the number of ring structures is equal to 1.
In this embodiment, the test ring structure 205 is located between the structure under test 200 and the ring structure 201, and the test ring structure 205 surrounds the structure under test 200. The constituent materials of the test ring structure 205 include copper; the test ring structure 205 is formed by a process including chemical vapor deposition or physical vapor deposition.
Referring to fig. 6 and 7, fig. 6 is a cross-sectional view of fig. 7 along the direction CC', fig. 7 is a top view of fig. 6 along the direction X, and a third dielectric structure 253 is formed on the second dielectric structure 252, the structure under test 200, the ring-shaped structure 201, and the test ring structure 205.
In this embodiment, the third medium structure 253 includes: a second barrier layer 222 on the second dielectric structure 252 and a third dielectric layer 243 on the second barrier layer 222.
In this embodiment, the bottom surface of the second barrier layer 222 is flush with the top surface of the ring-shaped structure 201. The constituent material of the second barrier layer 222 includes nitride. The second barrier layer 222 is formed by a process including chemical vapor deposition or physical vapor deposition.
The third dielectric layer 243 is made of a low-k material or an ultra-low-k material; the k value of the low-k material is less than 3, and the k value of the ultra-low-k material is less than 2.5. The forming process of the third dielectric layer 243 includes chemical vapor deposition or physical vapor deposition.
In this embodiment, the semiconductor test structure further includes: after forming the third dielectric layer 243, an electrical interconnect structure 203 is formed within the third dielectric layer 243, the electrical interconnect structure 203 being electrically connected to the structure under test 200.
The third dielectric layer 243 includes a first region (not shown) of the third dielectric layer located on the second barrier layer 222 and a second region (not shown) of the third dielectric layer located on the first region of the third dielectric layer.
The forming step of the electrical interconnection structure 203 includes: after the second barrier layer 222 is formed, a third dielectric layer first region is formed on the second barrier layer 222, and a conductive plug 208 is formed in the third dielectric layer first region, wherein the conductive plug 208 penetrates through the second barrier layer 222, and one end of the conductive plug 208 is connected with the structure 200 to be tested; forming a third dielectric layer second region on the third dielectric layer first region; an electrical interconnection structure 203 is formed in the second region of the third dielectric layer, the electrical interconnection structure 203 is connected to the other end of the conductive plug 208, and the electrical interconnection structure 203 is electrically connected to the structure to be tested 200 through the conductive plug 208.
In this embodiment, the conductive plugs 208 are made of copper or tungsten, and the formation process of the conductive plugs 208 includes chemical vapor deposition or physical vapor deposition.
The material of the electrical interconnection structure 203 includes copper, and the formation process of the electrical interconnection structure 203 includes chemical vapor deposition or physical vapor deposition.
It should be noted that the top view shown in fig. 7 does not include the third dielectric structure 253 for ease of understanding.
Correspondingly, the embodiment of the invention also provides a semiconductor test structure.
With continued reference to fig. 6 and 7, the semiconductor test structure includes: a substrate 260; an interlayer dielectric layer 202 on the substrate 260; a structure under test 200 located within an interlayer dielectric layer 202; a ring-shaped structure 201 located in the interlayer dielectric layer 202, the ring-shaped structure 201 surrounding the structure to be tested 200, the top surface of the ring-shaped structure 201 being flush with the top surface of the structure to be tested 200, the bottom surface of the ring-shaped structure 201 being lower than the bottom surface of the structure to be tested 200; an opening 204 in the annular structure 201, the opening 204 extending through the annular structure 201 in a direction perpendicular to the top surface of the annular structure 201.
In this embodiment, the substrate 260 provides a process platform for the interlayer dielectric layer 202, the ring-shaped structure 201, and the structure under test 200. The substrate 260 is composed of a material including silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), and the like.
In other embodiments, the substrate includes a base, a device layer on the base, and an interconnect layer connecting the device layers.
In this embodiment, the structure to be tested 200 includes a structure to be tested, and specifically, the structure to be tested is a metal interconnect line. In the semiconductor reliability test, the electrical reliability of the structure under test 200 is determined by performing an electromigration test on the structure under test 200.
The to-be-tested line structure comprises an inner-layer to-be-tested line structure (not shown) and an outer-layer to-be-tested line structure (not shown) positioned on the surface of the inner-layer to-be-tested line structure. The material of the inner layer to-be-measured line structure comprises copper, and the material of the outer layer to-be-measured line structure comprises tantalum. Because tantalum has good conductivity and capability of blocking other atoms, and tantalum has good inertness to copper, an outer layer to-be-measured line structure formed by tantalum is covered on the surface of an inner layer to-be-measured line structure formed by copper, so that the outer layer to-be-measured line structure is used as a blocking layer to block copper diffusion, and the to-be-measured structure 200 has good electrical performance.
In other embodiments, the constituent materials of the outer-layer under-test line structure include tantalum nitride or a combination of tantalum and tantalum nitride.
In this embodiment, the length of the structure under test 200 ranges from 300 micrometers to 500 micrometers, and the width of the structure under test 200 ranges from 0.1 micrometers to 5 micrometers.
With continued reference to fig. 6 and 7, the ring-shaped structure 201 surrounds the structure under test 200.
In this embodiment, the ring-shaped structure 201 is projected on the top surface of the substrate 260 in the shape of a rectangular ring. The pattern of the structure under test 200 projected on the top surface of the substrate 260 is surrounded by the rectangular ring. Thus, the ring-shaped structure 201 surrounds the periphery of the structure to be tested 200, thereby achieving the enclosure of the structure to be tested 200.
In other embodiments, the pattern projected on the surface of the substrate by the annular structure includes a ring, and the pattern projected on the surface of the substrate by the structure to be tested is located at the center of the ring, so that the annular structure surrounds the structure to be tested.
With continued reference to fig. 6, the pattern of the ring-shaped structure 201 projected on the plane perpendicular to the top surface of the substrate 260 is denoted as a first pattern, and the pattern of the structure to be tested 200 projected on the plane perpendicular to the top surface of the substrate 260 is denoted as a second pattern, so that the second pattern is completely located within the range of the first pattern, and therefore the ring-shaped structure 201 achieves surrounding of the peripheral sides of the structure to be tested 200.
Because the annular structure 201 surrounds the peripheral side surfaces of the structure to be tested 200, the annular structure 201 blocks external water vapor which invades the structure to be tested 200 from the side surfaces of the structure to be tested 200 in the interlayer dielectric layer 202, so that stability of the structure to be tested 200 when exposed to air is improved, the condition that electromigration performance of the structure to be tested 200 is affected due to invasion of water vapor is reduced, and authenticity and accuracy of electromigration test results of the structure to be tested 200 are improved. In addition, in the chemical mechanical polishing process in the semiconductor test structure manufacturing process, the annular structure 201 provides mechanical support for the structure to be tested 200, and because the annular structure 201 has better rigidity and larger surface area, and can provide better mechanical support for the structure to be tested 200 from all directions around, the situation that cracks occur in the semiconductor test structure in the process of receiving cutting is effectively reduced, and the polishing effect of the chemical mechanical polishing process is improved.
In other embodiments, the semiconductor test structure includes a number of structures under test. By adding the annular structure to the structure to be tested which is sensitive to water vapor in a targeted manner, a totally-enclosed protection structure does not need to be established around all the test parts, so that the preparation cost is saved, and the universality of the preparation process is improved.
In this embodiment, the material of the ring structure 201 includes copper.
With continued reference to fig. 7, in this embodiment, an opening 204 penetrating the ring structure 201 is provided in the ring structure 201, and the opening 204 makes the ring structure 201 open, so that the ring structure 201 has no electrical performance, and interference of the ring structure 201 to the test structure 200 during the electromigration test is avoided.
In this embodiment, the number of the annular structures 201 is equal to 2, each annular structure 201 is arranged in a concentric surrounding structure, each annular structure 201 jointly surrounds the structure to be measured 200, the structure to be measured 200 is located at the center of the concentric surrounding structure, the projection of each annular structure 201 on the top surface of the substrate 260 is a rectangular ring, and the interval distance between the rectangular rings ranges from 0.1 micrometers to 5 micrometers. Because each annular structure 201 surrounds the sides around the structure to be tested 200 twice, the intrusion of water vapor into the structure to be tested 200 is better reduced, and the authenticity and accuracy of the electromigration test result of the structure to be tested 200 are further improved.
In the present embodiment, two annular structures 201 are denoted as a first annular structure and a second annular structure, which surrounds the first annular structure. The first loop structure has oppositely disposed first and second wires 231, 232 and the second loop structure has oppositely disposed third and fourth wires 233, 234. The second line 232 is positioned between the first line 231 and the fourth line 234 such that the first line 231 and the fourth line 234 are spaced apart by the second line 232, the first line 231 is positioned between the third line 233 and the second line 232, and the third line 233 and the second line 232 are spaced apart by the first line 231.
The first and second annular structures each have an opening 204 extending through the annular structure 201. The opening 204 in the first annular structure is denoted as a first opening and the opening 204 in the second annular structure is denoted as a second opening. The first opening is located in the first line 231, and the second opening is located in the fourth line 234, so that the first opening and the second opening are spaced by the second line 232, and external moisture of the second annular structure is prevented from passing through the first opening and the second opening at the same time in the diffusion process, so that the blocking capability of the annular structure 201 to external moisture is improved, and the situation that external moisture invades the structure 200 to be tested from the side surface through the interlayer dielectric layer 202 is reduced.
In another embodiment, the number of ring structures is equal to 1, which reduces external moisture from the side intrusion into the structure under test, while making the semiconductor test structure simpler, thereby simplifying the manufacturing process cost.
With continued reference to fig. 6, the interlayer dielectric layer 202 includes: a first dielectric structure 251 on the substrate 260, a second dielectric structure 252 on the first dielectric structure 251, and a third dielectric structure 253 on the second dielectric structure 252; the structure under test 200 and the ring-like structure 201 are located within the second dielectric structure 252.
In this embodiment, the constituent material of the first dielectric structure 251 includes a low-k material or an ultra-low-k material.
The second dielectric structure 252 includes: a first barrier layer 221 on the first dielectric structure 251, a first dielectric layer 231 on the first barrier layer 221, and a second dielectric layer 232 on the first dielectric layer 231.
In this embodiment, the second dielectric layer 242 includes a low-k material or an ultra-low-k material.
With continued reference to fig. 6, in this embodiment, the ring structure 201 includes a connection ring 207 and a virtual ring 206 disposed on a top surface of the connection ring 207.
Specifically, the positions of the ring-shaped structure 201 and the structure to be tested 200 in the second dielectric structure 252 are: the connection ring 207 is located in the first dielectric layer 231 and the first barrier layer 221, and the bottom surface of the connection ring 207 is in contact with the top surface of the first dielectric structure 251; the structure to be tested 200 is located in the second dielectric layer 232; the dummy ring 206 is located in the second dielectric layer 232, the bottom surface of the dummy ring 206 is in contact with the top surface of the connection ring 207, and the ring-shaped structure 201 formed by the dummy ring 206 and the connection ring 207 surrounds the structure to be tested 200.
In this embodiment, the top surface of the virtual ring 206 is flush with the top surface of the structure under test 200, and the bottom surface of the virtual ring 206 is flush with the bottom surface of the structure under test 200.
In this embodiment, the pattern of the connection ring 207 projected on the top surface of the substrate 260 is denoted as a connection ring projection pattern, the connection ring projection pattern is denoted as a rectangular ring, the pattern of the virtual ring 206 projected on the top surface of the substrate 260 is denoted as a virtual ring projection pattern, the virtual ring projection pattern is denoted as a rectangular ring, and the connection ring projection pattern is located within the range of the virtual ring projection pattern. The rectangular ring width range of the connection ring projection pattern comprises 0.1-5 microns, the rectangular ring width range of the virtual ring projection pattern comprises 0.1-5 microns, and the rectangular ring width of the connection ring projection pattern is smaller than the rectangular ring width of the virtual ring projection pattern.
With continued reference to fig. 6 and 7, in this embodiment, the semiconductor test structure further includes: a test ring structure 205 located in the second dielectric layer 232, the test ring structure 205 being located between the structure under test 200 and the ring structure 201, the test ring structure 205 surrounding the structure under test 200. The test ring structure 205 is used to detect metal extrusion on the structure under test 200, thereby monitoring the failure condition of the structure under test 200.
With continued reference to fig. 6, the third medium structure 253 includes: a second barrier layer 222 on the second dielectric structure 252 and a third dielectric layer 243 on the second barrier layer 222.
In this embodiment, the material of the first blocking layer 221 includes nitride; the material of the second barrier layer 222 includes nitride. The material of the third dielectric layer 243 includes a low-k material or an ultra-low-k material.
In this embodiment, the pattern projected on the top surface of the first barrier layer 221 by the structure to be tested 200 is located within the range of the top surface of the first barrier layer 221, and the pattern projected on the bottom surface of the second barrier layer 222 by the structure to be tested 200 is located within the range of the bottom surface of the second barrier layer 222. The first barrier layer 221 is positioned under the structure under test 200 to reduce external moisture intrusion from the bottom surface of the structure under test 200, and the second barrier layer 222 is positioned on the structure under test 200 to block external moisture intrusion from the top surface of the structure under test 200. The first barrier layer 221 cooperates with the second barrier layer 222 to reduce the external moisture that invades the structure under test 200 from the direction perpendicular to the top surface of the substrate 260, and to improve the authenticity and accuracy of the electromigration test result of the structure under test 200.
In this embodiment, the virtual ring 206, the connection ring 207, the first barrier layer 221 and the second barrier layer 222 together form an enclosure for each direction of the structure under test 200, so as to reduce the water vapor intrusion from each direction of the structure under test 200, reduce the influence of the water vapor intrusion on the electromigration performance of the structure under test 200, and improve the authenticity and accuracy of the electromigration test result of the structure under test 200.
In this embodiment, the top surface of the first blocking layer 221 is higher than the bottom surface of the ring-shaped structure 201 formed by the connection ring 207 and the virtual ring 206, and the bottom surface of the second blocking layer 222 is flush with the top surface of the ring-shaped structure 201.
With continued reference to fig. 6 and 7, in this embodiment, the semiconductor test structure further includes: an electrical interconnect structure 203 located within the third dielectric layer 243, the electrical interconnect structure 203 being electrically connected to the structure under test 200.
In this embodiment, the third dielectric layer 243 includes a first region (not shown) of the third dielectric layer located on the second barrier layer 222 and a second region (not shown) of the third dielectric layer located on the first region of the third dielectric layer.
Specifically, the electrical interconnection structure 203 is located in the second region of the third dielectric layer, the electrical interconnection structure 203 is located at two ends of the structure to be tested 200, the electrical interconnection structure 203 is electrically connected to the structure to be tested 200 through a conductive plug 208, and the conductive plug 208 is located in the first region of the third dielectric layer and penetrates through the second barrier layer 222. The material of the electrical interconnect structure 203 comprises copper and the material of the conductive plugs 208 comprises tungsten or copper.
The structure under test 200 is connected to an electromigration test apparatus (not shown) via the electrical interconnect 203, thereby testing the structure under test 200. The electromigration test apparatus includes: the first loading point and the second loading point are used for applying a test voltage to the structure to be tested 200 so that the current of the structure to be tested 200 reaches a test condition; the first sensing point and the second sensing point are used for obtaining the sensing voltage of the structure to be tested 200 under the test condition. In the electromigration test process, by applying higher voltages to the first loading point and the second loading point, a larger current density is formed in the structure to be tested 200, so that electromigration in the structure to be tested 200 is accelerated, and the structure to be tested 200 is accelerated to fail, thereby measuring the failure time of the structure to be tested 200 under the test condition.
Fig. 8 and 9 are schematic diagrams illustrating a process of forming a semiconductor test structure according to another embodiment of the present invention.
Referring to fig. 8 and 9, fig. 8 is a cross-sectional view of fig. 9 along DD ', and fig. 9 is a top view of fig. 8 along Y', the method for forming the semiconductor test structure includes: providing a substrate 360; forming a first dielectric structure 351 on the substrate 360; forming a second dielectric structure 352 and the structure 300 to be tested, the annular structure 301 and the test ring structure 305 in the second dielectric structure 352 on the first dielectric structure 351, wherein the test ring structure 305 surrounds the structure 300 to be tested, the test ring structure 305 is positioned between the structure 300 to be tested and the annular structure 301, the annular structure 301 surrounds the structure 300 to be tested, the top surface of the annular structure 301 is flush with the top surface of the structure 300 to be tested, the bottom surface of the annular structure 301 is lower than the bottom surface of the structure 300 to be tested, an opening 304 is formed in the annular structure 301, and the opening 304 penetrates through the annular structure 301 along the direction perpendicular to the top surface of the annular structure 301; a third dielectric structure 353 is formed over the second dielectric structure 352, the structure under test 300, and the ring structure 301.
In this embodiment, the forming method, material and structure of the substrate 360, the first dielectric structure 351, the second dielectric structure 352, the third dielectric structure 353, the ring structure 301, the structure 300 to be tested, the opening 304 of the ring structure 301 and the test ring structure 305 are the same as the forming method, material and structure of the substrate 260, the first dielectric structure 251, the second dielectric structure 252, the third dielectric structure 253, the ring structure 201, the structure 200 to be tested, the opening 204 of the ring structure 201 and the test ring structure 205 in fig. 3 to 7, respectively, and will not be repeated here.
In this embodiment, the second medium structure 352 includes: a first barrier layer 321 on the first dielectric structure 351, a first dielectric layer 331 on the first barrier layer 321, and a second dielectric layer 332 on the first dielectric layer 331. The forming method, material and structure of the first barrier layer 321, the first dielectric layer 331 and the second dielectric layer 332 in this embodiment are the same as those of the first barrier layer 221, the first dielectric layer 231 and the second dielectric layer 232 in fig. 3 to 7, and will not be repeated here.
In this embodiment, the ring structure 301 includes a connection ring 307 and a virtual ring 306 disposed on a top surface of the connection ring 307. The forming method, material and structure of the connection ring 307 and the dummy ring 306 described in the present embodiment are the same as those of the connection ring 207 and the dummy ring 206 in fig. 3 to 7, respectively, and will not be described again here.
In this embodiment, the third medium structure 353 includes: a second barrier layer 322 on the second dielectric structure 352 and a third dielectric layer 343 on the second barrier layer 322. The forming method, material and structure of the second barrier layer 322 and the third dielectric layer 343 in this embodiment are the same as those of the second barrier layer 222 and the third dielectric layer 243 in fig. 3 to 7, respectively, and will not be repeated here.
In this embodiment, the method for forming a semiconductor test structure further includes: a test ring structure 305 is formed within the second dielectric structure 352 between the structure 300 under test and the ring structure 301, the test ring structure 305 surrounding the structure 300 under test. The forming method, material and structure of the test ring structure 305 in this embodiment are the same as those of the test ring structure 205 in fig. 3 to 7, and will not be repeated here.
In this embodiment, the semiconductor test structure further includes: after forming the first dielectric structure 351, an electrical interconnect structure 303 is formed within the first dielectric structure 351, the electrical interconnect structure 303 being electrically connected to the subsequently formed structure 300 to be tested.
The forming step of the electrical interconnection structure 303 includes: after forming the first dielectric structure 351, forming the electrical interconnect structure 303 within the first dielectric structure 351; after forming the first dielectric layer 331 and the first barrier layer 321, forming a conductive plug 308 in the first dielectric layer 331, where the conductive plug 308 penetrates the first barrier layer 321, and one end of the conductive plug 308 is connected to the electrical interconnection structure 303; the structure 300 to be tested is formed on the conductive plug 308 and the first dielectric layer 331, and the structure 300 to be tested is connected to the other end of the conductive plug 308, so that the structure 300 to be tested is electrically connected to the electrical interconnection structure 303 through the conductive plug 308.
In this embodiment, the conductive plugs 308 are made of copper or tungsten, and the formation process of the conductive plugs 308 includes chemical vapor deposition or physical vapor deposition.
The material of the electrical interconnection structure 303 includes copper, and the formation process of the electrical interconnection structure 303 includes chemical vapor deposition or physical vapor deposition.
It should be noted that the top view shown in fig. 9 does not include the third media structure 353 for ease of understanding.
Correspondingly, the embodiment of the invention also provides a semiconductor test structure.
With continued reference to fig. 8 and 9, the semiconductor test structure includes: a substrate 360; an interlayer dielectric layer 302 on the substrate 360; a structure 300 to be tested located within an interlayer dielectric layer 302; a ring-shaped structure 301 located in the interlayer dielectric layer 302, the ring-shaped structure 301 surrounding the structure 300 to be tested, the top surface of the ring-shaped structure 301 being flush with the top surface of the structure 300 to be tested, the bottom surface of the ring-shaped structure 301 being lower than the bottom surface of the structure 300 to be tested; an opening 304 in the annular structure 301, the opening 304 extending through the annular structure 301 in a direction perpendicular to the top surface of the annular structure 301.
In this embodiment, the materials and structures of the substrate 360, the ring-shaped structure 301, the structure to be tested 300 and the opening 304 of the ring-shaped structure 301 are the same as those of the substrate 260, the ring-shaped structure 201, the structure to be tested 200 and the opening 204 of the ring-shaped structure 201 in fig. 6 and 7, respectively, and will not be repeated here.
In this embodiment, the interlayer dielectric layer 302 includes: a first dielectric structure 351 located on the substrate 360, a second dielectric structure 352 located on the first dielectric structure 351, and a third dielectric structure 353 located on the second dielectric structure 352; the structure 300 to be tested and the ring-shaped structure 301 are located within the second dielectric structure 352.
In this embodiment, the second medium structure 352 includes: a first barrier layer 321 on the first dielectric structure 351, a first dielectric layer 331 on the first barrier layer 321, and a second dielectric layer 332 on the first dielectric layer 331. The materials and structures of the first dielectric structure 351, the first barrier layer 321, the first dielectric layer 331 and the second dielectric layer 332 in this embodiment are the same as those of the first dielectric structure 251, the first barrier layer 221, the first dielectric layer 231 and the second dielectric layer 232 in fig. 6 and 7, respectively, and will not be repeated here.
The ring structure 301 includes a connection ring 307 and a virtual ring 306 located on the top surface of the connection ring 307. The materials and structures of the connection ring 307 and the dummy ring 306 in this embodiment are the same as those of the connection ring 207 and the dummy ring 206 in fig. 6 and 7, respectively, and will not be repeated here.
The third medium structure 353 includes: a second barrier layer 322 on the second dielectric structure 352 and a third dielectric layer 343 on the second barrier layer 322. The materials and structures of the second barrier layer 322 and the third dielectric layer 343 in this embodiment are the same as those of the second barrier layer 222 and the third dielectric layer 243 in fig. 6 and 7, respectively, and the description thereof will not be repeated here.
In this embodiment, the semiconductor test structure further includes: a test ring structure 305 located within the second dielectric layer 332, the test ring structure 305 being located between the structure 300 under test and the ring structure 301, the test ring structure 305 surrounding the structure 300 under test.
With continued reference to fig. 8, in this embodiment, the semiconductor test structure further includes: an electrical interconnect structure 303 within the first dielectric structure 351, the electrical interconnect structure 303 being electrically connected to the structure 300 under test.
The bottom surface of the electrical interconnection structure 303 contacts the top surface of the substrate 360, the electrical interconnection structure 303 is located at two ends of the structure 300 to be tested, the electrical interconnection structure 303 is electrically connected to the structure 300 to be tested through a conductive plug 308, and the conductive plug 308 is located in the first dielectric layer 331 and penetrates through the first barrier layer 321.
The material of the electrical interconnect structure 303 comprises copper and the material of the conductive plug 308 comprises tungsten or copper.
The structure 300 under test is connected to an electromigration test apparatus (not shown) via the electrical interconnect 303, thereby testing the structure 300 under test.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (24)

1. A semiconductor test structure, comprising:
a substrate;
an interlayer dielectric layer on the substrate;
a structure to be tested located in the interlayer dielectric layer;
the annular structure is positioned in the interlayer dielectric layer, the annular structure surrounds the structure to be detected, the top surface of the annular structure is flush with the top surface of the structure to be detected, and the bottom surface of the annular structure is lower than the bottom surface of the structure to be detected;
and an opening in the annular structure, the opening extending through the annular structure in a direction perpendicular to a top surface of the annular structure.
2. The semiconductor test structure of claim 1, wherein the structure under test comprises a structure under test.
3. The semiconductor test structure of claim 1, further comprising: and the test ring structure is positioned between the structure to be tested and the annular structure and surrounds the structure to be tested.
4. The semiconductor test structure of claim 2, wherein the wire structure under test comprises an inner wire structure under test and an outer wire structure under test on a surface of the inner wire structure under test.
5. The semiconductor test structure of claim 4, wherein the constituent material of the inner-layer to-be-tested line structure comprises copper; the constituent materials of the outer layer to-be-tested line structure comprise one or a combination of tantalum and tantalum nitride.
6. The semiconductor test structure of claim 1, wherein the number of ring structures is equal to 1 or 2.
7. The semiconductor test structure of claim 6, wherein each ring structure is arranged in a concentric surrounding configuration when the number of ring structures is equal to 2.
8. The semiconductor test structure of claim 1, wherein the ring-like structure comprises a connecting ring and a dummy ring on a top surface of the connecting ring, the top surface of the dummy ring being flush with the top surface of the structure under test, the bottom surface of the dummy ring being flush with the bottom surface of the structure under test.
9. The semiconductor test structure of claim 1, wherein the material of the ring structure comprises copper.
10. The semiconductor test structure of claim 1, wherein the interlayer dielectric layer comprises: a first dielectric structure located on the substrate, a second dielectric structure located on the first dielectric structure, and a third dielectric structure located on the second dielectric structure; the structure to be tested and the annular structure are located in the second medium structure.
11. The semiconductor test structure of claim 10, wherein the second dielectric structure comprises: the first dielectric layer is arranged on the first dielectric structure, the second dielectric layer is arranged on the first dielectric layer, and the top surface of the first dielectric layer is higher than the bottom surface of the annular structure.
12. The semiconductor test structure of claim 11, wherein the material of the first dielectric structure comprises a low-k material or an ultra-low-k material; the material of the first dielectric layer comprises a low-k material or an ultra-low-k material; the material of the second dielectric layer comprises a low-k material or an ultra-low-k material; the k value of the low-k material is less than 3, and the k value of the ultra-low-k material is less than 2.5.
13. The semiconductor test structure of claim 11, wherein the material of the first barrier layer comprises nitride.
14. The semiconductor test structure of claim 11, further comprising: and the electrical interconnection structure is positioned in the first dielectric structure and is electrically connected with the structure to be tested.
15. The semiconductor test structure of claim 10, wherein the third dielectric structure comprises: a second barrier layer on the second dielectric structure and a third dielectric layer on the second barrier layer, wherein the bottom surface of the second barrier layer is flush with the top surface of the annular structure.
16. The semiconductor test structure of claim 15, wherein the material of the second barrier layer comprises nitride.
17. The semiconductor test structure of claim 15, wherein the material of the third dielectric layer comprises a low-k material or an ultra-low-k material; the k value of the low-k material is less than 3, and the k value of the ultra-low-k material is less than 2.5.
18. The semiconductor test structure of claim 15, further comprising: and the electrical interconnection structure is positioned in the third dielectric layer and is electrically connected with the structure to be tested.
19. The semiconductor test structure of claim 1, wherein the substrate comprises a base, a device layer on the base, and an interconnect layer connecting the device layers.
20. A method of forming a semiconductor test structure, comprising:
providing a substrate;
the method comprises the steps of forming an interlayer dielectric layer, a structure to be tested located in the interlayer dielectric layer and an annular structure located in the interlayer dielectric layer on a substrate, wherein the annular structure surrounds the structure to be tested, the top surface of the annular structure is flush with the top surface of the structure to be tested, the bottom surface of the annular structure is lower than the bottom surface of the structure to be tested, an opening is formed in the annular structure, and the opening penetrates through the annular structure along the direction perpendicular to the top surface of the annular structure.
21. The method of forming a semiconductor test structure of claim 20, wherein the interlayer dielectric layer comprises: a first dielectric structure located on the substrate, a second dielectric structure located on the first dielectric structure, and a third dielectric structure located on the second dielectric structure; the structure to be tested and the annular structure are located in the second medium structure.
22. The method of claim 21, wherein the forming the interlayer dielectric layer, the structure to be tested, and the ring structure comprises: forming a first dielectric structure on the substrate; forming a second medium structure on the first medium structure, and the structure to be tested and the annular structure which are positioned in the second medium structure; and forming a third medium structure on the second medium structure, the structure to be tested and the annular structure.
23. The method of forming a semiconductor test structure of claim 21, wherein the second dielectric structure comprises: the first dielectric layer is arranged on the first dielectric structure, the second dielectric layer is arranged on the first dielectric layer, and the bottom surface of the annular structure is lower than the top surface of the first dielectric layer.
24. The method of forming a semiconductor test structure of claim 21, wherein the third dielectric structure comprises: a second barrier layer on the second dielectric structure and a third dielectric layer on the second barrier layer, wherein the bottom surface of the second barrier layer is flush with the top surface of the annular structure.
CN202111458694.XA 2021-12-01 2021-12-01 Semiconductor test structure and forming method thereof Pending CN116259607A (en)

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