JP2000058611A - Method for evaluating semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for evaluating semiconductor device with which defective spots can be specified by readily grasping the magnitude of erosion and dishing through optical measurement and moreover, in electrical measurement. SOLUTION: In this method for evaluating semiconductor devices, the level difference of a hole pattern concentrating area resulting from the chemical- mechanical polishing of a substrate is measured. Optically measurable remaining film patterns are provided in a central part 1 and peripheral part 3 of the hole pattern concentrating area, and the film thicknesses of the respective patterns are measured. The level difference for the hole pattern concentrating region is found based on the measured values.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for evaluating a semiconductor device in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art With the integration of semiconductors, a chemical mechanical polishing method (CMP: Chemical-Mechanical) is used as a planarization technique.
-Polishing) has been increasingly used. FIG. 16A is a cross-sectional view of a groove pattern dense region 70 and a pattern region 71 having a large groove width before polishing by CMP in a half integrated circuit. Reference numeral 52 denotes a pattern formed under the film to be polished. 53 is a film to be polished on the pattern before polishing. Numeral 54 denotes a film to be polished in a portion having no pattern. FIG. 16B shows the films 53 and 54 to be polished during the CMP.
It is sectional drawing in the state which has been grind | polished. Although the pattern area is not polished, only the films to be polished 53 and 54 are polished. FIG. 16C is a cross-sectional view of the finished shape after polishing by CMP. 55 is an erosion. The erosion 55 is a phenomenon in which the height of the film to be polished 54 becomes lower than the height of the pattern in the groove pattern dense region by CMP. 56 is dishing. The dishing 56 is a phenomenon in which the height of the film to be polished 54 becomes lower than the height of the pattern 52 in a pattern region having a large groove width by CMP.

[0003]

However, in the prior art, the erosion 55 and dishing 56 generated by the CMP are evaluated by a step measuring device after the completion of the CMP process, the residual film evaluation after the CMP polishing by the film thickness measuring device, or It could be evaluated only by the cross-sectional shape evaluation method based on SEM (Scanning Electron Microscope) observation. Further, it was not known whether or not the erosion 55 and dishing 56 generated by the CMP after the completion of all the processes caused the failure.

The present invention solves the above-mentioned conventional problems. The size of erosion and dishing can be easily determined by optical measurement, and furthermore, the defective portion can be easily determined by electrical measurement. It is an object to provide a method for evaluating a semiconductor device.

[0005]

According to a first aspect of the present invention, there is provided a method for evaluating a semiconductor device, comprising: measuring a step in a dense region of a hole pattern caused by chemical mechanical polishing of a substrate. An optically measurable residual film measurement pattern is provided at the pattern center portion and the pattern peripheral portion, the film thickness of each of these residual film measurement patterns is measured, and a step in the hole pattern dense area is determined based on the measured value. It is a feature.

According to the semiconductor device evaluation method of the present invention, erosion by CMP is used as a test pattern, and a pattern for optically measuring a film thickness to be polished is separated from a peripheral pattern at the center of the pattern. Easily by measuring the film thickness of a large space, for example, an oxide film,
Erosion generated by CMP can be measured and evaluated.

A semiconductor device evaluation method according to claim 2 is
A method for evaluating a semiconductor device that measures a step in a hole pattern dense region generated by chemically and mechanically polishing a substrate, comprising a plurality of patterns in which the pattern density of the hole pattern dense region is changed, Provide an optically measurable residual film measurement pattern at the center and periphery of the pattern, measure the film thickness, find the step in the hole pattern dense area based on the measured value, and find the relationship between pattern density and step It is characterized by the following.

According to the semiconductor device evaluation method of the second aspect, the same effect as that of the first aspect is obtained. According to a third aspect of the present invention, in the method for evaluating a semiconductor device according to the first or second aspect, the width of the remaining film measurement pattern at the peripheral portion of the pattern is 100 μm.
m or more. According to the semiconductor device evaluation method of the third aspect, the same effect as that of the first aspect is obtained.

According to a fourth aspect of the present invention, there is provided a semiconductor device evaluation method comprising:
Forming an insulating film on a substrate and forming a first wiring thereon; forming a pattern of a hole pattern dense region on the first wiring and performing chemical mechanical polishing of the pattern; Forming a second wiring on the pattern, providing a hole for conducting the first wiring and the second wiring at the center of the pattern of the pattern, and forming a hole between the first wiring and the second wiring. And detecting a difference in film thickness from the resistance thereof, and electrically obtaining a step generated by polishing.

According to the semiconductor device evaluation method of the present invention, by providing the first wiring and the second wiring, erosion and dishing can be electrically evaluated, and furthermore, C
It is possible to determine whether the erosion and dishing caused by the MP can cause a defect after the end of the entire process,
Further, a defective portion can be specified. 6. The method for evaluating a semiconductor device according to claim 5, wherein the step of measuring a step in a line pattern dense region caused by chemical mechanical polishing of a substrate is performed. An optically measurable residual film measurement pattern is provided, the film thickness of each of these residual film measurement patterns is measured, and a step in a dense line pattern region is obtained based on the measured value.

According to the semiconductor device evaluation method of the fifth aspect, the same effect as that of the first aspect is obtained. 7. The method for evaluating a semiconductor device according to claim 6, wherein the step of measuring a step in a line pattern dense region caused by chemical mechanical polishing of a substrate is performed. Having a plurality of changed patterns, measuring the film thickness by providing an optically measurable residual film measurement pattern at the center of each pattern and the periphery of the pattern,
The method is characterized in that a step in a line pattern dense area is obtained based on the measured value, and a relationship between the pattern density and the step is obtained.

According to the semiconductor device evaluation method of the sixth aspect, the same effect as that of the first aspect is obtained. According to a seventh aspect of the present invention, in the semiconductor device evaluation method according to the fifth or sixth aspect, the width of the remaining film measurement pattern at the periphery of the pattern is 100 μm.
m or more. According to the semiconductor device evaluation method of the seventh aspect, the same effect as that of the fifth aspect is obtained.

[0013] According to a eighth aspect of the present invention, there is provided a semiconductor device evaluation method,
Forming an insulating film on a substrate and forming a first wiring thereon; forming a pattern of a line pattern dense region on the first wiring by a chemical mechanical polishing method; A step of forming a second wiring thereon, a step of providing a hole for conducting the first wiring and the second wiring at the center of the pattern, and applying a voltage between the first wiring and the second wiring To detect the difference in film thickness from the resistance,
Electrically obtaining a step generated by polishing.

According to the semiconductor device evaluation method of the eighth aspect, the same effect as that of the fourth aspect is obtained. The method of evaluating a semiconductor device according to claim 9, wherein the step of measuring a step in a pattern region having a large groove width surrounded by a metal and generated by chemically and mechanically polishing the substrate is performed. A residual film measurement pattern that can be optically measured is provided at the center and the periphery of the pattern, the film thickness of the residual film measurement pattern is measured, and a step in a large groove width pattern region surrounded by metal is determined based on the measured value. It is characterized by the following.

According to a ninth aspect of the present invention, there is provided a method for measuring and evaluating dishing by CMP.
This has the same effect as the first aspect. The method for evaluating a semiconductor device according to claim 10, wherein the step of measuring a step in a pattern region having a large groove width surrounded by metal and generated by chemically and mechanically polishing the substrate is performed.
It has multiple patterns in which the area of the metal in the pattern area with a large groove width surrounded by metal is changed, and provides an optically measurable residual film measurement pattern at the center of each pattern and the periphery of the pattern. Is measured, and based on the measured value, the step of the pattern region with a large groove width surrounded by metal is determined, and further, the relationship between the metal area and the step of the pattern region with a large groove width surrounded by metal is determined. It is a feature.

According to the semiconductor device evaluation method of the tenth aspect, the same effect as that of the first aspect is obtained. The method for evaluating a semiconductor device according to claim 11 is claim 9 or claim 10.
In the above, the width of the residual film measurement pattern around the pattern is 1
Not less than 00 μm. According to the semiconductor device evaluation method of the eleventh aspect, the same effect as that of the ninth aspect can be obtained.

According to a twelfth aspect of the present invention, there is provided a method for evaluating a semiconductor device, comprising: forming an insulating film on a substrate, forming a first wiring thereon; and forming a trench surrounded by metal on the first wiring. A step of forming a pattern in a pattern region having a large width by a chemical mechanical polishing method, a step of forming a second wiring on the pattern, and a step of forming a first wiring and a second wiring at a pattern central portion of the pattern. The method includes a step of providing a hole for conduction, and a step of applying a voltage between the first wiring and the second wiring, detecting a difference in film thickness from the resistance thereof, and electrically obtaining a step generated by polishing. .

According to the semiconductor device evaluation method of the twelfth aspect, the same effect as that of the fourth aspect is obtained. A method for evaluating a semiconductor device according to claim 13, wherein an insulating film is formed on a substrate,
Forming a first wiring thereon, forming an interlayer insulating film on the first wiring, forming a hole thereon by a chemical mechanical polishing method, and further forming a second hole thereon; Forming a wiring perpendicular to the first wiring, making the first wiring and the second wiring conductive by a hole, applying a voltage between the first wiring and the second wiring, Detecting a difference in film thickness from the resistance and electrically obtaining a step generated by polishing.

According to the semiconductor device evaluation method of the thirteenth aspect, the same effect as that of the fourth aspect is obtained, and the coordinates of the defective portion can be determined by appropriately selecting the first wiring and the second wiring. it can. The method for evaluating a semiconductor device according to claim 14, further comprising: forming an insulating film on the substrate; forming a groove on the insulating film;
A step of embedding a metal film in the groove, a step of forming a first wiring by a chemical mechanical polishing method thereafter, and applying a voltage to both ends of the first wiring to detect a difference in film thickness from the resistance. And a step of electrically determining a step generated by polishing.

According to the semiconductor device evaluation method of the fourteenth aspect, in addition to the same effects as those of the fourth aspect, it is possible to determine a defective portion due to an increase in resistance of the first wiring.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a test pattern for evaluating the erosion of a hole pattern in the method for evaluating a semiconductor device according to the first embodiment of the present invention. Reference numeral 1 denotes a pattern for optically measuring a film thickness to be polished after polishing by CMP, and is formed of a silicon oxide film. 2 is a hole dense pattern. The hole dense pattern 2 is formed by burying a metal film in an opening in the interlayer insulating film and polishing by CMP. Erosion occurs at this time. 3 is a large silicon oxide film space for separating the hole dense pattern,
This is the reference film thickness for comparison with Pattern 1 for optically measuring the film thickness after polishing by CMP. The size of the erosion can be simplified by comparing the wide silicon oxide film space 3 for separating the hole dense pattern and the pattern 1 film thickness for optically measuring the film thickness to be polished by the CMP. I understand. 4 is the width of the space of the silicon oxide film. This width is sufficiently large to be 100 μm or more so as not to be affected by scraping by CMP.

FIG. 2 is a cross-sectional view after the CMP of the test pattern for evaluating the erosion of the hole pattern of FIG. Reference numeral 5 corresponds to the reference numeral 1 and is a pattern for optically measuring the film thickness to be polished after the polishing by CMP, and is composed of a silicon oxide film. Numeral 6 corresponds to 2, and is a hole-shaped dense pattern. Numeral 7 corresponds to 3 and is a space for a wide silicon oxide film for separation. The size of the erosion can be easily determined by optically measuring the thickness of the large silicon oxide film space 7 for separation and the thickness of the pattern 5 for optically measuring the thickness to be polished and comparing them with each other. I understand. Note that 5 is the central part of the remaining film measurement pattern, and 7
Is the peripheral portion of the pattern.

FIG. 3 shows a pattern obtained by changing the pattern density of the hole dense pattern 2 shown in FIG. FIG. 11A shows a small pattern density, FIG. 10B shows a larger pattern density, and FIG. 10C shows a larger pattern density. In the case where the pattern density was changed, a pattern 1 for optically measuring the film thickness to be polished after the polishing by CMP in FIG.
The relationship between pattern density and erosion can be evaluated by optically measuring and comparing the film thickness in the space 3 portion of the wide silicon oxide film for separating the hole dense pattern from the silicon oxide film. The erosion increases as the pattern density increases, and the erosion decreases as the pattern density decreases.

FIG. 4 is a plan view of a test pattern for evaluating erosion of a line pattern in the method for evaluating a semiconductor device according to the second embodiment of the present invention. 8 is CM
This is a pattern for optically measuring the film thickness to be polished after polishing by P, and is made of a silicon oxide film. 9 is a metal line dense pattern. The line pattern 9 is formed by digging a groove in the interlayer insulating film, filling the metal film, and polishing by CMP. Erosion occurs at this time. Reference numeral 10 denotes a portion serving as a reference film thickness for comparison with the metal line dense pattern 9 and the pattern 8 for optically measuring the film thickness to be polished after CMP. The size of the erosion can be easily determined by comparing the large silicon oxide film space 10 for separating the line dense pattern with the pattern 8 for optically measuring the film thickness to be polished by the CMP. I understand. 11 is the width of the space of the silicon oxide film. This width is sufficiently large to be 100 μm or more so as not to be affected by scraping by CMP.

FIG. 5 is a cross-sectional view after the CMP of the test pattern of FIG. 4 for evaluating erosion. Reference numeral 12 denotes a pattern for optically measuring a film thickness to be polished after polishing by CMP, and is formed of a silicon oxide film. Reference numeral 13 corresponds to 9 and is a metal line dense pattern. Reference numeral 14 denotes a large silicon oxide film space corresponding to 10 for separation. In addition, 12 is a pattern center portion of the residual film measurement pattern, and 14 is a pattern peripheral portion.
Large silicon oxide film space 14 for separation and CMP
The size of the erosion can be easily determined by optically measuring and comparing the film thickness of the pattern 12 for optically measuring the film thickness to be polished after the polishing.

FIG. 6 shows the metal line dense pattern 9 of FIG.
Are changed. FIG. 11A shows a small pattern density, FIG. 10B shows a larger pattern density, and FIG. 10C shows a larger pattern density. In the pattern with the changed pattern density, a pattern 8 for optically measuring a film thickness to be polished by the CMP shown in FIG. 4 and a space 10 made of a wide silicon oxide film for separating a metal line dense pattern. The relationship between pattern density and erosion can be evaluated by optically measuring and comparing the film thicknesses. The erosion decreases as the pattern density increases, and the erosion increases as the pattern density decreases.

FIG. 7 is a plan view of a test pattern for evaluating dishing in the semiconductor device evaluation method according to the third embodiment of the present invention. Reference numeral 15 denotes a pattern for optically measuring a film thickness to be polished after polishing by CMP, which is a silicon oxide film. Reference numeral 16 denotes a metal pattern. The metal pattern 16 is formed by burying a metal film in an opening in the interlayer insulating film and polishing by CMP. Dishing occurs at this time. Reference numeral 17 denotes a wide silicon oxide film space for separating a metal pattern.
This is a portion serving as a reference film thickness for comparison with the pattern 15 for optically measuring the film thickness after polishing by P. By comparing the portion 15 for measuring the film thickness to be polished and the space 17 of the wide silicon oxide film for separating the metal pattern, the size of the dishing can be easily known. 1
8 is the width of the space of the silicon oxide film. This width is C
The width is sufficiently large to be 100 μm or more so as not to be affected by scraping due to MP.

FIG. 8 is a cross-sectional view after the test pattern of FIG. 7 for evaluating dishing is subjected to CMP. Reference numeral 19 corresponds to the reference numeral 15 and is a cross-sectional view of the portion 15 for measuring a film thickness to be polished after polishing by CMP, which is a silicon oxide film. 2
0 corresponds to 16 and is a metal pattern. 21 is 17
And a space for a wide silicon oxide film for separation. Note that 19 is the pattern center portion of the residual film measurement pattern, and 21 is the pattern peripheral portion.

FIG. 9 shows a variation of the chip size of the metal pattern 16 of FIG. FIG. 11A shows a case where the chip size is large, FIG. 10B shows a case where the chip size is smaller, and FIG. 10C shows a case where the chip size is even smaller.
The chip having the changed chip size is polished, and the CM shown in FIG.
Evaluation of the relationship between chip size and dishing by optically measuring and comparing the portion 15 for measuring the thickness of the film to be polished after polishing with P and the space portion 17 of the wide silicon oxide film for separating the metal pattern. can do. The dishing is larger as the chip size is larger, and the dishing is smaller as the chip size is smaller.

FIG. 10 shows a pattern for measuring the erosion generated by CMP electrically and specifying the point of occurrence in the method for evaluating a semiconductor device according to the fourth embodiment of the present invention. FIG. 10A shows the first wiring 22 formed on the silicon oxide film. 23
Is a pad for electrically measuring the wiring. FIG.
10B, an interlayer insulating film is formed on the first wiring 22 formed in FIG. 10A, an opening is formed in the interlayer insulating film so as to be in contact with the first wiring 22, metal is buried, and CMP polishing is performed. FIG. 3 is a view showing a hole 24 formed. At this time, erosion has occurred. FIG. 10C shows that the second wiring 25 is formed on the hole 24 so as to be in contact with the hole 24. Reference numeral 26 denotes a pad for electrically measuring a wiring.

FIG. 11 is a sectional view of FIG.
39 is a first wiring 22. 40 is a hole 24. Reference numeral 41 denotes an interlayer insulating film formed on the first wiring 39, which is planarized by performing CMP. Reference numeral 42 denotes the second wiring 25. The first wiring 39 and the second wiring 42 are electrically connected by the hole 40. When a voltage is applied to the pads 23 and 26 and a current flows in FIG. 10, the electrical resistance at the location where erosion occurs becomes lower than that at the location where erosion does not occur. Further, the resistance rising portion is defined by the first wiring 22.
By appropriately selecting the second wiring 25 and the second wiring 25, the coordinates can be specified.

FIG. 12 shows a pattern for electrically measuring the erosion of a hole pattern generated by CMP in the semiconductor device evaluation method according to the fifth embodiment of the present invention. FIG. 12A shows a first wiring 27 formed on a silicon oxide film. 28
Is a pad for electrically measuring the wiring. FIG.
FIG. 4B shows that the pattern density of the hole dense pattern is changed on the first wiring 27 in the same manner as in FIG.
It is the top view which formed what changed the mask size with constant pattern density of the hole dense pattern 47 by CMP. At this time, erosion has occurred. 29,
Reference numeral 30 denotes a hole that is electrically connected to the first wiring 27. FIG. 12C shows that the second wiring 31 is formed on the holes 29 and 30 so as to be in contact with the holes 29 and 30.
Reference numeral 32 denotes a pad for electrically measuring a wiring.

FIG. 13 is a sectional view of FIG.
43 is a cross section of the first wiring 27. 45 is Hall 2
9, 30. Reference numeral 44 denotes a cross section after the CMP of the holes 47 and 48 obtained by changing the pattern density of the holes 29 and 30. 46 is the second wiring 31. The first wiring 27 and the second wiring 31 are electrically connected by the hole 45. When a voltage is applied to the pads 28 and 32 and a current flows in FIG. 12, the wiring chain resistance at the location where erosion occurs becomes lower than the portion where erosion does not occur. Also,
The resistance drop point can be specified as coordinates by appropriately selecting the first wiring 27 and the second wiring 31. In addition, the pattern density 48 of the hole dense pattern and the pattern density 47 of the hole dense pattern having the same pattern density and the mask size 47 are simultaneously polished, and the erosion is evaluated. And the relationship between the mask size can be understood in more detail.

FIG. 14 shows a pattern for measuring the erosion generated by CMP electrically and specifying the point of occurrence in the method for evaluating a semiconductor device according to the sixth embodiment of the present invention. FIG. 14A shows a first wiring 33 formed on a silicon oxide film. 49
Is a pad for electrically measuring the wiring. FIG.
FIG. 5B shows that the pattern density of the metal line dense pattern is changed on the first wiring 33 in the same manner as in FIG.
FIG. 1 is a plan view showing a case 1 in which the pattern density of a metal line dense pattern is constant and the mask size is changed 50 is formed by CMP. At this time, erosion has occurred. Reference numerals 34 and 35 are holes that are electrically connected to the first wiring 33. FIG. 14C shows that the second wiring 36 is formed on the holes 34 and 35. Reference numeral 37 denotes a pad for electrically measuring a wiring. When a voltage is applied to the pad 49 and the pad 37 in FIG. 14 to cause a current to flow, the wiring chain resistance at the location where erosion occurs becomes lower than the portion where no erosion occurs. Further, the resistance drop point can be specified as coordinates by appropriately selecting the first wiring 33 and the second wiring 36. A pattern 51 of a metal line pattern with a changed pattern density and a pattern 51 of a metal line pattern with a fixed pattern density and a changed mask size are simultaneously formed, and the erosion is evaluated. And the relationship between the mask size can be understood in more detail.

The pattern in the pattern region having a large groove width shown in FIGS. 7 to 9 can be applied in place of the pattern shown in FIG. 14 by the method described with reference to FIG. FIG. 15 shows a pattern for evaluating erosion only by wiring resistance in the method for evaluating a semiconductor device according to the seventh embodiment of the present invention. A groove is formed in the interlayer insulating film, a metal film is buried, and then the first wiring 38 is formed by performing CMP. This first wiring 38
When a voltage is applied to both ends and a current flows, the portion where erosion occurs becomes thinner in the thickness of the wiring, so that the electrical resistance increases. With this structure, it is possible to specify the erosion generation location at the pad level. Erosion can be easily evaluated by reducing the number of steps.

Although the above embodiment describes the application to a hole pattern or a line pattern by embedding a metal, the application to an STI (Shallow Trench isolation) process is also possible. In the case of STI, since the trench type oxide film is separated, erosion can be evaluated in the same manner as in the above line pattern.

[0037]

According to the semiconductor device evaluation method of the present invention, a pattern for optically measuring a film thickness to be polished and a peripheral pattern are formed at the center of the pattern by using erosion by CMP as a test pattern. The erosion generated by CMP can be easily measured and evaluated by measuring the film thickness of a large space for an oxide film for separation, for example.

According to the semiconductor device evaluation method of the second aspect, the same effect as that of the first aspect is obtained. According to the semiconductor device evaluation method of the third aspect, the same effect as that of the first aspect is obtained. According to the semiconductor device evaluation method of the fourth aspect,
By providing the first wiring and the second wiring, erosion and dishing can be evaluated electrically, and it can be determined whether the erosion and dishing generated by the CMP can be a cause of failure after completion of the entire process. Can be identified.

According to the semiconductor device evaluation method of the fifth aspect, the same effect as that of the first aspect is obtained. According to the semiconductor device evaluation method of the sixth aspect, the same effect as that of the first aspect is obtained. According to the semiconductor device evaluation method of the seventh aspect,
There is an effect similar to that of the fifth aspect.

According to the semiconductor device evaluation method of the eighth aspect, the same effect as that of the fourth aspect is obtained. According to the semiconductor device evaluation method of the ninth aspect, the same effect as that of the first aspect can be obtained in measuring and evaluating dishing by CMP.
According to the semiconductor device evaluation method of the tenth aspect, the same effect as that of the first aspect is obtained.

According to the semiconductor device evaluation method of the eleventh aspect, the same effect as that of the ninth aspect can be obtained. According to the semiconductor device evaluation method of the twelfth aspect, the same effect as that of the fourth aspect is obtained. According to the semiconductor device evaluation method of the thirteenth aspect, in addition to the same effects as those of the fourth aspect, the coordinates of the defective portion can be determined by appropriately selecting the first wiring and the second wiring.

According to the semiconductor device evaluation method of the fourteenth aspect, in addition to the same effects as those of the fourth aspect, it is possible to determine a defective portion due to an increase in resistance of the first wiring.

[Brief description of the drawings]

FIG. 1 is a plan view of a test pattern for evaluating erosion in a semiconductor device evaluation method according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view after the test pattern for evaluating erosion in FIG. 1 is subjected to CMP.

FIG. 3 is a plan view of a plurality of modes in which the pattern density of the hole dense pattern in FIG. 1 is changed.

FIG. 4 is a plan view of a test pattern for evaluating erosion according to a second embodiment of the present invention.

5 is a cross-sectional view after the test pattern for evaluating erosion in FIG. 4 is subjected to CMP.

6 is a plan view of a plurality of forms in which the pattern density of the dense metal line pattern of FIG. 4 is changed.

FIG. 7 is a plan view of a test pattern for evaluating dishing according to a third embodiment of the present invention.

8 is a cross-sectional view after the test pattern for evaluating dishing of FIG. 7 is subjected to CMP.

FIG. 9 is a plan view of a plurality of embodiments in which the chip size in FIG. 7 is changed.

FIG. 10 shows a CMP according to a fourth embodiment of the present invention.
FIG. 4 is a plan view of a pattern for electrically measuring erosion generated by the measurement and specifying a generated position.

FIG. 11 is a cross-sectional view of a pattern for electrically measuring erosion generated by CMP in FIG.

FIG. 12 shows a CMP according to a fifth embodiment of the present invention.
FIG. 4 is a plan view of a pattern for electrically measuring erosion generated by the measurement and specifying a generated position.

FIG. 13 is a cross-sectional view of a pattern for electrically measuring erosion and dishing generated by the CMP in FIG.

FIG. 14 is a plan view of a pattern for electrically measuring erosion generated by CMP according to the sixth embodiment of the present invention and specifying a generated position.

FIG. 15 is a plan view of a pattern for electrically measuring dishing generated by CMP according to the seventh embodiment of the present invention and specifying a generated position.

FIG. 16 is a schematic explanatory view of conventional chemical mechanical polishing.

[Explanation of symbols]

1 A portion for measuring a film thickness to be polished by CMP 2 A hole dense pattern 3 A wide oxide film space for separating a hole dense pattern 4 A width of a silicon oxide film space 5 A cross-sectional view of a silicon oxide film 6 A hole dense Cross-sectional view by pattern 7 Cross-sectional view of space of silicon oxide film 8 Portion of measuring film thickness to be polished after CMP 9 Metal line dense pattern 10 Space of silicon oxide film 11 Space width of silicon oxide film 12 Polishing by CMP Cross-sectional view of portion to be measured after polishing 13 Cross-sectional view by metal line dense pattern 14 Cross-sectional view of silicon oxide film space 15 Portion to measure polishing film thickness after polishing by CMP 16 Metal pattern 17 Silicon oxide film Space 18 Silicon oxide film space width 19 Polishing after polishing by CMP Sectional view of portion for measuring polishing film thickness 20 Sectional view of metal pattern 21 Sectional view of silicon oxide film space 22 First interconnect 23 Pad 24 Hole 25 Second interconnect 26 Pad 27 First interconnect 28 Pad 29 Hole 30 Hole 31 Second wiring 32 Pad 33 First wiring 34 Hole 35 Hole 36 Second wiring 37 Pad 38 First wiring 39 Cross section of first wiring 40 Hole 41 Interlayer insulating film 42 Cross section of second wiring FIG. 43 Cross-sectional view of the first wiring 44 Cross-sectional view of the pattern in which the pattern density of holes is changed 45 Hole 46 Cross-sectional view of the second wiring 47 The pattern in which the pattern density of the hole dense pattern is constant and the mask size is changed 48 holes Varying pattern density of dense pattern 49 Pad 50 Pattern of metal line pattern 51 metal line pattern 52 to be polished film formed under the pattern 53 to be polished film 54 to be polished film 55 erosion 56 dishing which the pattern density is varied in that by changing the mask size in degrees constant

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Tetsuo Ishida 1-1, Yukicho, Takatsuki-shi, Osaka Matsushita Electronics Co., Ltd. (72) Inventor Mitsunari Satake 1-1, Yukicho, Takatsuki-shi, Osaka Matsushita Electronics Industrial Co., Ltd. F term (reference) 4M106 AA12 AB15 AB17 AC02 BA14 CA10 CA48 CA70 DH57

Claims (14)

[Claims] An evaluation method of a semiconductor device for measuring a step in a dense region of a hole pattern, which is generated by chemically and mechanically polishing a substrate, comprising: a residual film measurement capable of optically measuring a central portion of a pattern and a peripheral portion of the pattern. A method of evaluating a semiconductor device, comprising: providing a pattern; measuring the film thickness of each of the remaining film measurement patterns; and obtaining a step in the hole pattern dense region based on the measured value. 2. A method for evaluating a semiconductor device, comprising measuring a step in a dense hole pattern region caused by chemical mechanical polishing of a substrate, the method comprising the steps of: Having, provided a residual film measurement pattern that can be optically measured at the center of the pattern and the periphery of the pattern, measure the film thickness, determine the step in the hole pattern dense region based on the measured value, and further determine the pattern density and A method for evaluating a semiconductor device, comprising: determining a relationship between steps. 3. The method for evaluating a semiconductor device according to claim 1, wherein the width of the remaining film measurement pattern at the peripheral portion of the pattern is 100 μm or more. 4. An insulating film is formed on a substrate, and a first
Forming a pattern of a hole pattern dense area on the first wiring, and performing chemical mechanical polishing of the pattern; and forming a second wiring on the pattern. Forming a hole for conducting the first wiring and the second wiring at the center of the pattern, and applying a voltage between the first wiring and the second wiring to reduce the resistance thereof. A step of detecting a difference in film thickness and obtaining a step generated by polishing electrically. 5. A method for evaluating a semiconductor device, comprising measuring a step in a dense line pattern region caused by chemically and mechanically polishing a substrate, wherein a residual film measurement capable of optically measuring a central portion of the pattern and a peripheral portion of the pattern. A method for evaluating a semiconductor device, comprising: providing a pattern; measuring the film thickness of each of the remaining film measurement patterns; and obtaining a step in the dense line pattern region based on the measured value. 6. A method for evaluating a semiconductor device, comprising measuring a step in a dense line pattern region caused by chemically mechanically polishing a substrate, comprising the steps of: Having, provided a residual film measurement pattern that can be optically measured at the center of the pattern and the periphery of the pattern to measure the film thickness, determine the step of the line pattern dense region based on the measured value, furthermore, the pattern density and A method for evaluating a semiconductor device, comprising: determining a relationship between steps. 7. The method for evaluating a semiconductor device according to claim 5, wherein the width of the residual film measurement pattern at the peripheral portion of the pattern is 100 μm or more. 8. An insulating film is formed on a substrate, and a first
Forming a pattern of a line pattern dense region on the first wiring by a chemical mechanical polishing method, and forming a second wiring on the pattern; Providing a hole for conducting the first wiring and the second wiring at the center of the pattern; and applying a voltage between the first wiring and the second wiring to reduce the thickness of the pattern from its resistance. Detecting the difference and obtaining a step generated by polishing electrically. 9. A method for evaluating a semiconductor device, comprising measuring a step in a pattern region having a large groove width surrounded by metal, which is generated by chemically and mechanically polishing a substrate. An optically measurable residual film measurement pattern is provided, a film thickness of the residual film measurement pattern is measured, and a step in a large groove width pattern region surrounded by the metal is obtained based on the measured value. Evaluation method of semiconductor device. 10. A method for evaluating a semiconductor device, comprising measuring a step in a pattern region having a large groove width surrounded by a metal, which is generated by chemically and mechanically polishing a substrate, wherein the groove width surrounded by the metal is measured. It has a plurality of patterns in which the area of the metal is changed in a large pattern region, and provides an optically measurable residual film measurement pattern at the central portion and the peripheral portion of each pattern, and measures the film thickness. A step of obtaining a step in a pattern region having a large groove width surrounded by the metal based on the value, and further obtaining a relation between an area of the metal and a step in the pattern region having a large groove width surrounded by the metal. Device evaluation method. 11. The method for evaluating a semiconductor device according to claim 9, wherein the width of the residual film measurement pattern at the peripheral portion of the pattern is 100 μm or more. 12. A step of forming an insulating film on a substrate and forming a first wiring thereon, and forming a pattern in a pattern region having a large groove width surrounded by metal on the first wiring. Forming by a mechanical and mechanical polishing method, forming a second wiring on the pattern, and providing a hole for conducting the first and second wirings at the center of the pattern. Process, the first wiring and the second
Applying a voltage between the wirings to detect a difference in film thickness from the resistance thereof, and obtaining a step generated by polishing electrically. 13. A step of forming an insulating film on a substrate and forming a first wiring thereon, a step of forming an interlayer insulating film on the first wiring, and a chemical mechanical Forming a hole by a selective polishing method, further forming a second wiring thereon so as to be orthogonal to the first wiring, and conducting the first wiring and the second wiring by the hole. Applying a voltage between the first wiring and the second wiring, detecting a difference in film thickness from the resistance thereof, and obtaining a step generated by polishing electrically. . 14. A step of forming an insulating film on a substrate, forming a groove on the insulating film, embedding a metal film in the groove, and thereafter forming a first wiring by a chemical mechanical polishing method. And a step of applying a voltage to both ends of the first wiring, detecting a difference in film thickness from the resistance thereof, and obtaining a step generated by polishing electrically.