CN116248814A - Control device and control method for transmitting video data by utilizing double-edge trigger - Google Patents

Control device and control method for transmitting video data by utilizing double-edge trigger Download PDF

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Publication number
CN116248814A
CN116248814A CN202310244381.7A CN202310244381A CN116248814A CN 116248814 A CN116248814 A CN 116248814A CN 202310244381 A CN202310244381 A CN 202310244381A CN 116248814 A CN116248814 A CN 116248814A
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China
Prior art keywords
double
data
video
edge
input end
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CN202310244381.7A
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Chinese (zh)
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银小兵
刘爱明
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Beijing Weiming Huiyan Technology Co ltd
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Beijing Weiming Huiyan Technology Co ltd
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Priority to CN202310244381.7A priority Critical patent/CN116248814A/en
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/222—Studio circuitry; Studio devices; Studio equipment
    • H04N5/262—Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects
    • H04N5/268—Signal distribution or switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/234—Processing of video elementary streams, e.g. splicing of video streams, manipulating MPEG-4 scene graphs
    • H04N21/23418—Processing of video elementary streams, e.g. splicing of video streams, manipulating MPEG-4 scene graphs involving operations for analysing video streams, e.g. detecting features or characteristics
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/234—Processing of video elementary streams, e.g. splicing of video streams, manipulating MPEG-4 scene graphs
    • H04N21/2343—Processing of video elementary streams, e.g. splicing of video streams, manipulating MPEG-4 scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements
    • H04N21/234381—Processing of video elementary streams, e.g. splicing of video streams, manipulating MPEG-4 scene graphs involving reformatting operations of video signals for distribution or compliance with end-user requests or end-user device requirements by altering the temporal resolution, e.g. decreasing the frame rate by frame skipping
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
    • H04N21/44008—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving operations for analysing video streams, e.g. detecting features or characteristics in the video stream
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/44—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs
    • H04N21/4402—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display
    • H04N21/440281—Processing of video elementary streams, e.g. splicing a video clip retrieved from local storage with an incoming video stream, rendering scenes according to MPEG-4 scene graphs involving reformatting operations of video signals for household redistribution, storage or real-time display by altering the temporal resolution, e.g. by frame skipping

Abstract

The invention relates to a control device and a control method for transmitting video data by utilizing a double-edge trigger, wherein the control device comprises a video decoder chip and a video display interface chip, a video signal selection device is arranged between the video decoder chip and the video display interface chip, the video signal selection device comprises the double-edge trigger and two double-way data selectors, and the positive-edge input end of the double-edge trigger is connected with the output end of a first double-way data selector; the negative edge input end of the double-edge trigger is connected with the output end of the second double-path data selector; the selection signal inputs of the two-way data selector are connected to the sel signal. The invention utilizes a control device and a control method for transmitting video data by using a double-edge trigger, and adopts the double-edge trigger to generate DDR and SDR signals; the final logic of data output is fixed regardless of DDR or SDR signals, so that the certainty of input and output time sequence is ensured, the circuit is simplified, the transmission cost is reduced, and the video data transmission efficiency is improved.

Description

Control device and control method for transmitting video data by utilizing double-edge trigger
Technical Field
The present invention relates to a video data processing method, and in particular, to a control device and a control method for transmitting video data by using a dual edge trigger.
Background
In the digital video industry, the chip responsible for generating video, such as the video decoder chip (rear Wen Tongchen source chip) is often separate from the chip pushing the video to a computer display screen or television screen (video display interface chip). One of the more common formats in these two inter-chip video data interaction schemes is a control signal such as a line-field sync signal (hs, vs, de), a data signal such as video data (rgb/yuv), and a video clock (pixel_clk). The video clock may vary but the format of the interface signal does not vary for different resolutions, such as a standard definition (720 x576@60 fps) resolution corresponding to a 27Mhz video clock and a high definition (1920 x1080@60 fps) resolution corresponding to a 148.5Mhz video clock.
The bottom interface of the video interaction scheme generally depends on LVCMOS, and is mainly characterized by point-to-point single-ended transmission. The socket is effective in standard, so that the socket is not used for many years in the industry. But in recent years, as video resolution goes from traditional standard definition to 4K, this set of socket standards begins to face challenges. Because if one wants to reuse the existing interface for video data interaction, one natural idea is to further increase the frequency of the video clock, say 4k@30fps corresponds to a clock frequency of 297Mhz, the problem is solved if one can increase the video clock to 297Mhz, but unfortunately the level standard (LVCMOS) of the physical interface is very difficult to support the interface signal running to over 200Mhz. To reuse existing standards without increasing the clock frequency, the more common video display interface chips in the industry support basically what is known as DDR mode in that the frequency of the video clock does not need to run to 297Mhz, but only to half of it, i.e., 148.5Mhz, while transmitting video data at the same time on both the top and bottom edges of the clock, such video data having a bandwidth equivalent to SDR (i.e., single edge mode) transmission at 297 Mhz. This is a very good idea, but its challenge is that the source chip must also support more than 4K resolution SDR signals and other lower resolution SDR signals.
For the source chip, a double-edge trigger (DDR flop) is generally required for generating the DDR interface signal, and a single-edge trigger (SDR flop) is generally only required for generating the SDR interface signal, which is a knowledge of the engineering world.
Then DDR (4K resolution) and SDR (below 4K resolution) modes must be selected using combinational logic (such as a multiplexer) before exiting the IO, if the clock-to-data-out delay of the last stage register is noted as t0 (commonly known in the industry as clk-to-q delay), the data-out-to-chip pad delay is noted as t1, and the pad delay itself is noted as t2. The total delay of the video data can be expressed as t=t0+t1+t2.
For the prior art, data at different resolutions must first pass through two sets of registers of different types, and it is not possible to consider the different types of registers to be identical in terms of their end-to-data output delay (clk-to-q delay), i.e., t0 is related to resolution (even though there is some variance in clk-to-q delay among individuals of the same type of registers).
In addition, there are two paths from the data output end to the chip pad (refer to 4k_path and 1080p_path in fig. 3), and the delays t1 of the two paths also differ (mainly, the lengths of the wires corresponding to the two paths differ, and then the delays of the 0 end and the 1 end of the multiplexer also differ). The total delay of the data output at the different resolutions of the conventional method cannot be kept unchanged. At least two conditions of IO time sequence are caused, which inevitably generates considerable challenges to time sequence constraint of interconnection among chips, and if the time sequence among interfaces of interconnection is not satisfied, data cannot be normally transmitted.
Disclosure of Invention
In order to overcome the defects in the prior art, the invention provides a control method for transmitting video data by utilizing a double-edge trigger, which has the advantages of simplifying a circuit, reducing transmission cost and improving video data transmission efficiency and reliability.
The technical scheme adopted by the invention is as follows:
the control device for transmitting video data by utilizing the double-edge trigger comprises a video decoder chip and a video display interface chip, wherein a video signal selection device is arranged between the video decoder chip and the video display interface chip and comprises the double-edge trigger and two double-way data selectors, and the positive-edge input end of the double-edge trigger is connected with the output end of the first double-way data selector; the negative edge input end of the double-edge trigger is connected with the output end of the second double-path data selector; the selection signal input ends of the two-way data selectors are connected with the sel signal;
the first input end of the first two-way data selector is connected with 4K data positive edge data;
the second input end of the first two-way data selector is connected with a 1080p data output end;
the first input end of the second double-way data selector is connected with the negative edge data of the 4K data;
the second input end of the second double-way data selector is connected with 1080p data;
the second input end of the first two-way data selector is connected in parallel with the second input end of the second two-way data selector.
The CLK terminal of the dual edge flip-flop is connected to the pixel_clk signal.
A transmission video data control method of an apparatus for transmitting video data using a dual edge trigger, comprising the steps of:
step S101, starting;
step S102, inputting video signals;
step S103, determining whether the resolution of the video signal is 4k30, if so, jumping to step S104, otherwise jumping to step S107,
step S104, the two-way data selector sets sel to 1;
step S105, configuring a clock frequency corresponding to pixel_clk resolution;
step S106, respectively inputting different video data by the positive edge input end Dp/the negative edge input end Dn of the double-edge trigger;
step S107, the two-way data selector sets sel to 0;
step S108, configuring a clock frequency corresponding to pixel_clk resolution;
step S109, the same video data is input from the positive edge input end Dp/the negative edge input end Dn of the dual edge flip-flop
Step S110, the output end of the double-edge trigger outputs video data;
step S111 ends.
Compared with the prior art, the invention has the beneficial effects that:
the invention uses the control method of the double-edge trigger to transmit video data, simplifies the circuit, reduces the transmission cost, improves the video data transmission efficiency, and improves the stability and reliability of the transmitted data.
The invention utilizes the control method of the double-edge trigger to transmit video data, and adopts the double-edge trigger to generate DDR and SDR signals; the last level of logic of its data output, whether DDR or SDR signals, is fixed, ensuring certainty of the input-output (IO) timing, which is a point of pain where inter-chip interconnects in video systems are not bypassed.
The control method for transmitting video data by utilizing the double-edge trigger is particularly important for the design of generating video by using the FPGA and has considerable value for the design of ASIC video output.
The invention solves the practical problem of data exchange between the information source chip and the video interface chip, and can be also expanded to all occasions needing to use DDR and SDR simultaneously.
Drawings
FIG. 1 is a schematic diagram of data transmission of a prior art video decoder chip and video display interface chip;
FIG. 2 is a schematic diagram of DDR and SDR data transfers of a prior art video decoder chip and video display interface chip;
fig. 3 is a schematic diagram of a prior art structure for transmitting video data between a video decoder chip and a video display interface chip.
FIG. 4 is a schematic diagram of a video decoder chip and a video display interface chip of a control device for transmitting video data using dual edge triggers according to the present invention;
fig. 5 is a control flow chart of a control method of transmitting video data using a dual edge trigger according to the present invention.
Detailed Description
The invention is described in detail below with reference to the attached drawings and examples:
1-5, a control device for transmitting video data by using a dual-edge trigger includes a video decoder chip and a video display interface chip, wherein a video signal selecting device is arranged between the video decoder chip and the video display interface chip, the video signal selecting device includes a dual-edge trigger and two-way data selectors, and the positive edge input end of the dual-edge trigger is connected with the output end of a first two-way data selector; the negative edge input end of the double-edge trigger is connected with the output end of the second double-path data selector; the selection signal input ends of the two-way data selectors are connected with the sel signal;
the first input end of the first two-way data selector is connected with 4K data positive edge data;
the second input end of the first two-way data selector is connected with a 1080p data output end;
the first input end of the second double-way data selector is connected with the negative edge data of the 4K data;
the second input end of the second double-way data selector is connected with 1080p data;
the second input end of the first two-way data selector is connected in parallel with the second input end of the second two-way data selector.
The CLK terminal of the dual edge flip-flop is connected to the pixel_clk signal.
A transmission video data control method of a control device for transmitting video data using a dual edge trigger, comprising the steps of:
step S101, starting;
step S102, inputting video signals;
step S103, determining whether the resolution of the video signal is 4k30, if so, jumping to step S104, otherwise jumping to step S107,
step S104, the two-way data selector sets sel to 1;
step S105, configuring a clock frequency corresponding to pixel_clk resolution;
step S106, respectively inputting different video data by the positive edge input end Dp/the negative edge input end Dn of the double-edge trigger;
step S107, the two-way data selector sets sel to 0;
step S108, configuring a clock frequency corresponding to pixel_clk resolution;
step S109, the same video data is input from the positive edge input end Dp/the negative edge input end Dn of the dual edge flip-flop
Step S110, the output end of the double-edge trigger outputs video data;
step S111 ends.
The control method of the invention for transmitting video data by utilizing the double-edge trigger, because the selection logic of the data path is in front of the data input end of the register, as long as the time point of the video data reaching the data input end of the register meets the time constraint such as establishment, holding time (which is known as setup hold timing in the industry) and the like, even if the data input end of the register is different due to different branches of the multiplexer, namely, the video data with different resolutions has difference (see fig. 4), the difference does not affect any one of t0/t1/t2 at all.
The control method for transmitting video data by utilizing the double-edge trigger is particularly important to the design of the FPGA, because the double-edge register of the FPGA is usually designed near the pad, and a multiplexer is not inserted on the path from the output of the double-edge register to the pad.
Taking fig. 4 as an example, a typical video output flow is as follows: it is first clear that the resolution of the video in any period of time can only be a certain, either 1080p, or 4k30, or other resolution lower than 1080p, such as 576p, the application designer should set the resolution according to the user's needs (e.g. the user selects the current output resolution by means of a command line or an image interface), if the user needs to output 1080p and below, the application must set sel to 0, if the user needs to output 4k30, then set sel to 1.
The software then configures pixel_clk to the clock frequency corresponding to the resolution (e.g., 1080p and 4k30 are both 148.5Mhz,720p is 74.25Mhz, and 576p is 27 Mhz) and enables the clock, and finally outputs 1080p_data (if 1080p resolution) or 4k30_data_p/4k30_data_n (if 4k30 resolution) and hs/vs/de control signals corresponding to the resolution.
As in fig. 4, the multiplexer selects 1080p data channels if sel is 0 and selects 4k30 data channels if sel is 1.
The control system distinguishes according to user requirements, which require the user to decide the current resolution, e.g. the display resolution is adjusted manually.
For 1080p and 4k30, the clock frequencies used are 148.5Mhz, except that the former uses only positive (SDR) and the latter uses both positive and negative (DDR) edges.
For other resolutions such as 720p,576p, etc., the frequency of pixel_clk may decrease, such as 720p typically 74.25Mhz and 576p typically 27Mhz pixel_clk. The present invention and the prior art do so.
The invention utilizes the control method of the double-edge trigger to transmit video data, and adopts the double-edge trigger to generate DDR and SDR signals; the last level of logic of its data output, whether DDR or SDR signals, is fixed, ensuring certainty of the input-output (IO) timing, which is a point of pain where inter-chip interconnects in video systems are not bypassed.
The control method for transmitting video data by utilizing the double-edge trigger is particularly important for the design of generating video by using the FPGA and has considerable value for the design of ASIC video output.
The invention solves the practical problem of data exchange between the information source chip and the video interface chip, and can be also expanded to all occasions needing to use DDR and SDR simultaneously.
The invention uses the control method of the double-edge trigger to transmit video data, for 4K resolution, the positive edge input end (Dp)/negative edge input end (Dn) of the double-edge trigger are respectively connected with different inputs, for resolution below 4K, the positive edge input end and the negative edge input end of the double-edge register are connected with the same input, in this case, the net effect is equivalent to a single-edge register. The invention utilizes the point to achieve the purpose of sharing and outputting the final stage circuit for the multi-resolution image, and has the advantages that the final stage path is identical regardless of the resolution, and the board stage does not need to consider various conditions.
The above description is only of the preferred embodiment of the present invention, and is not intended to limit the structure of the present invention in any way. Any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present invention fall within the technical scope of the present invention.

Claims (3)

1. The utility model provides a utilize controlling means of two edge trigger transmission video data, includes video decoder chip and video display interface chip, is provided with video signal selecting arrangement between video decoder chip and the video display interface chip, its characterized in that: the video signal selecting device comprises a double-edge trigger and two double-path data selectors, wherein the positive-edge input end of the double-edge trigger is connected with the output end of the first double-path data selector; the negative edge input end of the double-edge trigger is connected with the output end of the second double-path data selector; the selection signal input ends of the two-way data selectors are connected with the sel signal;
the first input end of the first two-way data selector is connected with 4K data positive edge data;
the second input end of the first two-way data selector is connected with a 1080p data output end;
the first input end of the second double-way data selector is connected with the negative edge data of the 4K data;
the second input end of the second double-way data selector is connected with 1080p data;
the second input end of the first two-way data selector is connected in parallel with the second input end of the second two-way data selector.
2. The control device for transmitting video data using a dual edge trigger according to claim 1, wherein: the CLK terminal of the dual edge flip-flop is connected to the pixel_clk signal.
3. A transmission video data control method of the apparatus for transmitting video data using a double edge trigger as claimed in any one of claims 1 or 2, characterized by: the method comprises the following steps:
step S101, starting;
step S102, inputting video signals;
step S103, determining whether the resolution of the video signal is 4k30, if so, jumping to step S104, otherwise jumping to step S107,
step S104, the two-way data selector sets sel to 1;
step S105, configuring a clock frequency corresponding to pixel_clk resolution;
step S106, respectively inputting different video data by the positive edge input end Dp/the negative edge input end Dn of the double-edge trigger;
step S107, the two-way data selector sets sel to 0;
step S108, configuring a clock frequency corresponding to pixel_clk resolution;
step S109, the same video data is input from the positive edge input end Dp/the negative edge input end Dn of the dual edge flip-flop
Step S110, the output end of the double-edge trigger outputs video data;
step S111 ends.
CN202310244381.7A 2023-03-14 2023-03-14 Control device and control method for transmitting video data by utilizing double-edge trigger Pending CN116248814A (en)

Priority Applications (1)

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CN202310244381.7A CN116248814A (en) 2023-03-14 2023-03-14 Control device and control method for transmitting video data by utilizing double-edge trigger

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202310244381.7A CN116248814A (en) 2023-03-14 2023-03-14 Control device and control method for transmitting video data by utilizing double-edge trigger

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CN116248814A true CN116248814A (en) 2023-06-09

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