CN116247069B - Semiconductor structure, preparation method thereof and back-illuminated image sensor - Google Patents
Semiconductor structure, preparation method thereof and back-illuminated image sensor Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1463—Pixel isolation structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14601—Structural or functional details thereof
- H01L27/1464—Back illuminated imager structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
- H01L27/144—Devices controlled by radiation
- H01L27/146—Imager structures
- H01L27/14683—Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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Abstract
The disclosure relates to the technical field of integrated circuit design and manufacturing, in particular to a semiconductor structure and a preparation method thereof, and a back-illuminated image sensor, wherein the semiconductor structure comprises a substrate, a barrier layer, a second isolation structure and a functional layer; the substrate is provided with a first surface and a second surface, first isolation structures are formed in the substrate in a spaced arrangement mode, and the first isolation structures extend towards the second surface of the substrate through the first surface of the substrate; the barrier layer extends along a first direction and covers the surface of the first isolation structure, which is close to the second surface of the substrate; the second isolation structures are formed in the substrate and are arranged at intervals along the first direction, and the second isolation structures extend towards the first surface of the substrate through the second surface of the substrate at least to the surface, close to the second surface of the substrate, of the barrier layer; the functional layer is formed in the substrate and is positioned between the second isolation structures adjacent along the first direction. The insulation effect around the functional layer can be enhanced, and the undesirable effects such as crosstalk and the like are avoided, so that the quality of an output image is improved.
Description
Technical Field
The present disclosure relates to integrated circuit design and manufacturing technology, and more particularly, to a semiconductor structure, a method for manufacturing the same, and a backside illuminated image sensor.
Background
A complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, abbreviated as CMOS) image sensor is a device for converting an optical image into an electrical signal, and is widely used in the fields of smart phones, monitoring security, automotive electronics, machine security, and the like. Compared with a charge coupled device (Charge Coupled Device, CCD for short) image sensor, the CMOS image sensor has the advantages of low power consumption, small size and the like. For example, a backside illuminated incident (Back Side Illumination, BSI) CMOS image sensor can improve light utilization and dark imaging quality by changing the direction of light incidence.
However, in the conventional back-illuminated image sensor, the incident light directly irradiates the substrate material near the photodiode, and the light at the back of the substrate material may diffuse to the adjacent pixel cells due to poor insulation effect around the pixel cells of the conventional back-illuminated image sensor, and the diffuse light and the incident light are recombined, so that crosstalk is not ideal, and the quality of the output image is reduced.
Disclosure of Invention
Based on the above, the disclosure provides a semiconductor structure, a preparation method thereof and a back-illuminated image sensor, which can at least strengthen the insulation effect around the functional layer, avoid the undesirable effect of crosstalk, and further improve the quality of an output image.
To solve the above technical problems and other problems, according to some embodiments, an aspect of the present disclosure provides a semiconductor structure including a substrate, a barrier layer, a second isolation structure, and a functional layer; the substrate is provided with a first surface and a second surface which are opposite along the thickness direction, first isolation structures which are arranged at intervals along the first direction are formed in the substrate, and the first isolation structures extend towards the second surface of the substrate through the first surface of the substrate; the first direction is perpendicular to the thickness direction of the substrate; the barrier layer extends along a first direction and covers the surface of the first isolation structure, which is close to the second surface of the substrate; the second isolation structures are formed in the substrate and are arranged at intervals along the first direction, and the second isolation structures extend towards the first surface of the substrate through the second surface of the substrate at least to the surface, close to the second surface of the substrate, of the barrier layer; the functional layer is formed in the substrate and is positioned between the second isolation structures adjacent along the first direction.
In the semiconductor structure of the embodiment, the barrier layer extending along the first direction and covering the surface of the first isolation structure in the substrate close to the second surface of the substrate, and the second isolation structure extending at least to the surface of the barrier layer close to the second surface of the substrate towards the first surface of the substrate via the second surface of the substrate, so that the bottom-closed isolation structure formed by the second isolation structure and the barrier layer is formed between the functional layer and the first isolation structure and between the adjacent functional layers, thereby enhancing the insulation effect around the functional layers, avoiding the undesirable effects such as crosstalk and the like caused by the recombination of diffuse light generated by diffusing light to adjacent pixel units and incident light, and improving the quality of output images.
In some embodiments, the barrier layer includes a first barrier layer and a second barrier layer stacked in sequence along a thickness direction of the substrate, the first barrier layer being located between the second barrier layer and the functional layer; and the second isolation structure extends at least to a surface of the first barrier layer close to the second surface of the substrate.
In some embodiments, the functional layer is located between adjacent first isolation structures along an orthographic projection of the thickness direction of the substrate on the first surface of the substrate.
In some embodiments, the semiconductor structure further includes a dielectric layer formed on the second surface of the substrate and covering the second isolation structure and a surface of the functional layer adjacent to the second surface of the substrate.
In some embodiments, the functional layer includes a photosensitive element; the semiconductor structure further comprises a photosensitive electrode, wherein the photosensitive electrode is formed on the surface, close to the second surface of the substrate, of the dielectric layer, and orthographic projection along the thickness direction of the substrate is located in the second isolation structure.
In some embodiments, the second isolation structure includes a first isolation layer and a second isolation layer; the first isolation layer is positioned on the surface of the barrier layer, which is close to the second surface of the substrate, and extends along the thickness direction of the substrate; the second isolation layer surrounds the bottom and the side walls of the first isolation layer.
According to some embodiments, another aspect of the present disclosure provides a backside illuminated image sensor comprising the semiconductor structure of any one of the above embodiments.
In the back-illuminated image sensor of the above embodiment, the bottom-closed isolation structure formed by the second isolation structure and the barrier layer is formed between the functional layer and the first isolation structure and between the adjacent functional layers, so that the insulation effect around the functional layer is enhanced, the undesirable effects such as crosstalk caused by recombination of diffuse light and incident light generated by diffusing light to adjacent pixel units are avoided, interference between pixel units in the image sensor is avoided, and generation of dark current or white pixels in the image sensor can be effectively avoided, so that the quality of an output image is improved.
According to some embodiments, a further aspect of the present disclosure provides a method for preparing a semiconductor structure, comprising the steps of: providing a substrate, wherein the substrate is provided with a first surface of the substrate and a second surface of the substrate which are opposite in the thickness direction of the substrate, and first isolation structures which are arranged at intervals in the first direction are formed in the substrate; the first isolation structure extends towards the second surface of the substrate via the first surface of the substrate; the first direction is perpendicular to the thickness direction of the substrate; forming a barrier layer extending along the first direction, wherein the barrier layer covers the surface of the first isolation structure close to the second surface of the substrate; forming second isolation structures which are arranged at intervals along the first direction in the substrate, wherein the second isolation structures extend to at least the surface of the barrier layer, which is close to the second surface of the substrate, towards the first surface of the substrate through the second surface of the substrate; a functional layer is formed in the substrate, and the functional layer is located between the second isolation structures adjacent along the first direction.
In the method for manufacturing a semiconductor structure in the above embodiment, the barrier layer extending along the first direction and covering the surface of the first isolation structure in the substrate close to the second surface of the substrate, and the second isolation structure extending at least to the surface of the barrier layer close to the second surface of the substrate via the second surface of the substrate towards the first surface of the substrate, thereby forming a bottom-closed isolation structure between the functional layer and the first isolation structure and between adjacent functional layers and formed by the second isolation structure and the barrier layer, thereby enhancing the insulation effect around the functional layer, avoiding the crosstalk non-ideal effect caused by the recombination of diffuse light and incident light generated by the diffusion of light to adjacent pixel units, and improving the quality of an output image.
In some embodiments, forming the barrier layer extending along the first direction includes: sequentially forming a first barrier layer and a second barrier layer which are laminated along the thickness direction of the substrate, wherein the first barrier layer is positioned between the second barrier layer and the functional layer; the second isolation structure extends at least to a surface of the first barrier layer adjacent to the second surface of the substrate.
In some embodiments, forming second isolation structures therein spaced apart along the first direction includes: forming a groove in the substrate, wherein the groove extends towards the first surface at least to the surface of the barrier layer, which is close to the second surface of the substrate, through the second surface; forming a second isolation layer covering the surface of the trench; and filling the groove to form a first isolation layer covering the second isolation layer.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a cross-sectional illustration of a semiconductor structure in an embodiment of the present disclosure;
FIG. 2 is a cross-sectional illustration of a semiconductor structure in another embodiment of the present disclosure;
FIG. 3 is a flow chart illustrating a method of fabricating a semiconductor structure in an embodiment of the present disclosure;
FIG. 4 is a schematic cross-sectional view of the structure obtained in step S10 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
FIG. 5 is a schematic cross-sectional view of a functional region formed in step S40 in a method of fabricating a semiconductor structure according to an embodiment of the present disclosure;
FIG. 6 is a schematic cross-sectional view of a structure obtained in step S20 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
FIG. 7 is a schematic cross-sectional view of a structure obtained in step S30 in a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 8 is a schematic cross-sectional view of a dielectric layer and a photosensitive electrode formed in a method for fabricating a semiconductor structure according to an embodiment of the disclosure.
Reference numerals illustrate:
10. a substrate; 101. a first surface; 102. a second surface; 20. a first isolation structure; 30. a barrier layer; 31. a first barrier layer; 32. a second barrier layer; 302. a barrier material layer; 40. a second isolation structure; 41. a first isolation layer; 42. a second isolation layer; 43. a groove; 50. a functional layer; 501. a functional area; 60. a photosensitive electrode; 70. a dielectric layer; 71. a first dielectric layer; 72. a second dielectric layer; 73. a third dielectric layer; 74. a fourth dielectric layer; 81. a fifth dielectric layer; 82. a sixth dielectric layer; 90. a bonding pad; 91. a polysilicon layer; 92. and a connection layer.
Detailed Description
In order that the disclosure may be understood, a more complete description of the disclosure will be rendered by reference to the appended drawings. Preferred embodiments of the present disclosure are shown in the drawings. This disclosure may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description of the disclosure herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present disclosure. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concepts of the disclosure by way of illustration, and only the components related to the disclosure are shown in the illustration, rather than being drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Referring to fig. 1, in a conventional back-illuminated image sensor, an isolation structure is generally formed on the back surface of a chip to separate different pixels, and second isolation structures 40 corresponding to the first isolation structures 20 are formed on two sides of a functional layer 50 to reduce signal crosstalk between adjacent pixels, however, because the second isolation structures 40 on two sides of the functional layer 50 are not completely insulated from the corresponding first isolation structures 20, when incident light directly irradiates a photosensitive element of the functional layer 50, such as a photodiode as a pixel unit, and a nearby substrate material, light on the back surface of the substrate material may diffuse into adjacent pixel units to generate diffuse light and rejoin the incident light, resulting in undesirable effects such as crosstalk, and reducing quality of an output image.
Based on the above, the disclosure provides a semiconductor structure, a preparation method thereof and a back-illuminated image sensor, which can at least strengthen the insulation effect around the functional layer, avoid the undesirable effects such as crosstalk and the like, and further improve the quality of an output image.
Referring to fig. 2, in accordance with some embodiments, a semiconductor structure is provided, the semiconductor structure including a substrate 10, a barrier layer 30, a second isolation structure 40, and a functional layer 50; the substrate 10 has a first surface 101 and a second surface 102 opposite to each other in a thickness direction thereof, first isolation structures 20 are formed in the substrate 10 at intervals in the first direction, and the first isolation structures 20 extend toward the second surface 102 of the substrate 10 via the first surface 101 of the substrate 10; the first direction may be an OX direction, and the thickness direction of the substrate 10 may be an OY direction, the first direction being perpendicular to the thickness direction of the substrate 10; the barrier layer 30 extends along the first direction and covers a surface of the first isolation structure 20 adjacent to the second surface 102 of the substrate 10; the second isolation structures 40 are formed in the substrate 10 and are arranged at intervals along the first direction, and the second isolation structures 40 extend towards the first surface 101 of the substrate 10 via the second surface 102 of the substrate 10 at least to the surface of the barrier layer 30 close to the second surface 102 of the substrate 10; the functional layer 50 is formed within the substrate 10 and is located between the second isolation structures 40 adjacent in the first direction.
In the semiconductor structure of the above embodiment, the insulating effect around the functional layer 50 is enhanced by the barrier layer 30 extending along the first direction and covering the surface of the first isolation structure 20 in the substrate 10 near the second surface 102 of the substrate 10, and the second isolation structure 40 extending toward the first surface 101 of the substrate 10 via the second surface 102 of the substrate 10 to at least the surface of the barrier layer 30 near the second surface 102 of the substrate 10, so that the bottom-closed isolation structure formed by the second isolation structure 40 and the barrier layer 30 is formed between the functional layer 50 and the first isolation structure 20 and between the adjacent functional layers 50, thereby enhancing the insulating effect around the functional layer 50, and avoiding the undesirable effects such as crosstalk caused by the recombination of diffuse light and incident light generated by the diffusion of light to the adjacent pixel units, thereby improving the quality of the output image.
With continued reference to fig. 2, in some embodiments, the substrate 10 may be formed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate 10 is a semiconductor structure that provides mechanical support and electrical properties for fabricating a semiconductor device, and the substrate 10 may be a single-layer structure or a multi-layer structure. For example, the substrate 10 may be a III/V semiconductor substrate 10 or a II/VI semiconductor substrate 10. Those skilled in the art may select the type of substrate 10 based on the type of transistor formed on substrate 10, and thus the type of substrate 10 should not limit the scope of the present disclosure.
With continued reference to fig. 2, in some embodiments, the first isolation structure 20 may employ a shallow trench isolation structure (Shallow Trench Isolation, STI for short) to isolate two adjacent devices, so as to prevent failure caused by current flowing between the adjacent devices, where the shallow trench isolation structure may reduce the area occupied by the wafer surface, increase the integration level of the devices, maintain the flatness of the wafer surface, and reduce the risk of channel width erosion; with continued reference to fig. 2, in some embodiments, the second isolation structure 40 may employ a deep trench isolation structure (Deep Trench Isolation, DTI for short) to achieve an insulating effect on both sides of the functional layer 50, so as to avoid undesirable effects such as crosstalk.
With continued reference to fig. 2, in some embodiments, the second isolation structure 40 includes a first isolation layer 41 and a second isolation layer 42; the first isolation layer 41 is located on a surface of the barrier layer 30 close to the second surface 102 of the substrate 10, and extends in the thickness direction of the substrate 10; the second isolation layer 42 surrounds the bottom and side walls of the first isolation layer 41; the material of the first isolation layer 41 includes Spin-on glass (Spin on Glass Coating, abbreviated as SOG), in which a liquid solvent containing a filler is uniformly coated on a surface to be filled in a Spin Coating manner, and then the solvent is removed by heat treatment, so that a solidified dielectric material similar to silicon dioxide is left on the surface to be filled; the second isolation layer 42 comprises an oxide layer, for example, the material of the second isolation layer 42 comprises silicon oxide.
With continued reference to fig. 2, in some embodiments, the barrier layer 30 includes a first barrier layer 31 and a second barrier layer 32 sequentially stacked along the thickness direction of the substrate 10, the first barrier layer 31 being located between the second barrier layer 32 and the functional layer 50; and the second isolation structure 40 extends via at least to a surface of the first barrier layer 31 adjacent to the second surface 102 of the substrate 10; since the second barrier layer 32 covers the first isolation structure 20 in the substrate 10, the first barrier layer 31 covers the second barrier layer 32, and the second isolation structure 40 extends at least to the surface of the first barrier layer 31 near the second surface 102 of the substrate 10, so that the corresponding first isolation structure 20 and second isolation structure 40 between the functional layers 50 are isolated from each other, and the insulation effect around the functional layers 50 is enhanced; in addition, since the second barrier layer 32 extends along the first direction, a bottom-closed isolation structure formed by the second isolation structure 40 and the barrier layer 30 is formed, so that the insulation effect around the functional layer 50 is enhanced, and the undesirable effects such as crosstalk caused by recombination of diffuse light and incident light generated by diffusing light to adjacent pixel units are avoided, thereby improving the quality of the output image.
With continued reference to fig. 2, in some embodiments, the material of the first barrier layer 31 includes boron; the material of the second barrier layer 32 includes silicon oxide; since the material of the first barrier layer 31 is different from the material of the substrate 10, the first barrier layer 31 can serve as an etch stop layer during the process of forming the second isolation structure 40, avoiding over etching.
With continued reference to fig. 2, in some embodiments, the semiconductor structure further includes a dielectric layer 70, where the dielectric layer 70 is formed on the second surface 102 of the substrate 10 and covers the second isolation structure 40 and the surface of the functional layer 50 near the second surface 102 of the substrate 10, so as to prevent electrons from overflowing; the dielectric layer 70 can be one layer or a plurality of layers, the insulating effect of the dielectric layer 70 is better, and the electronic overflow can be better prevented; in some embodiments, dielectric layer 70 includes a first dielectric layer 71, a second dielectric layer 72, a third dielectric layer 73, and a fourth dielectric layer 74 that are sequentially stacked on a second surface 102 of substrate 10; in some embodiments, the first dielectric layer 71 includes an oxide layer, the second dielectric layer 72 includes an aluminum oxide layer, the third dielectric layer 73 includes a thallium oxide layer, the fourth dielectric layer 74 includes a metal oxide layer, and the first dielectric layer 71, the second dielectric layer 72, the third dielectric layer 73, and the fourth dielectric layer 74 are all made of a compound material having a high dielectric constant; the thickness D1 of the first dielectric layer 71 along the direction of the substrate 10 ranges from 18 a to 22 a, for example, the thickness D1 of the first dielectric layer 71 may be 18 a, 19 a, 20 a, 21 a, 22 a, or the like; the thickness D2 of the second dielectric layer 72 along the direction of the substrate 10 ranges from 67.5 a to 82.5 a, for example, the thickness D2 of the second dielectric layer 72 may be 67.5 a, 70 a, 72.5 a, 75 a, 77.5 a, 80 a, 82.5 a, or the like; the thickness D3 of the third dielectric layer 73 along the direction of the substrate 10 ranges from 460 a to 580 a, for example, the thickness D3 of the third dielectric layer 73 may be 460 a, 480 a, 500 a, 520 a, 540 a, 560 a, 580 a, or the like; the thickness D4 of the fourth dielectric layer 74 along the direction of the substrate 10 ranges from 1600 a to 2000 a, for example, the thickness D4 of the fourth dielectric layer 74 may be 1600 a, 1700 a, 1800 a, 1900 a or 2000 a, etc.; the applicant has proved that, in the case where the dielectric layers include the first dielectric layer 71, the second dielectric layer 72, the third dielectric layer 73 and the fourth dielectric layer 74 which are sequentially stacked on the second surface 102 of the substrate 10, the first dielectric layer 71 includes an oxide layer, the second dielectric layer 72 includes an alumina layer, the third dielectric layer 73 includes a thallium oxide layer, the fourth dielectric layer 74 includes a metal oxide layer, and the thicknesses D1 to D4 of the first dielectric layer 71, the second dielectric layer 72, the third dielectric layer 73 and the fourth dielectric layer 74 respectively fall within the above-described ranges, the insulating effect of the dielectric layers is better; especially, under the conditions that the thickness D1 is 20 angstroms, the thickness D2 is 75 angstroms, the thickness D3 is 520 angstroms and the thickness D4 is 1800 angstroms, the optimal insulation effect in the experimental range can be achieved, so that the electrical protection of the functional layer 50 is better realized, and the reliability of the semiconductor device is improved. It should be noted that, the number of layers, materials and thickness of the dielectric layer 70 can be adjusted as required by those skilled in the art.
With continued reference to fig. 2, in some embodiments, the functional layer 50 is located between adjacent first isolation structures 20 along the front projection of the thickness direction of the substrate 10 on the first surface 101 of the substrate 10.
With continued reference to FIG. 2, in some embodiments, the functional layer 50 includes photosensitive elements; for example, the functional layer 50 includes a P-type semiconductor layer and an N-type semiconductor layer, for example, the photosensitive element may include a Photodiode (PD) having a characteristic of forward-turn-on and reverse-turn-off, and a characteristic of a capacitor, when a reverse bias voltage is applied to the photodiode, the capacitor is charged, and after the capacitor is fully charged, photon injection causes new electron hole pairs to be excited inside, and the electron hole pairs formed by the original charge are paired to discharge, so as to form a photocurrent, and the capacitor is charged with the photocurrent to become a voltage output, thereby realizing conversion between an optical signal and an electrical signal.
With continued reference to fig. 2, in some embodiments, the semiconductor structure further includes a photosensitive electrode 60, where the photosensitive electrode 60 is formed on a surface of the dielectric layer 70 near the second surface 102 of the substrate 10, and an orthographic projection along a thickness direction of the substrate 10 is located in the second isolation structure 40 for photosensitive color filtering; in some embodiments, the photosensitive electrode 60 includes a dielectric layer and a conductive layer sequentially stacked along the thickness direction of the substrate 10, and when the dielectric layer 70 has a multi-layered structure and includes at least one metal layer or metal compound layer, the photosensitive electrode 60 and the dielectric layer 70 may together form a composite metal grid (Composite Metal Grid, CMG), so as to further enhance the insulation effect and the electrical protection of the functional layer 50.
With continued reference to fig. 2, in some embodiments, the semiconductor structure further includes a pad 90, the pad 90 being located on the first surface 101 of the substrate 10. One end of the bonding pad 90, which is close to the substrate 10, may be connected to the functional layer 50 through a connection structure, and the other end of the bonding pad 90, which is away from the substrate 10, is used to bind the driving circuit board, so as to achieve signal transmission between the driving circuit board and the functional layer 50. In some embodiments, the connection structure between the pad 90 and the functional layer 50 includes a polysilicon layer 91 and a connection layer 92. The polysilicon layer 91 is disposed on the first surface 101 of the substrate 10, and the connection layer 92 is disposed between the pad 90 and the polysilicon layer 91. In some embodiments, an interlayer dielectric layer 70 is further disposed between the substrate 10 and the pad 90; the interlayer dielectric layer can be one layer or multiple layers. Illustratively, the interlayer dielectric layer includes a fifth dielectric layer 81 and a sixth dielectric layer 82 sequentially stacked on the first surface 101 of the substrate 10; fifth dielectric layer 81 comprises a silicon nitride layer, sixth dielectric layer 82 comprises an oxide layer, the material of pad 90 comprises copper, and connection layer 92 comprises a conductive metal layer.
With continued reference to fig. 2, in some embodiments, the distance L1 between the surfaces of the first dielectric layer 71 and the fifth dielectric layer 81 opposite to each other in the thickness direction of the substrate 10 may range from 2.5 μm to 3.5 μm, for example, the distance L1 may be 2.5 μm, 2.7 μm, 2.9 μm, 3.0 μm, 3.1 μm, 3.3 μm, 3.5 μm, etc.
With continued reference to fig. 2, in accordance with some embodiments, the present disclosure provides a backside illuminated image sensor comprising the semiconductor structure of any one of the above embodiments.
With continued reference to fig. 2, in the back-illuminated image sensor of the above embodiment, by forming the bottom-sealed isolation structure between the functional layer 50 and the first isolation structure 20 and between the adjacent functional layers 50, which is formed by the second isolation structure 40 and the barrier layer 30, the insulation effect around the functional layers 50 is enhanced, so as to avoid the undesirable effects such as crosstalk caused by the diffuse light generated by diffusing light into the adjacent pixel units and the recombination of the incident light, and to avoid the interference between the pixel units in the image sensor, and to effectively avoid the generation of dark current or white pixels in the image sensor, thereby improving the quality of the output image.
Referring to fig. 2 and 3, according to some embodiments, the disclosure provides a method for manufacturing a semiconductor structure, including the following steps:
step S10: providing a substrate 10, wherein the substrate 10 is provided with a first surface 101 of the substrate 10 and a second surface 102 of the substrate 10 which are opposite to each other along the thickness direction of the substrate 10, and first isolation structures 20 which are arranged at intervals along the first direction are formed in the substrate 10; the first isolation structures 20 extend towards the second surface 102 of the substrate 10 via the first surface 101 of the substrate 10; the first direction is perpendicular to the thickness direction of the substrate 10;
step S20: forming a barrier layer 30 extending along a first direction, the barrier layer 30 covering a surface of the first isolation structure 20 adjacent to the second surface 102 of the substrate 10;
step S30: forming second isolation structures 40 in the substrate 10 at intervals along the first direction, wherein the second isolation structures 40 extend toward the first surface 101 of the substrate 10 via the second surface 102 of the substrate 10 at least to a surface of the barrier layer 30 adjacent to the second surface 102 of the substrate 10;
step S40: a functional layer 50 is formed within the substrate 10, the functional layer 50 being located between the second isolation structures 40 adjacent in the first direction.
With continued reference to fig. 2 and 3, in the method for manufacturing a semiconductor structure according to the foregoing embodiments, in step S10 to step S40, the thickness direction of the substrate 10 may be the OY direction, the first direction may be the OX direction, the first isolation structure 20 may be a shallow trench isolation structure to isolate two adjacent devices, prevent failure caused by current flowing between the adjacent devices, the shallow trench isolation structure may reduce the area occupied by the wafer surface, increase the integration level of the devices, maintain the flatness of the wafer surface, and reduce the risk of channel width erosion, and the second isolation structure 40 may be a deep trench isolation structure; the barrier layer 30 extending along the first direction and covering the surface of the first isolation structure 20 in the substrate 10 close to the second surface 102 of the substrate 10, and the second isolation structure 40 extending towards the first surface 101 of the substrate 10 via the second surface 102 of the substrate 10 at least to the surface of the barrier layer 30 close to the second surface 102 of the substrate 10, thereby forming a bottom-closed isolation structure between the functional layer 50 and the first isolation structure 20 and between the adjacent functional layers 50 and formed by the second isolation structure 40 and the barrier layer 30, thereby enhancing the insulation effect around the functional layers 50, avoiding the crosstalk non-ideal effect caused by diffusing light to adjacent pixel units, and recombining diffused light and incident light, and improving the quality of the output image.
It should be understood that, although the steps in the flowchart of fig. 3 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, although at least a portion of the steps in FIG. 3 may include multiple steps or stages that are not necessarily performed at the same time, but may be performed at different times, the order in which the steps or stages are performed is not necessarily sequential, and may be performed in rotation or alternatively with at least a portion of the steps or stages in other steps or steps.
Referring to fig. 4, in some embodiments, before performing step S20, a step of cleaning the substrate 10 may be further included, and impurities on the surface of the substrate 10 may be removed by cleaning, so as to avoid affecting the subsequent process and further ensure the performance of the device. Specifically, the substrate 10 may be cleaned with a cleaning solution, and the substrate 10 may be placed in a cleaning tank in which the cleaning solution is stored for cleaning. The particular cleaning fluids and cleaning procedures used to clean the substrate 10 are known to those skilled in the art and will not be discussed in detail herein. It should be noted that, after the substrate 10 is cleaned, a step of drying the substrate 10 is further required, and a method of drying the substrate 10 is well known to those skilled in the art, and will not be described here.
Referring to fig. 4 to 6, in some embodiments, forming the barrier layer 30 extending along the first direction includes: sequentially forming a first barrier layer 31 and a second barrier layer 32 stacked in the thickness direction of the substrate 10, the first barrier layer 31 and the second barrier layer 32 extending in a first direction, which may be an OX direction, the first barrier layer 31 being located between the second barrier layer 32 and the functional layer 50; the second isolation structure 40 extends at least to a surface of the first barrier layer 31 adjacent to the second surface 102 of the substrate 10; since the second barrier layer 32 covers the first isolation structure 20 in the substrate 10, the first barrier layer 31 covers the second barrier layer 32, and the second isolation structure 40 extends at least to the surface of the first barrier layer 31 near the second surface 102 of the substrate 10, so that the corresponding first isolation structure 20 and second isolation structure 40 between the functional layers 50 are isolated from each other, and the insulation effect around the functional layers 50 is enhanced; in addition, since the second barrier layer 32 extends along the first direction, a bottom-closed isolation structure formed by the second isolation structure 40 and the barrier layer 30 is formed, so that the insulation effect around the functional layer 50 is enhanced, and the undesirable effects such as crosstalk caused by recombination of diffuse light and incident light generated by diffusing light to adjacent pixel units are avoided, thereby improving the quality of the output image.
Referring to fig. 4 to 6, in some embodiments, forming a first barrier layer 31 and a second barrier layer 32 stacked in sequence along a thickness direction of a substrate 10 includes: sequentially forming a first barrier layer 31 and a barrier material layer 302 which are stacked along the thickness direction of the substrate 10 by adopting a covering ion implantation process, wherein the first barrier layer 31 and the barrier material layer 302 extend along a first direction, the first direction can be an OX direction, and then treating the barrier material layer 302 by adopting an annealing process so as to form a second barrier layer 32; in some embodiments, the material of the first barrier layer 31 includes boron; the material of the barrier material layer 302 includes oxygen ions or elemental oxygen, and the material of the second barrier layer 32 includes silicon oxide.
Referring to fig. 5 to 7, in some embodiments, forming the second isolation structures 40 therein, which are arranged at intervals along the first direction, includes: forming a trench 43 in the substrate 10, the trench 43 extending toward the first surface 101 of the substrate 10 via the second surface 102 of the substrate 10 at least to a surface of the barrier layer 30 adjacent to the second surface 102 of the substrate 10; forming a second isolation layer 42 covering the surface of the trench 43; the trench 43 is filled with a first isolation layer 41 covering the second isolation layer 42. The material of the first separator 41 includes spin-on glass; the second isolation layer 42 comprises an oxide layer, for example, the material of the second isolation layer 42 comprises silicon oxide. Referring to fig. 6, in some embodiments, an etching process may be used to trim the trench 43 in the second surface 102 of the substrate 10, for example, a dry etching process or a wet etching process may be used, for example, a plasma etching process may be used, where a high-frequency glow discharge reaction is used to activate reactive gases, such as atoms or free radicals, and these reactive gases diffuse to the etched portion to react with the etched material to form volatile products to be removed, thereby improving the manufacture Cheng Sulv; in the case of forming the trench 43 by using an etching process, the first barrier layer 31 may serve as an etching stop layer for the trench 43, avoiding overetching. Referring to fig. 6 to 7, in some embodiments, the first isolation layer 41 and/or the second isolation layer 42 may be formed by a chemical vapor deposition or physical vapor deposition (Physical vapor deposition, PVD) process, and the chemical vapor deposition process may include one or more of Atmospheric Pressure Chemical Vapor Deposition (APCVD), low Pressure Chemical Vapor Deposition (LPCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD), for example, the Low Pressure Chemical Vapor Deposition (LPCVD) has good step coverage, composition and structure controllability, and the Low Pressure Chemical Vapor Deposition (LPCVD) may improve deposition rate and output, and reduce process cost, and the Low pressure chemical vapor deposition does not require a carrier gas, thereby reducing particle contamination.
Referring to fig. 5 and 6, in some embodiments, forming the functional layer 50 in the substrate 10 includes: defining a functional region 501 in the substrate 10, wherein an orthographic projection of the functional region 501 on the first surface 101 of the substrate 10 in the thickness direction of the substrate 10 is located between adjacent first isolation structures 20; after forming the trenches 43, a functional layer 50 is formed based on the remaining functional regions 501, the functional layer 50 being located between the trenches 43 adjacent in the first direction; in some embodiments, functional layer 50 includes photosensitive elements; illustratively, the functional layer 50 includes a P-type semiconductor layer and an N-type semiconductor layer, and for example, the photosensitive element may include a Photodiode (PD).
Referring to fig. 7 and 8, in some embodiments, after forming the functional layer 50 in the substrate 10, forming the dielectric layer 70 on the second surface 102 of the substrate 10, wherein the dielectric layer 70 covers the second isolation structure 40 and the surface of the functional layer 50 near the second surface 102 of the substrate 10, so as to prevent the electrons from overflowing; the dielectric layer 70 can be one layer or a plurality of layers, the insulating effect of the dielectric layer 70 is better, and the electronic overflow can be better prevented; in some embodiments, dielectric layer 70 includes a first dielectric layer 71, a second dielectric layer 72, a third dielectric layer 73, and a fourth dielectric layer 74 that are sequentially stacked on a second surface 102 of substrate 10; in some embodiments, the first dielectric layer 71 includes an oxide layer, the second dielectric layer 72 includes an aluminum oxide layer, the third dielectric layer 73 includes a thallium oxide layer, the fourth dielectric layer 74 includes a metal oxide layer, and the first dielectric layer 71, the second dielectric layer 72, the third dielectric layer 73, and the fourth dielectric layer 74 are all made of a compound material having a high dielectric constant; referring to fig. 5 and 6, in some embodiments, the second surface 102 of the substrate 10 is annealed to form the first dielectric layer 71 while the blocking material layer 302 is annealed, and the first dielectric layer 71 covers the surface of the functional layer 50 near the second surface 102 of the substrate 10, so as to electrically protect the functional layer 50, prevent electrons from overflowing, and improve the reliability of the semiconductor device.
Referring to fig. 7 and 8, in some embodiments, after forming the dielectric layer 70 on the second surface 102 of the substrate 10, forming the photosensitive electrode 60 on a surface of the dielectric layer 70 close to the second surface 102 of the substrate 10, wherein an orthographic projection of the photosensitive electrode 60 along the thickness direction of the substrate 10 is located in the second isolation structure 40 for photosensitive color filtering; in some embodiments, the photosensitive electrode 60 includes a dielectric layer and a conductive layer sequentially stacked along the thickness direction of the substrate 10, and when the dielectric layer 70 has a multi-layered structure and includes at least one metal layer or metal compound layer, the photosensitive electrode 60 and the dielectric layer 70 may together form a composite metal grid (Composite Metal Grid, CMG), so as to further enhance the insulation effect and the electrical protection of the functional layer 50.
Note that the above embodiments are for illustrative purposes only and are not meant to limit the present disclosure.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The foregoing examples merely represent several embodiments of the present disclosure, which are described in more detail and are not to be construed as limiting the scope of the disclosure. It should be noted that variations and modifications can be made by those skilled in the art without departing from the spirit of the disclosure, which are within the scope of the disclosure.
Claims (10)
1. A semiconductor structure, comprising:
the substrate is provided with a first surface and a second surface which are opposite in the thickness direction, first isolation structures which are arranged at intervals in the first direction are formed in the substrate, and the first isolation structures extend towards the second surface through the first surface; the first direction is perpendicular to the thickness direction;
a barrier layer extending along the first direction and covering a surface of the first isolation structure adjacent to the second surface;
the second isolation structures are formed in the substrate and are arranged at intervals along the first direction, and the second isolation structures extend towards the first surface at least to the surface, close to the second surface, of the barrier layer through the second surface;
a functional layer formed within the substrate and located between the second isolation structures adjacent along the first direction; the functional layer comprises a photosensitive element;
the barrier layer comprises a first barrier layer and a second barrier layer which are sequentially laminated along the thickness direction, and the first barrier layer is positioned between the second barrier layer and the functional layer; and
the second isolation structure extends at least to a surface of the first barrier layer adjacent to the second surface.
2. The semiconductor structure of claim 1, wherein the material of the first barrier layer comprises boron.
3. The semiconductor structure of claim 2, wherein an orthographic projection of said functional layer along said thickness direction on said first surface is located between adjacent ones of said first isolation structures.
4. The semiconductor structure of claim 2, further comprising a dielectric layer formed on the second surface and covering the second isolation structure and a surface of the functional layer proximate the second surface.
5. The semiconductor structure of claim 4, wherein the functional layer comprises a photosensitive element;
the semiconductor structure further comprises a photosensitive electrode, wherein the photosensitive electrode is formed on the surface, close to the second surface, of the dielectric layer, and orthographic projection along the thickness direction is located in the second isolation structure.
6. The semiconductor structure of any of claims 2-5, wherein the second isolation structure comprises a first isolation layer and a second isolation layer;
the first isolation layer is positioned on the surface of the barrier layer, which is close to the second surface, and extends along the thickness direction; the second isolation layer surrounds the bottom and the side walls of the first isolation layer.
7. A backside illuminated image sensor comprising the semiconductor structure of any of claims 1-6.
8. A method of fabricating a semiconductor structure, comprising the steps of:
providing a substrate, wherein the substrate is provided with a first surface and a second surface which are opposite in the thickness direction, and first isolation structures which are arranged at intervals in the first direction are formed in the substrate; the first isolation structure extends toward the second surface via the first surface; the first direction is perpendicular to the thickness direction;
forming a barrier layer extending along the first direction, wherein the barrier layer covers the surface of the first isolation structure close to the second surface;
forming second isolation structures in the substrate, wherein the second isolation structures are arranged at intervals along the first direction, and extend towards the first surface through the second surface at least to the surface, close to the second surface, of the barrier layer;
forming a functional layer in the substrate, wherein the functional layer is positioned between the second isolation structures adjacent along the first direction; the functional layer comprises a photosensitive element;
the barrier layer comprises a first barrier layer and a second barrier layer which are sequentially laminated along the thickness direction, and the first barrier layer is positioned between the second barrier layer and the functional layer; the second isolation structure extends at least to a surface of the first barrier layer adjacent to the second surface.
9. The method of manufacturing a semiconductor structure of claim 8, wherein the material of the first barrier layer comprises boron.
10. The method of manufacturing a semiconductor structure according to claim 8, wherein forming second isolation structures in the substrate at intervals along the first direction comprises:
forming a trench in the substrate, the trench extending toward the first surface via the second surface at least to a surface of the barrier layer adjacent to the second surface;
forming a second isolation layer covering the surface of the groove;
and filling the groove to form a first isolation layer covering the second isolation layer.
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