CN116247055B - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers - Google Patents
Semiconductor device with a semiconductor layer having a plurality of semiconductor layers Download PDFInfo
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- CN116247055B CN116247055B CN202310534527.1A CN202310534527A CN116247055B CN 116247055 B CN116247055 B CN 116247055B CN 202310534527 A CN202310534527 A CN 202310534527A CN 116247055 B CN116247055 B CN 116247055B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 239000002184 metal Substances 0.000 claims abstract description 54
- 230000000903 blocking effect Effects 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0711—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors
- H01L27/0716—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with bipolar transistors and diodes, or capacitors, or resistors in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Abstract
The present application provides a semiconductor device including: the metal collector electrode is provided with a first region and a second region positioned at one side of the first region; the P-type collector part and the N-type drain region part are arranged on the metal collector in the same layer, the P-type collector part is positioned in the first region and the second region, and the N-type drain region part is positioned in the second region; the N-type drift part and the super junction N-type drift part are arranged on the P-type collector part and the N-type drain region part in the same layer and are respectively positioned in the first region and the second region; the first P-type protection part is arranged in the N-type drift part; the super junction P-type column part and the second P-type protection part are arranged in the super junction N-type drift part, and the second P-type protection part is positioned in a region of the super junction N-type drift part far away from the metal collector electrode; the first grid structure and the first emission electrode are positioned in the first area; the second grid structure and the second emission electrode are positioned in the second area; the N-type cut-off part is arranged between the first P-type protection part and the second P-type protection part so as to avoid interference in the device.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to a semiconductor device.
Background
A super junction Metal-Oxide-semiconductor field-Effect Transistor (MOSFET) is a multi-sub conductive device, and has the advantages of high switching speed, low switching loss, and good frequency characteristics. But at higher voltages, the increase in current and on-state loss increases significantly, resulting in a superjunction MOSFET device that is not as efficient in driving under heavy load conditions as an insulated Gate bipolar transistor (insulated Gate BipolarTransistor, IGBT).
An insulated Gate bipolar transistor (insulated Gate BipolarTransistor, IGBT) is a bipolar conductive device, and has the advantages of high MOSFET input impedance, low control power and simple driving circuit. However, under light load, the IGBT does not drive as efficiently as the superjunction MOSFET.
At present, in order to obtain the advantages of the super-junction MOSFET chip and the IGBT chip at the same time, the super-junction MOSFET and the IGBT chip are generally packaged in parallel to form a new device structure, but because the super-junction MOSFET chip and the IGBT chip are integrated together, new parasitic capacitance and inductance are introduced, namely the mutual interference occurs, so that the performance of the device is poor.
Disclosure of Invention
In view of this, the present application provides a semiconductor device to solve the problem of interference occurring in the existing device.
The present application provides a semiconductor device including:
a metal collector having a first region and a second region located at one side of the first region;
the P-type current collecting part and the N-type drain region part are arranged on the metal current collector in the same layer, the P-type current collecting part is positioned in the first region and the second region, and the N-type drain region part is positioned in the second region;
the N-type buffer layer is arranged on the P-type current collecting part and the N-type drain region;
the N-type drift part and the super-junction N-type drift part are arranged on the N-type buffer layer in the same layer, the N-type drift part is positioned in the first region, and the super-junction N-type drift part is positioned in the second region;
the first P-type protection part, the first P-type part and the first N-type emission part are arranged in the N-type drift part, and the first P-type protection part is positioned in a region of the N-type drift part, which is far away from the metal collector electrode;
the super junction P-type column part, the second P-type protection part and the second N-type emission part are arranged in the super junction N-type drift part, and the second P-type protection part is positioned in a region of the super junction N-type drift part far away from the metal collector electrode;
a first gate structure and a first emitter electrode located in the first region;
a second gate structure and a second emitter electrode located in the second region; and
the N-type cut-off part is arranged on at least one of the N-type drift part and the super junction N-type drift part and is positioned between the first P-type protection part and the second P-type protection part.
The thickness of the N-type cut-off part is the same as that of the N-type drift part or the super junction N-type drift part.
And one end of the second P-type protection part, which is close to the N-type drift part, is overlapped with one end of the P-type current collection part, which is far away from the N-type drift part.
The distance between one end of the second P-type protection part far away from the N-type drift part and one end of the P-type current collection part far away from the N-type drift part is 0-5 micrometers.
And the sum of the thicknesses of the N-type drift part and the N-type buffer layer is equal to the thickness of the N-type cut-off part.
The N-type cut-off parts are arranged at intervals, and the N-type cut-off parts are overlapped in the direction from the N-type drift part to the metal collector.
The second P-type protection part is located at one side of the super junction P-type column part far away from the metal collector, and located at one side of the second N-type emission part near the N-type drift part, the first P-type protection part is located at one side of the first P-type part and the first N-type emission part near the super junction N-type drift part, and the height of the super junction P-type column part is the same as the height of the P-type blocking part.
The first grid structure is located in the N-type drift portion, the first P-type portion and the first N-type emission portion are both in contact with the first grid structure, and the first emission electrode is arranged on one side, far away from the metal collector, of the first grid structure.
The second grid structure is arranged in the super-junction N-type drift part, the second P-type protection part is arranged on one side, close to the N-type drift part, of the second grid structure, the second N-type emission part is in contact with the second grid structure, and the second emission electrode is arranged on one side, far away from the metal collector, of the second grid structure.
The first grid structure is positioned on one side of the N-type drift part, which is far away from the metal collector electrode, and the first emission electrode covers the first grid structure; the second grid structure is positioned on one side of the super junction N-type drift part far away from the metal collector electrode, and the second emission electrode covers the second grid structure.
The application provides a semiconductor device, with the P type collector portion not only set up in first region, but also set up in the second region for IGBT slot cell district is enough long to the route of N type drain region portion, thereby avoids IGBT switch-on in-process, appears the negative resistance phenomenon. In this application, through setting up N type and cut off the portion in N type drift portion and/or super junction N type drift portion that keep away from metal collector one side, and N type cut off the portion setting in between first P type protection part and the second P type protection part for IGBT and super junction MOSFET are in when blocking state, are located the IGBT of first region and are in N type cut off the portion department, and are located the super junction MOSFET of second region and are in N type cut off the portion department, the electric field is cut off, thereby avoid appearing mutual interference between super junction MOSFET and the IGBT, thereby improve the performance of device.
In this application, through set up N type shutoff portion between super junction MOSFET and IGBT for two chips of super junction MOSFET and IGBT need not to leave certain distance when parallelly connected encapsulation, in order to reduce the area that the super junction MOSFET is in the same place with the IGBT is integrated.
In this application, because set up N type shutoff portion between super junction MOSFET and IGBT for be connected between super junction MOSFET and the IGBT and need not the wiring and connect, avoid the wiring to introduce new parasitic capacitance and inductance, thereby guaranteed the performance of device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic view of a first structure of a semiconductor device provided in the present application;
fig. 2 is a schematic circuit diagram of a semiconductor device provided in the present application;
fig. 3 is a schematic diagram of a voltage path structure of the semiconductor device provided in the present application;
fig. 4 is a schematic view of a second structure of the semiconductor device provided in the present application.
Reference numerals:
10. a semiconductor device; 20. an N-type cut-off part; 100. a metal collector; 110. a first region; 120. a second region; 200. a P-type current collector; 300. an N-type drain region; 400. an N-type buffer layer; 500. an N-type drift portion; 510. a first P-type protection part; 520. a first P-type part; 530. a first P-type ohmic portion; 540. a first N-type emission part; 600. a first gate structure; 610. a first gate electrode; 620. a first gate dielectric layer; 700. a first emitter electrode; 800. a super junction N-type drift part; 810. super junction P-type column part; 820. a second P-type protection part; 830. a second P-type section; 840. a second P-type ohmic portion; 850. a second N-type emission part; 900. a second gate structure; 910. a second gate electrode; 920. a second gate dielectric layer; 1000. and a second emitter electrode. The super junction N-type drift part is a super junction N-type drift part,
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application. The various embodiments described below and their technical features can be combined with each other without conflict.
The application provides a semiconductor device, including metal collector, P type collector, N type drain region portion, N type buffer layer, N type drift portion, super junction N type drift portion, first P type protection portion, first P type portion, first N type emission portion, super junction P type post portion, second P type protection portion, second N type emission portion, first grid structure, first emitter electrode, second grid structure, second emitter electrode and N type stop portion. The metal collector electrode is provided with a first region and a second region positioned at one side of the first region; the P-type collector part and the N-type drain region part are arranged on the metal collector in the same layer, the P-type collector part is positioned in the first region and the second region, and the N-type drain region part is positioned in the second region; the N-type buffer layer is arranged on the P-type current collecting part and the N-type drain region; the N-type drift part and the super junction N-type drift part are arranged on the N-type buffer layer in the same layer, the N-type drift part is positioned in the first region, and the super junction N-type drift part is positioned in the second region; the first P-type protection part, the first P-type part and the first N-type emission part are arranged in the N-type drift part, and the first P-type protection part is positioned in a region of the N-type drift part far away from the metal collector electrode; the super junction P-type column part, the second P-type protection part and the second N-type emission part are arranged in the super junction N-type drift part, and the second P-type protection part is positioned in a region of the super junction N-type drift part far away from the metal collector electrode; the first grid structure and the first emission electrode are positioned in the first area; the second grid structure and the second emission electrode are positioned in the second area; the N-type cut-off part is arranged between the first P-type protection part and the second P-type protection part, wherein the film layer arranged in the first area forms an IGBT, and the film layer arranged in the second area forms a super junction MOSFET.
In the application, the P-type current collecting part is not only arranged in the first area, but also arranged in the second area, so that the path from the cell area of the IGBT groove to the N-type drain area is long enough, and the negative resistance phenomenon is avoided in the IGBT conduction process. In this application, through setting up N type and cut off the portion in N type drift portion and/or super junction N type drift portion that keep away from metal collector one side, and N type cut off the portion setting in between first P type protection part and the second P type protection part for IGBT and super junction MOSFET are in when blocking state, are located the IGBT of first region and are in N type cut off the portion department, and are located the super junction MOSFET of second region and are in N type cut off the portion department, the electric field is cut off, thereby avoid appearing mutual interference between super junction MOSFET and the IGBT, thereby improve the performance of device.
In this application, through set up N type shutoff portion between super junction MOSFET and IGBT for two chips of super junction MOSFET and IGBT need not to leave certain distance when parallelly connected encapsulation, in order to reduce the area that the super junction MOSFET is in the same place with the IGBT is integrated.
In this application, because set up N type shutoff portion between super junction MOSFET and IGBT for be connected between super junction MOSFET and the IGBT and need not the wiring and connect, avoid the wiring to introduce new parasitic capacitance and inductance, thereby guaranteed the performance of device.
Referring to fig. 1 to 3, fig. 1 is a schematic view of a first structure of a semiconductor device provided in the present application; fig. 2 is a schematic circuit diagram of a semiconductor device provided in the present application; fig. 3 is a schematic diagram of a voltage path structure of the semiconductor device provided in the present application.
The application provides a semiconductor device 10, which comprises a metal collector 100, a P-type collector 200, an N-type drain 300, an N-type buffer 400, an N-type drift 500, a super junction N-type drift, a first P-type protection 510, a first P-type 520, a first P-type ohmic 530, a first N-type emitter 540, a first gate structure 600, a first emitter 700, a super junction P-type pillar 810, a second P-type protection 820, a second P-type 830, a second P-type ohmic 840, a second N-type emitter 850, a second gate structure 900, a second emitter 1000, and an N-type stop 20.
Specifically, the metal collector 100 has a first region 110 and a second region 120 located at one side of the first region 110. The P-type collector 200 and the N-type drain 300 are arranged on the metal collector 100 in the same layer, the P-type collector 200 is located in the first region 110 and the second region 120, and the N-type drain 300 is located in the second region 120. The N-type buffer layer 400 is provided on the P-type collector 200 and the N-type drain 300. The N-type drift portion 500 and the super junction N-type drift portion are disposed on the N-type buffer layer 400, and the N-type drift portion 500 is located in the first region 110, and the super junction N-type drift portion is located in the second region 120. The plurality of first P-type protection portions 510 are provided, and the plurality of first P-type protection portions 510 are disposed in the N-type drift portion 500 at intervals and are located in a region of the N-type drift portion 500 away from the metal collector 100. The first P-type portion 520 is disposed in a region of the N-type drift portion 500 away from the metal collector 100, and the first P-type protection portion 510 is disposed at a side away from the second region 120. The first P-type ohmic portion 530 is disposed in a region of the N-type drift portion 500 away from the metal collector 100, and is located at a side of the first P-type portion 520 away from the metal collector 100. The first N-type emitter 540 is disposed in a region of the N-type drift 500 away from the metal collector 100 and on a side of the first P-type portion 520 away from the metal collector 100. The N-type drift part 500 has a trench, the first gate structure 600 is filled in the trench, the first gate includes a first gate electrode 610 and a first gate dielectric layer 620 covering the first gate electrode 610, the trench is disposed between adjacent first P-type parts 520 and between adjacent first N-type emission parts 540, the first gate structure 600 is in contact with the first N-type emission parts 540 and the first P-type parts 520, and in addition, the first gate structure 600 closest to the second region 120 is also in contact with the first P-type protection part 510, and the first gate electrode 610 serves as one terminal of the device. The first emitter electrode 700 is disposed on a side of the N-type drift portion 500 away from the metal collector 100.
Next, the super junction P-type pillar 810, the second P-type protection 820, the second P-type 830, the second P-type ohmic 840, the second N-type emitter 850, and the second gate structure 900 are all disposed in the super junction N-type drift. The super junction P-type pillar portions 810 are provided in plurality, the plurality of super junction P-type pillar portions 810 are arranged at intervals, and one end of the plurality of super junction P-type pillar portions 810, which is close to the metal collector 100, is contacted with the N-type buffer layer 400. The second P-type protection portion 820 is disposed on a side of the super junction P-type pillar portion 810 away from the metal collector 100, and contacts the super junction P-type pillar portion 810. The second gate structure 900 is disposed on a side of the second P-type protection portion 820 away from the first region 110 and is in contact with the second P-type protection portion 820, the second gate structure 900 is disposed in the super junction N-type drift portion through a trench, the second gate structure 900 includes a second gate electrode 910 and a second gate dielectric layer 920 covering the second gate electrode 910, and the second gate electrode 910 serves as one terminal in the device. The second P-type portion 830, the second P-type ohmic portion 840 and the second N-type emitter 850 are disposed on a side of the second P-type protection portion 820 away from the first region 110. The second P-type ohmic portion 840 and the second N-type emitter portion 850 are disposed on a side of the second P-type portion 830 away from the metal collector 100, and the second N-type emitter portion 850 and the second P-type portion 830 are in contact with the second gate dielectric layer 920. The second emitter electrode 1000 is disposed on a side of the super junction N-type drift portion away from the metal collector 100 and is located in the second region 120, where the second emitter electrode 1000 and the first emitter electrode 700 are used together as an emitter and are one of terminals.
Next, the N-type cut-off portion 20 is disposed in at least one of the N-type drift portion 500 and the superjunction N-type drift portion and is located between the first P-type protection portion 510 and the second P-type protection portion 820, wherein the film layer disposed in the first region 110 constitutes an IGBT, and the film layer disposed in the second region 120 constitutes a superjunction MOSFET.
In the application, the device of the application uses four terminals, namely, the metal collector 100 is used as one terminal, the first emitter electrode 700 and the second emitter electrode 1000 are used as emitters together to form one terminal, the first gate electrode 610 is used as one terminal, the second gate electrode 910 is used as one terminal, the first gate electrode 610 controls the switch of the IGBT, and the second gate electrode 910 controls the switch of the super-junction MOSFET, so that the super-junction MOSFET is conducted under the condition of small current, and the efficiency of the device under light load is improved; under the condition of large current, the IGBT is conducted, and the efficiency of the device under heavy load is improved.
When the first gate electrode 610 is subjected to positive voltage, the IGBT-side electron current flows from the first N-type emitter 540 through the channel into the N-type drift 500, the N-type buffer layer 400 of the IGBT, and the N-type buffer layer 400 of the superjunction MOSFET, and finally into the N-type drain 300. When v1=jn (Rs-igbt+rs-mosfet) > VJ1, VJ1 is the on voltage of the PN junction J1 formed by the P-type collector 200 and the N-type buffer layer 400 of the IGBT, the P-type collector 200 of the IGBT injects holes into the N-type region, the IGBT generates a conduction modulation effect, and the IGBT is fully turned on. When V1 is larger than VJ1, the larger the corresponding Jn is, the more easily the Snapback phenomenon occurs. By using the resistor Rs-MOSFET of the N-type buffer layer 400 of the super junction MOSFET terminal region, the V1 can be larger than the VJ1 by using the smaller current Jn on the basis of not additionally increasing the chip size, so that the negative resistance (Snapback) phenomenon can be effectively inhibited.
In this application, the P-type collector 200 is not only disposed in the first region 110, but also disposed in the second region 120, so that the path from the cell region of the IGBT trench to the N-type drain region 300 is long enough, thereby avoiding the negative resistance phenomenon during the turn-on process of the IGBT. In this application, the N-type cut-off portion 20 is disposed on the N-type drift portion 500 and/or the superjunction N-type drift portion far away from the metal collector 100, and the N-type cut-off portion 20 is disposed between the first P-type protection portion 510 and the second P-type protection portion 820, so that when the IGBT and the superjunction MOSFET are in a blocking state, the IGBT located in the first region 110 is at the N-type cut-off portion 20, the electric field is cut off, and the superjunction MOSFET located in the second region 120 is at the N-type cut-off portion 20, the electric field is cut off, thereby avoiding mutual interference between the superjunction MOSFET and the IGBT, and improving the performance of the device.
In this application, through set up N type shutoff portion 20 between super junction MOSFET and IGBT for two chips of super junction MOSFET and IGBT need not to leave certain distance when parallelly connected encapsulation, in order to reduce the area that the super junction MOSFET is in the same place with the IGBT is integrated.
In this application, because set up N type shutoff portion 20 between super junction MOSFET and IGBT for be connected between super junction MOSFET and the IGBT and need not the wiring and connect, avoid the wiring to introduce new parasitic capacitance and inductance, thereby guaranteed the performance of device.
In another embodiment, the thickness of the N-type cut-off portion 20 is the same as that of the N-type drift portion 500 or the superjunction N-type drift portion, i.e. the end portion of the N-type cut-off portion 20 near the metal collector 100 is in contact with the N-type buffer layer 400, i.e. the uninterrupted N-type cut-off portion 20 is disposed in the whole drift portion.
In this application, since the N-type cut-off portion 20 is provided in the entire drift portion, the IGBT and the MOSFET are prevented from interfering with each other when both are in the blocking state in one step.
In another embodiment, an end of the second P-type protection portion 820 close to the N-type drift portion 500 overlaps an end of the P-type collector portion 200 away from the N-type drift portion 500, so as to further generate a negative resistance phenomenon during the IGBT turn-on process.
In another embodiment, the distance between the end of the second P-type protection portion 820 away from the N-type drift portion 500 and the end of the P-type collector portion 200 away from the N-type drift portion 500 is 0-5 micrometers, i.e. the distance between the end of the second P-type protection portion 820 away from the N-type drift portion 500 and the end of the P-type collector portion 200 away from the N-type drift portion 500 in the direction from the first region 110 toward the second region 120 is 0-5 micrometers. Specifically, the distance between the end of the second P-type protection portion 820 away from the N-type drift portion 500 and the end of the P-type collector portion 200 away from the N-type drift portion 500 may be 0 micrometers, 1 micrometer, 2 micrometers, 3 micrometers, 5 micrometers, or the like, that is, the end of the second P-type protection portion 820 away from the N-type drift portion 500 coincides with the end of the P-type collector portion 200 away from the N-type drift portion 500, or the end of the P-type collector portion 200 away from the N-type drift portion 500 is longer than the end of the second P-type protection portion 820 away from the N-type drift portion 500 by 1 micrometer, or the like.
In this application, the distance from the end of the second P-type protection portion 820 away from the N-type drift portion 500 to the end of the P-type current collection portion 200 away from the N-type drift portion 500 is set to 0-5 micrometers in the direction from the first region 110 toward the second region 120, so that a negative resistance phenomenon occurs during the IGBT turn-on process.
In another embodiment, the sum of the thicknesses of the N-type drift portion 500 and the N-type buffer layer 400 is equal to the thickness of the N-type cut-off portion 20, that is, the N-type cut-off portion 20 is not only disposed in the whole drift portion, but also disposed in the N-type buffer layer 400, so as to further avoid the occurrence of mutual interference between the superjunction MOSFET and the IGBT.
In another embodiment, the N-type cut-off parts 20 are plural, each two adjacent N-type cut-off parts 20 are disposed at intervals, and the N-type cut-off parts 20 are overlapped in the direction from the N-type drift part 500 to the metal collector 100, so as to further avoid the mutual interference between the superjunction MOSFET and the IGBT.
The working principle of the semiconductor device 10 provided in the present application is as follows:
when the first gate electrode 610 and the second gate electrode 910 are both at zero potential, the emitter is at zero potential, and the metal collector 100 is applied with a positive voltage, the IGBT and the MOSFET are both in a blocking state, and the left and right depletion lines are separated by the N cut-off portion at the maximum breakdown voltage BVDSS. When the second gate electrode 910 applies a positive voltage, the first gate electrode 610 is at zero potential, the emitter is at zero potential, and the metal collector 100 applies a positive voltage, the superjunction MOSFET turns on. When a positive voltage is applied to the first gate electrode 610, the second gate electrode 910 is at zero potential, the emitter is at zero potential, and the metal collector 100 is positive voltage, the IGBT turns on.
Referring to fig. 4, fig. 4 is a schematic diagram illustrating a second structure of the semiconductor device 10 provided in the present application. It should be noted that the second structure is different from the first structure in that:
the gate structures of the IGBT and MOSFET are planar gate structures. Specifically, the first gate structure 600 is located at a side of the N-type drift portion 500 away from the metal collector 100, and the first emitter electrode 700 covers the first gate structure 600; the second gate structure 900 is located at a side of the super junction N-type drift portion away from the metal collector 100, and the second emitter electrode 1000 covers the second gate structure 900. Other structures are the same as those in fig. 1, and will not be described again here.
The foregoing embodiments are merely examples of the present application, and are not intended to limit the scope of the patent application, so that all equivalent structures or equivalent processes using the descriptions and the drawings of the present application, such as the combination of technical features of the embodiments, or direct or indirect application to other related technical fields, are included in the scope of the patent protection of the present application.
Claims (10)
1. A semiconductor device, comprising:
a metal collector having a first region and a second region located at one side of the first region;
the P-type current collecting part and the N-type drain region part are arranged on the metal current collector in the same layer, the P-type current collecting part is positioned in the first region and the second region, and the N-type drain region part is positioned in the second region;
the N-type buffer layer is arranged on the P-type current collecting part and the N-type drain region;
the N-type drift part and the super-junction N-type drift part are arranged on the N-type buffer layer in the same layer, the N-type drift part is positioned in the first region, and the super-junction N-type drift part is positioned in the second region;
the first P-type protection part, the first P-type part and the first N-type emission part are arranged in the N-type drift part, and the first P-type protection part is positioned in a region of the N-type drift part, which is far away from the metal collector electrode;
the super junction P-type column part, the second P-type protection part and the second N-type emission part are arranged in the super junction N-type drift part, and the second P-type protection part is positioned in a region of the super junction N-type drift part far away from the metal collector electrode;
a first gate structure and a first emitter electrode located in the first region;
a second gate structure and a second emitter electrode located in the second region; and
the N-type cut-off part is arranged on at least one of the N-type drift part and the super junction N-type drift part and is positioned between the first P-type protection part and the second P-type protection part.
2. The semiconductor device according to claim 1, wherein a thickness of the N-type cut-off portion is the same as a thickness of the N-type drift portion or the superjunction N-type drift portion.
3. The semiconductor device according to claim 1, wherein an end of the second P-type protection portion close to the N-type drift portion overlaps with an end of the P-type collector portion remote from the N-type drift portion.
4. The semiconductor device according to claim 1, wherein a distance between an end of the second P-type protection portion remote from the N-type drift portion and an end of the P-type collector portion remote from the N-type drift portion is 0 to 5 μm.
5. The semiconductor device according to claim 1, wherein a sum of thicknesses of the N-type drift portion and the N-type buffer layer is equal to a thickness of the N-type cut portion.
6. The semiconductor device according to claim 1, wherein a plurality of the N-type cut-off portions are provided, each two adjacent N-type cut-off portions are provided at an interval, and the plurality of N-type cut-off portions are provided so as to overlap in a direction from the N-type drift portion toward the metal collector.
7. The semiconductor device of any of claims 1-6, wherein the second P-type protection portion is located on a side of the superjunction P-type pillar portion away from the metal collector and on a side of the second N-type emitter portion closer to the N-type drift portion, the first P-type protection portion is located on a side of the first P-type portion and the first N-type emitter portion closer to the superjunction N-type drift portion, and a height of the second P-type protection portion is the same as a height of the first P-type protection portion.
8. The semiconductor device of claim 7, wherein the first gate structure is located in the N-type drift portion, the first P-type portion and the first N-type emitter portion are both disposed in contact with the first gate structure, and the first emitter electrode is disposed on a side of the first gate structure away from the metal collector.
9. The semiconductor device of claim 7, wherein the second gate structure is disposed in the super junction N-type drift portion, the second P-type protection portion is disposed on a side of the second gate structure adjacent to the N-type drift portion, the second N-type emitter is disposed in contact with the second gate structure, and the second emitter electrode is disposed on a side of the second gate structure remote from the metal collector.
10. The semiconductor device of claim 7, wherein the first gate structure is located on a side of the N-type drift portion away from the metal collector, the first emitter electrode overlying the first gate structure; the second grid structure is positioned on one side of the super junction N-type drift part far away from the metal collector electrode, and the second emission electrode covers the second grid structure.
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| JP3908572B2 (en) * | 2002-03-18 | 2007-04-25 | 株式会社東芝 | Semiconductor element |
| CN102005475B (en) * | 2010-10-15 | 2012-07-25 | 无锡新洁能功率半导体有限公司 | Insulated gate bipolar transistor (IGBT) with improved terminal and manufacturing method thereof |
| JP6177154B2 (en) * | 2013-07-16 | 2017-08-09 | 株式会社東芝 | Semiconductor device |
| CN103489908A (en) * | 2013-09-16 | 2014-01-01 | 电子科技大学 | RC-IGBT capable of eliminating negative resistance effect |
| CN107768429B (en) * | 2017-10-27 | 2020-11-13 | 电子科技大学 | Super junction IGBT device with mixed conduction mode |
| CN109888005B (en) * | 2019-01-22 | 2021-11-09 | 上海华虹宏力半导体制造有限公司 | Reverse-conducting super-junction IGBT device and manufacturing method thereof |
| CN110444590B (en) * | 2019-09-05 | 2021-01-22 | 电子科技大学 | Super junction LIGBT power device |
| US10931276B1 (en) * | 2019-09-27 | 2021-02-23 | Alpha And Omega Semiconductor (Cayman) Ltd. | Combined IGBT and superjunction MOSFET device with tuned switching speed |
| CN112164722A (en) * | 2020-11-04 | 2021-01-01 | 深圳市威兆半导体有限公司 | Shielded gate MOSFET device with uniformly doped channel and processing technology |
| CN113690317A (en) * | 2021-08-19 | 2021-11-23 | 福建晋润半导体技术有限公司 | Planar power MOSFET device with super junction structure and manufacturing method thereof |
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