CN116244482B - Circuit simulation display method and device - Google Patents
Circuit simulation display method and device Download PDFInfo
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- CN116244482B CN116244482B CN202310515852.3A CN202310515852A CN116244482B CN 116244482 B CN116244482 B CN 116244482B CN 202310515852 A CN202310515852 A CN 202310515852A CN 116244482 B CN116244482 B CN 116244482B
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Abstract
The application discloses a circuit simulation display method and device. Wherein the method comprises the following steps: receiving an excitation of a predetermined format; screening out target circuits to be simulated and target excitation to be simulated in excitation; simulating a target circuit based on target excitation to generate a simulation result; and displaying at least the target excitation, the target circuit and the simulation result on the target display interface. The application solves the technical problems of complicated operation, time consumption and low simulation efficiency in the simulation process caused by the fact that the simulation excitation, the simulation result and the simulation circuit are respectively displayed in different display windows in the related technology.
Description
Technical Field
The application relates to the field of digital circuits, in particular to a circuit simulation display method and device.
Background
In the related EDA technology, simulation excitation, simulation results and a simulation circuit are respectively displayed in different display windows, when a user views different data, the user needs to switch back and forth between the display windows, and the operation steps are complicated. For example, when the user finds that the excitation signal of the simulation result needs to be modified, the user needs to manually switch from the window where the simulation result is located to the window where the simulation excitation is located, and after the modification of the excitation signal is completed, compiling again and running the simulation, at this time, the user needs to manually switch to the display window where the simulation result is located to check the newly generated excitation waveform and the result waveform based on the excitation waveform, so that in the related art, the display mode is complex in operation, wastes time and affects the simulation efficiency.
In view of the above problems, no effective solution has been proposed at present.
Disclosure of Invention
The embodiment of the application provides a circuit simulation display method and device, which at least solve the technical problems of complex operation, time consumption and low simulation efficiency in the simulation process caused by the fact that simulation excitation, simulation results and a simulation circuit are displayed in different display windows respectively in the related technology.
According to an aspect of an embodiment of the present application, there is provided a circuit simulation display method, including: receiving an excitation of a predetermined format; screening out target circuits to be simulated and target excitation to be simulated in excitation; simulating a target circuit based on target excitation to generate a simulation result; and displaying at least the target excitation, the target circuit and the simulation result on the target display interface.
Optionally, screening the target circuit to be simulated and target excitation to be simulated in the excitation includes: receiving a first selection instruction of a target object; determining a target area in a circuit diagram selected by a first selection instruction; detecting a circuit belonging to a target area, and determining the circuit belonging to the target area as a target circuit, wherein the target circuit comprises one or more circuits; the method comprises the steps of acquiring excitation belonging to a target area, and determining the excitation belonging to the target area as target excitation, wherein the target excitation comprises one or more excitations.
Optionally, screening the target circuit to be simulated and target excitation to be simulated in the excitation includes: displaying first identification information corresponding to each circuit and second identification information corresponding to each excitation; receiving a second selection instruction of the target object, and determining that first identification information selected by the second selection instruction is first target identification information and second identification information selected by the second selection instruction is second target identification information; determining a circuit corresponding to the first target identification information as a target circuit; and determining the excitation corresponding to the second target identification information as target excitation.
Optionally, screening the target circuit to be simulated and target excitation to be simulated in the excitation includes: receiving a third selection instruction of the target object, and determining excitation selected by the third selection instruction as target excitation; acquiring an input signal and/or an output signal in target excitation; the target circuit is determined from the input signal and/or the output signal in the target stimulus.
Optionally, screening the target circuit to be simulated and target excitation to be simulated in the excitation includes: receiving a fourth selection instruction of the target object, and determining a circuit selected by the fourth selection instruction as a target circuit; determining an input signal and/or an output signal in a target circuit; a target stimulus is determined in the stimulus from the input signal and/or the output signal in the target circuit.
Optionally, simulating the target circuit based on the target excitation to generate a simulation result includes: establishing a target corresponding relation between target excitation and a target circuit; and simulating the target excitation and the target circuit based on the target corresponding relation to generate a simulation result.
Optionally, establishing a target correspondence between target stimulus and target circuit includes: establishing a first corresponding relation between a target circuit and a plurality of target excitations; simulating the target excitation and the target circuit based on the target corresponding relation to generate a simulation result, wherein the simulation result comprises the following steps: and simulating the target circuit by adopting a plurality of target excitations based on the first corresponding relation to obtain a plurality of simulation results of the target circuit under the plurality of target excitations.
Optionally, establishing a target correspondence between target stimulus and target circuit further includes: establishing a second corresponding relation between the target circuits and target excitation; simulating the target excitation and the target circuit based on the target corresponding relation to generate a simulation result, and further comprising: and simulating the target circuits by adopting target excitation based on the second corresponding relation to obtain a plurality of simulation results generated by each target circuit in the target circuits under the target excitation.
Optionally, the method further comprises: under the condition that the simulation result comprises a first input excitation waveform and a second input excitation waveform, establishing an association relation between the first input excitation waveform and the second input excitation waveform; modifying the first input excitation waveform to obtain a modified first input excitation waveform; obtaining updated target excitation according to the association relation and the modified first input excitation waveform; and simulating the target circuit based on the updated target excitation to obtain a new simulation result.
Optionally, the target circuit includes: logic algorithm circuit, target excitation includes: the simulation result comprises: logic operation results, wherein the logic operation excitation signal comprises: an input signal and an output signal; the input signal comprises at least two types of inputs: the first type of input signals have signal identifications and logic values, and the second type of input signals only have signal identifications; the output signal includes: logic values or input signal identification.
According to another aspect of the embodiment of the present application, there is also provided a circuit simulation display apparatus, including: a receiving module for receiving an excitation in a predetermined format; the screening module is used for screening out a target circuit to be simulated and target excitation to be simulated in excitation; the generating module is used for simulating the target circuit based on the target excitation to generate a simulation result; and the display module is used for displaying at least target excitation, target circuit and simulation result on the target display interface.
In the embodiment of the application, the simulation excitation, the simulation circuit and the simulation result are simultaneously displayed on the same display interface, and the excitation in a preset format is received; screening out target circuits to be simulated and target excitation to be simulated in excitation; simulating a target circuit based on target excitation to generate a simulation result; at least displaying target excitation, target circuit and simulation result on the target display interface achieves the purpose of rapidly completing simulation on the same interface, thereby realizing the technical effects of avoiding switching display windows back and forth in the simulation process, simplifying the operation steps of simulation, improving the simulation efficiency, and further solving the technical problems of complex operation, time consumption and low simulation efficiency in the simulation process caused by displaying the simulation excitation, the simulation result and the simulation circuit on different display windows respectively in the related art.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a schematic diagram of a display interface for displaying simulation data by a piece of software according to the related art;
FIG. 2 is a flow chart of an alternative circuit simulation display method according to an embodiment of the application;
FIG. 3 is a schematic diagram of an alternative circuit selection method in an embodiment of the application;
FIG. 4 is a schematic illustration of an alternative stimulus selection method in an embodiment of the application;
FIG. 5 is a schematic diagram of an alternative simulation circuit in an embodiment of the present application;
FIG. 6 is a schematic diagram of an alternative simulation result in an embodiment of the present application;
FIG. 7 is a schematic diagram of an alternative excitation simulation circuit in accordance with an embodiment of the present application;
FIG. 8 is a schematic diagram of an alternative modified waveform in an embodiment of the application;
FIG. 9 is a diagram showing waveform changes after modifying the first signal of the RN according to an embodiment of the present application;
FIG. 10 is a schematic diagram of two simulation circuits being simulated simultaneously;
FIG. 11 is a circuit diagram of an alternative logic operation in an embodiment of the present application;
FIG. 12 is a schematic diagram of an alternative display window of automatically generated logic calculation results in an embodiment of the present application;
FIG. 13 is a schematic diagram showing a circuit obtained by logic operation in the present embodiment;
fig. 14 is a schematic structural diagram of a circuit simulation display device according to an embodiment of the present application.
Detailed Description
In order that those skilled in the art will better understand the present application, a technical solution in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, shall fall within the scope of the present application.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The simulation technique of the digital circuit in the related art generates a simulation result waveform from an HDL code for reading the HDL code (the HDL code includes two pieces of information: design information and stimulus information). For the convenience of analysis, a circuit diagram can be generated according to HDL codes and can be matched with waveforms for use. In the prior art, because the format of the circuit diagram and the storage format of HDL codes are different, the circuit diagram converted according to the HDL codes exists in a second independent window different from the HDL code window for display; editing simulation excitation (simulation conditions and simulation environment), wherein the simulation excitation exists in a code form, so that the simulation excitation and HDL code are displayed by using the same window; a simulated waveform is generated from the circuit diagram and the simulated stimulus, and the simulated waveform is displayed in a third independent waveform window. The results of circuit diagrams, simulation excitation, simulation waveforms and the like in the prior art are respectively in a plurality of independent view windows, and a user needs to call a plurality of windows to view according to requirements.
FIG. 1 is a schematic diagram of simulation data displayed by a piece of software according to the related art, as shown in FIG. 1, wherein the upper left is a code window (HDL code or simulation stimulus is selectively displayed), the upper right is a circuit window, and the lower is a waveform window:
After a user simulates a section of HDL code, circuit diagram data, simulation excitation and simulation waveforms are respectively stored in different files. When the user turns on the HDL code analysis again, the above data needs to be loaded in turn. When the simulation data is large, loading the data is slow. Meanwhile, the problems of inconvenient operation of result display and the like exist.
In the related art, simulation excitation usually exists in a code form, and after the excitation code is written, a running simulation is compiled to generate a simulation waveform. The simulation excitation and the simulation waveform are independent windows, the simulation waveform simultaneously comprises the waveform of the excitation signal and the result waveform, when a user finds that the excitation signal has a problem through the simulation waveform, the simulation waveform needs to be modified in an excitation code, and the simulation is compiled and operated again to generate a new excitation waveform and a new result waveform. When the excitation waveform is found to be problematic, the excitation code needs to be modified, and the simulation needs to be compiled and run for many times, so that the steps are complicated.
If logic calculation is carried out on the circuit diagram converted by HDL codes, the circuit diagram at the moment also exists in a separate window for display (same logic simulation); editing and displaying signal values required by editing logic algorithm in an independent window; the logic operation result is generated by the circuit diagram and the logic operation signal value, and is also displayed in a separate window.
Therefore, the simulation is performed by the simulation technology in the related technology, and if the circuit simulation is to be performed, the circuit diagram window, the simulation excitation window and the simulation waveform window are required to be called and switched to be checked so as to analyze the simulation result, and the simulation process has the technical problems that the calling windows are more, the operation is complicated, the simulation result and the analysis of the result cannot be visually displayed, and the like.
In order to solve the above technical problems, according to an embodiment of the present application, there is provided an embodiment of a circuit simulation display method, it should be noted that the steps illustrated in the flowchart of the drawings may be performed in a computer system such as a set of computer executable instructions, and that although a logic order is illustrated in the flowchart, in some cases, the steps illustrated or described may be performed in an order different from that herein.
Fig. 2 is a circuit simulation display method according to an embodiment of the present application, as shown in fig. 2, the method includes the following steps:
step S202, receiving excitation in a preset format;
step S204, screening out a target circuit to be simulated and target excitation to be simulated in excitation;
step S206, simulating the target circuit based on the target excitation to generate a simulation result;
Step S208, at least the target excitation, the target circuit and the simulation result are displayed on the target display interface.
In the circuit simulation display method, excitation in a preset format can be received first; screening out target circuits to be simulated and target excitation to be simulated in excitation; simulating a target circuit based on target excitation to generate a simulation result; finally, at least the target excitation, the target circuit and the simulation result are displayed on the target display interface, so that the purpose of rapidly completing the simulation on the same interface is achieved, the display window is prevented from being switched back and forth in the simulation process, the operation steps of the simulation are simplified, the technical effect of the simulation efficiency is improved, and the technical problems of complex operation, time consumption and low simulation efficiency in the simulation process caused by the fact that the simulation excitation, the simulation result and the simulation circuit are displayed on different display windows respectively in the related art are solved. It should be noted that the excitation in the predetermined format includes, but is not limited to: excitation of text formats.
In some optional embodiments of the present application, the screening of the target circuit to be simulated and the target excitation to be simulated in the excitation may be implemented by the following steps, specifically, receiving a first selection instruction of the target object; determining a target area in a first selection instruction selection circuit diagram; detecting a circuit belonging to a target area, and determining the circuit belonging to the target area as a target circuit, wherein the target circuit comprises one or more circuits; the method comprises the steps of acquiring excitation belonging to a target area, and determining the excitation belonging to the target area as target excitation, wherein the target excitation comprises one or more excitations.
In some optional embodiments of the present application, in order to facilitate rapid determination of a target circuit and target excitation, the target circuit to be simulated and the target excitation to be simulated in the excitation may be screened out by means of identification information corresponding to each of the selection circuit and the excitation, and specifically, the method is implemented by the following steps: displaying first identification information corresponding to each circuit and second identification information corresponding to each excitation; receiving a second selection instruction of the target object, and determining that first identification information selected by the second selection instruction is first target identification information and second identification information selected by the second selection instruction is second target identification information; determining a circuit corresponding to the first target identification information as a target circuit; and determining the excitation corresponding to the second target identification information as target excitation. For example, there are A, B, C, D first identification information corresponding to each of the 4 circuits, a, b, c, d second identification information corresponding to each of the 4 stimuli, and if the first target identification information selected by the user is a and the second target identification information is a, the target circuit a may be simulated based on the target stimulus a, and in the selection process, there may be a plurality of stimuli or circuits selected.
In some embodiments of the present application, a target circuit to be simulated and target excitation to be simulated in excitation are screened, and the excitation selected by the third selection instruction can be determined as target excitation for receiving the third selection instruction of the target object; acquiring an input signal and/or an output signal in target excitation; the target circuit is determined from the input signal and/or the output signal in the target stimulus.
As another alternative embodiment, screening out a target circuit to be simulated and a target excitation to be simulated in the excitation includes: receiving a fourth selection instruction of the target object, and determining a circuit selected by the fourth selection instruction as a target circuit; determining an input signal and/or an output signal in a target circuit; a target stimulus is determined in the stimulus from the input signal and/or the output signal in the target circuit. The target circuit may be determined either by the input signal and/or the output signal of the target stimulus or by the input signal and/or the output signal of the target circuit.
In some embodiments of the present application, in order to improve simulation efficiency and save simulation time, simulation of one circuit to multiple excitations or simulation of multiple circuits to one excitation may be implemented by establishing a correspondence between excitation and circuits, that is, a simulation result may be generated by simulating a target circuit based on a target excitation, and then simulating a target excitation and a target circuit based on the target correspondence, so as to generate a simulation result.
Optionally, for simulation of multiple excitations by a circuit, establishing a target correspondence between target excitations and target circuits includes: establishing a first corresponding relation between a target circuit and a plurality of target excitations; therefore, the simulation is performed on the target excitation and the target circuit based on the target corresponding relation, so that a simulation result is generated, and the simulation is performed on the target circuit by adopting a plurality of target excitations based on the first corresponding relation, so that a plurality of simulation results generated by the target circuit under the plurality of target excitations are obtained.
Similarly, for simulation of multiple circuits to one excitation, a target corresponding relation between target excitation and target circuits is established, and a second corresponding relation between multiple target circuits and target excitation can be established; therefore, the simulation is performed on the target excitation and the target circuits based on the target corresponding relation to generate a simulation result, and the simulation is performed on the plurality of target circuits based on the second corresponding relation by using the target excitation to obtain a plurality of simulation results generated by each target circuit in the plurality of target circuits under the target excitation.
The target stimulus includes an input signal name, an input signal value, and an output signal name, and by combining the input signal value and the circuit connection relationship, the operation state of the circuit can be calculated, so as to determine the state of the output signal under the specified input condition.
In practical simulation applications, a plurality of excitations may exist at the same time, at this time, after a certain excitation of the plurality of excitations is changed, simulation may be performed again based on the changed excitation according to the association relationship between the plurality of excitations, which may be implemented specifically by the following steps: under the condition that the simulation result comprises a first input excitation waveform and a second input excitation waveform, establishing an association relation between the first input excitation waveform and the second input excitation waveform, modifying the first input excitation waveform to obtain a modified first input excitation waveform, obtaining updated target excitation according to the association relation and the modified first input excitation waveform, and finally simulating the target circuit based on the updated target excitation to obtain a new simulation result.
The simulation results in some embodiments of the present application may be simulation waveforms, or may be logic calculation results.
The circuit simulation display method of the application can be realized by the following steps:
(1) The circuit diagram is opened. Simulation stimulus information is added to the circuit diagram and displayed in a tabular manner (i.e., simulation stimulus in text form). It should be noted that, the simulation excitation information may be a table of simulation excitation signals, and may also be a text with a certain fixed format, for example: HDL code, or other simulation excitation information corresponding to the circuit diagram, in this exemplary embodiment taking a simulation table as an example;
(2) Editing a simulation form, filling excitation required by simulation and signals needing to check waveforms in the form, wherein input signals in excitation are filled in a form of 'signal names and signal values', and the waveforms of output signals needing to be checked are directly filled in the form of 'signal names';
(3) Multiple simulation tables can be added in one circuit diagram;
(4) One circuit is selected as a simulation circuit, and one table is selected as simulation excitation. The simulation circuit can be an entire circuit diagram or a partial circuit diagram. It should be noted that the selected operation may be implemented by operations such as clicking, sliding, etc., for example, selecting a circuit to be simulated and a table to be simulated with a rectangular frame, and then performing simulation; the simulation table can also be directly selected, and the corresponding simulation circuit is automatically determined from the current circuit according to the signal names in the simulation table;
(5) The simulation circuit can support to select a plurality of simulation circuits in the circuit diagram for simulation, each simulation circuit can correspond to a plurality of simulation tables, and each simulation table can correspond to a plurality of simulation circuits; the same excitation is utilized to simulate a plurality of circuits, and the same circuit can be also utilized to simulate the same circuit;
(6) And (5) performing simulation and automatically generating a simulation result. The result has various presentation forms, and the presentation form can be displayed as an independent waveform window, and waveforms in the window can be copied to a circuit diagram for display, and can also be directly displayed in the circuit diagram;
(7) The excitation waveform can be modified in the simulation result, the modification can synchronously update the corresponding simulation table, and the simulation is performed again to obtain a new simulation result.
The target area is selected in the circuit diagram, the corresponding circuit or stimulus can be selected directly in the circuit diagram view by using a selection tool, and the selection of the target circuit or target stimulus can be realized by directly selecting the corresponding circuit name and stimulus name in tools such as a library manager. The target area may be a part of the circuit or the excitation in the circuit diagram, or may be the whole circuit or the excitation.
The library manager in the related software may include identification information (i.e., circuit name) corresponding to each circuit and identification information (i.e., excitation file name) corresponding to each excitation, and the circuit corresponding to the first identification information may be determined by selecting the first identification information, so that a circuit diagram where the circuit is located is taken as a target circuit; and determining the excitation corresponding to the second identification information by selecting the second identification information, so that the excitation is taken as the target excitation.
Illustratively, the left side of fig. 3 shows the circuit identification information and the excitation identification information contained in the library manager, and the counter circuit corresponding to the circuit identification information can be determined by selecting the circuit identification information count_3b, so that the counter circuit is used as the target circuit to be simulated, as shown in the right side of fig. 3; in addition, the target stimulus to be simulated can also be determined by selecting the stimulus identification information tb_count_3b.v in the library manager, as shown in fig. 4.
FIG. 5 is a schematic diagram of an alternative simulation circuit according to an embodiment of the present application, as shown in FIG. 5, in which a simulation table can be edited for the simulation circuit, and then signal values of input signals are set in the table, in which the input signals in FIG. 5 include a clock signal CP, an enable signal CR, a reset signal RN, and output signals requiring waveform checking are added to the table, and in which the output signals in FIG. 5 include COUNT [2:0], as shown in the following table:
in the table, "-" means that the previous value was inverted, and "-" means that the previous value was held.
The simulation table is simulated, so that a simulation result diagram can be automatically generated, and is shown in fig. 6 as a simulation result schematic diagram. In the circuit simulation process, a simulation table and a simulation result block diagram can be sequentially added in a circuit diagram, and fig. 7 is a circuit display diagram finally obtained in the embodiment of the application, as shown in fig. 7, in the circuit display diagram, a simulation excitation, a simulation result and a simulation circuit can be simultaneously displayed in one interface. It should be specifically noted that, in the prior art shown in fig. 1, multiple windows may be stacked and displayed in parallel in one interface, but the circuit diagram, the excitation and the waveform result are still multiple windows in nature, and the target excitation, the target circuit and the simulation result are not displayed in the same window in the implementation of the present application.
It should be noted that the simulation excitation waveform can be modified in two ways:
(1) The simulation excitation table is modified, the simulation excitation table can be edited and modified, and the simulation result can be changed by changing the simulation excitation, as shown in the following table:
the simulation excitation table includes signal names and signal values of the input signals CP, CR, RN and signal names of the output signals COUNT [2:0 ]. When the signal value of the input signal CR changes, the CR signal waveform in the simulation result changes synchronously, and because the CR signal, the CP signal and the RN signal affect the output signal COUNT [2:0] together, after the CR signal value changes, the CP signal, the RN signal and the changed CR signal simulate the simulation circuit again to obtain a new simulation result, and the waveform of COUNT [2:0] also changes along with the change of the simulation result, as shown in a modified waveform schematic diagram in FIG. 8.
(2) Modifying the simulation excitation waveform, wherein the simulation excitation waveform can be edited and modified, and the simulation result can be changed by changing the excitation waveform;
it should be noted that, the content in the waveform block diagram includes an input signal waveform and an output result signal waveform, and for the input signal waveform, the input signal waveform is editable and modifiable, and the edited and modified input signal waveform can be updated to an excitation file or an excitation table, that is, the input signal waveform can be modified according to the user's requirement; in fig. 9, the first signal value of RN is changed from "1" to "0", so that the modified RN signal value can be automatically synchronized to the simulation table, and after re-simulation, the waveform of COUNT [2:0] is found to be modified correspondingly, as shown in fig. 9, which is a schematic diagram of waveform change after the first signal of RN is modified.
In the above embodiment, only one simulation table is added in the circuit diagram, in other alternative implementations, a plurality of simulation tables can be added in one circuit to perform circuit simulation, the method and simulation process for adding tables are the same as those in the above embodiment, fig. 10 is a schematic diagram of simultaneously performing simulation on two simulation circuits, two simulation circuits can be selected in one circuit diagram to perform simulation as shown in fig. 10, wherein the simulation circuit 1 is a counter circuit (left dashed line box in fig. 10), and the simulation circuit 2 is an equivalent comparator circuit (right dashed line box in fig. 10).
It should be noted that, in the related art, the circuit diagram (or the functional module in an HDL code file) in one window needs to be compiled and simulated at the same time, and as long as one circuit/functional module is not compiled, another circuit/functional module cannot be simulated. It is easy to note that the present application can select two circuits to simulate simultaneously, and can select one of the circuits to simulate, even if one of the circuits/functional modules is not compiled or is not compiled, the simulation of the other circuit is not affected.
The inventive method according to the present application includes logic operations in addition to the above-described simulation (i.e., logic simulation). Logic computation is a special logic simulation. Namely, the target circuit can also be a logic operation circuit, the target excitation can also be a logic operation excitation signal, the simulation result can also be a logic operation result, and it should be noted that the logic operation excitation signal includes: an input signal and an output signal. The following describes a logic operation part in the embodiment of the present application:
in other alternative embodiments of the present application, logic operation excitation signals of a predetermined format may also be received; screening logic operation circuits and logic operation excitation signals to be subjected to logic operation; performing logic operation on the logic operation circuit based on the logic operation excitation signal to generate a logic operation result; at least a logic operation circuit, a logic operation excitation signal and a logic operation result are displayed on a target display interface. Wherein the logic operation excitation signal comprises an input signal and an output signal; the input signal comprises at least two types of inputs: the method has signal identification and logic value or only has signal identification; the output signal may be a logic value or an input signal identification.
In some alternative embodiments, the logic operation circuit performs logic operation based on the logic operation excitation signal to generate a logic operation result, specifically, in the case of determining the input signal and the logic value of the input signal, performs logic operation in combination with the input signal and the circuit connection relationship (i.e., the logic relationship), and generates the output signal in the form of the logic value or the input signal identification expression. Specifically, the screening of the logic operation circuit and the logic operation excitation signal to be subjected to logic operation can be realized by the following steps:
receiving a first selection instruction of a target object; determining a target area selected by the first selection instruction; detecting a circuit belonging to the target area, and determining the circuit belonging to the target area as a logic operation circuit; and obtaining the excitation belonging to the target area, and determining the excitation belonging to the target area as a logic algorithm excitation signal.
In some embodiments of the present application, a logic operation circuit may be simulated based on a logic operation excitation signal to obtain a logic operation result of the logic operation circuit, including: establishing a target corresponding relation between a logic operation excitation signal and a logic operation circuit; and carrying out logic operation on the logic operation excitation signal and the logic operation circuit based on the target corresponding relation to obtain a logic operation result.
It should be noted that, establishing the target correspondence between the logic operation circuit and the logic operation excitation signal includes: establishing a first corresponding relation between a logic operation circuit and a plurality of logic operation excitation signals; accordingly, the logic operation circuit and the logic operation excitation signal are logically operated based on the target correspondence relationship to generate a logic operation result, including: and carrying out logic operation on the logic operation circuit by adopting a plurality of logic operation excitation signals based on the first corresponding relation to obtain a plurality of logic operation results generated by the logic operation circuit under the plurality of logic operation excitation signals.
Optionally, establishing a target correspondence between the logic operation circuit and the logic operation excitation signal further includes: establishing a second corresponding relation between the logic operation circuits and the logic operation excitation signals; therefore, the logic operation circuit and the logic operation excitation signal are logically operated based on the target correspondence relationship to generate a logic operation result, and the method further includes: and carrying out logic operation on the plurality of logic operation circuits by adopting the logic operation excitation signals based on the second corresponding relation to obtain a plurality of logic operation results generated by each logic operation circuit in the plurality of logic operation circuits under the logic operation excitation signals.
By way of example, the logic algorithm may be implemented by the following steps, in particular:
(1) The circuit diagram is opened. Logic operation information is added to the circuit diagram and can be displayed in a tabular manner.
(2) Editing a logic operation table, wherein an input signal can adopt a form of signal identification plus logic value to add a logic operation excitation signal to a logic operation circuit, and can also adopt a form of signal identification or default; the output signal of the calculation result (expression) is required to be checked to directly fill in a signal identifier in the table;
(3) Multiple logic tables may be added to a circuit diagram;
(4) One circuit is selected as a logic operation circuit, and one table is selected as a logic operation table. The logic operation circuit can be an entire circuit diagram or a partial circuit diagram;
(5) Supporting the selection of a plurality of logic operation circuits in the circuit diagram for logic operation, wherein each logic operation circuit can correspond to a plurality of logic operation tables, and each logic operation table can correspond to a plurality of logic operation circuits;
(6) And carrying out calculation and automatically generating a logic calculation result. The logic calculation result is directly displayed in a circuit diagram window;
(7) The input signals can be modified in the logic operation result, the corresponding logic operation tables can be synchronously updated by the modification, and the logic operation is performed again to obtain a new logic operation result.
Fig. 11 is an exemplary logic operation circuit diagram, as shown in fig. 11. The logic operation circuit of this embodiment can edit the operation table, as shown in the following table, and adds logic value operation to the input signal A [1:0], when A [1:0] is equal to the corresponding logic value, the logic function of the circuit is as follows:
in addition, in the circuit shown in FIG. 11, there are 4 input signals, namely DATA 0-DATA 3, in addition to A1:0, and in the algorithm table, the simulation calculation of the logic function can be performed without setting the 4 signals or only setting the signal names of the 4 signals. For example, in the operation table shown in the above table, only the logic value of the input signal whose signal identifier is a 1:0 is set, the logic value of the input signal whose signal identifier is DATA0 to DATA3 is not set, and the circuit shown in fig. 11 is logically operated based on the operation table, and the result of the logic operation is shown in fig. 12, and it can be seen that the result of the logic operation performed with only the logic value of the input signal whose signal identifier is a 1:0 is set is a simplified expression for the signal identifier of another input signal DATA0 to DATA3 whose specific logic value is not set.
It will be appreciated that if the logic values of the input signals for the signal flags A1:0 and DATA 0-DATA 3 are set simultaneously, then the resulting logic operation results are the specific logic values.
The logic operation table is operated to automatically generate a logic operation result, and the result can be directly displayed in the current circuit diagram, as shown in fig. 12, which is a schematic diagram of a display window of the logic operation result automatically generated in the embodiment of the present application, and in the logic operation process, the logic operation table and the logic operation result can be sequentially added in the circuit diagram, and fig. 13 is a schematic diagram of a circuit display obtained by logic operation in the embodiment.
It is easy to notice that the embodiment of the application can realize that the simulation excitation, the simulation result and the simulation circuit are displayed in the circuit diagram, and can also realize that the logic operation excitation signal, the logic operation result and the logic operation circuit are displayed in the circuit diagram; the user can directly simulate or logically calculate the appointed circuit in the circuit diagram, and the simulation and the logic calculation processes and results are displayed in the circuit diagram without calling other windows, so that the operation is simple and convenient, and the circuit analysis is facilitated.
Fig. 14 shows a circuit simulation display apparatus according to an embodiment of the present application, as shown in fig. 14, the apparatus includes:
A receiving module 140 for receiving an excitation of a predetermined format;
the screening module 142 is used for screening out a target circuit to be simulated and target excitation to be simulated in excitation;
a generating module 144, configured to simulate the target circuit based on the target excitation to generate a simulation result;
the display module 146 is configured to display at least the target excitation, the target circuit, and the simulation result on the target display interface.
In the circuit simulation display device, a receiving module 140 is used for receiving excitation in a preset format; the screening module 142 is used for screening out a target circuit to be simulated and target excitation to be simulated in excitation; a generating module 144, configured to simulate the target circuit based on the target excitation to generate a simulation result; the display module 146 is configured to display at least the target excitation, the target circuit and the simulation result on the target display interface, thereby achieving the purpose of completing the simulation on the same interface quickly, avoiding switching the display window back and forth in the simulation process, simplifying the operation steps of the simulation, and improving the technical effect of the simulation efficiency, and further solving the technical problems of complicated operation, time consumption and low simulation efficiency in the simulation process caused by displaying the simulation excitation, the simulation result and the simulation circuit on different display windows in the related art.
According to another aspect of the embodiment of the present application, there is further provided a nonvolatile storage medium, where the nonvolatile storage medium includes a stored program, and when the program runs, the device in which the nonvolatile storage medium is controlled to execute any one of the circuit simulation display methods.
Specifically, the storage medium is used for storing program instructions for executing the following functions, and the following functions are realized:
receiving an excitation of a predetermined format; screening out target circuits to be simulated and target excitation to be simulated in excitation; simulating a target circuit based on target excitation to generate a simulation result; and displaying at least the target excitation, the target circuit and the simulation result on the target display interface.
According to another aspect of the embodiment of the present application, there is further provided a processor, configured to execute a program, where any one of the circuit simulation display methods is executed when the program is executed.
Specifically, the above processor is configured to call program instructions in the memory, and implement the following functions:
receiving an excitation of a predetermined format; screening out target circuits to be simulated and target excitation to be simulated in excitation; simulating a target circuit based on target excitation to generate a simulation result; and displaying at least the target excitation, the target circuit and the simulation result on the target display interface.
The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.
In the foregoing embodiments of the present application, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.
In the several embodiments provided in the present application, it should be understood that the disclosed technology may be implemented in other manners. The above-described embodiments of the apparatus are merely exemplary, and the division of the units, for example, may be a logic function division, and may be implemented in another manner, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interfaces, units or modules, or may be in electrical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application, which are intended to be comprehended within the scope of the present application.
Claims (10)
1. The circuit simulation display method is characterized by comprising the following steps of:
receiving an excitation in a predetermined format in a circuit diagram, the predetermined format including at least a text format;
screening out a target circuit to be simulated and target excitation to be simulated in the excitation;
in the circuit diagram, simultaneously selecting the target circuit and the target excitation, and simulating the target circuit based on the selected target excitation to generate a simulation result, wherein the target circuit is a local circuit in the circuit diagram;
rapidly completing simulation on a target display interface, and displaying at least the target excitation, the target circuit and the simulation result on the target display interface, wherein the target display interface is an interface where a circuit diagram is located;
under the condition that the simulation result comprises a first input excitation waveform and a second input excitation waveform, establishing an association relation between the first input excitation waveform and the second input excitation waveform; modifying the first input excitation waveform to obtain a modified first input excitation waveform; obtaining updated target excitation according to the association relation and the modified first input excitation waveform; and simulating the target circuit based on the updated target excitation to obtain a new simulation result.
2. The method of claim 1, wherein screening out target circuits to be simulated and target stimuli to be simulated from the stimuli comprises:
receiving a first selection instruction of a target object;
determining a target area in the circuit diagram selected by the first selection instruction;
detecting a circuit belonging to the target area, and determining the circuit belonging to the target area as the target circuit, wherein the target circuit comprises one or more circuits;
acquiring the excitation belonging to the target area, and determining the excitation belonging to the target area as the target excitation, wherein the target excitation comprises one or more excitations.
3. The method of claim 2, wherein screening out the target circuit to be simulated and the target stimulus to be simulated from the stimulus comprises:
displaying first identification information corresponding to each circuit and second identification information corresponding to each excitation;
receiving a second selection instruction of a target object, and determining that first identification information selected by the second selection instruction is first target identification information and second identification information selected by the second selection instruction is second target identification information;
Determining a circuit corresponding to the first target identification information as the target circuit;
and determining the excitation corresponding to the second target identification information as the target excitation.
4. The method of claim 1, wherein screening out target circuits to be simulated and target stimuli to be simulated from the stimuli comprises:
receiving a third selection instruction of a target object, and determining excitation selected by the third selection instruction as the target excitation;
acquiring an input signal and/or an output signal in the target excitation;
the target circuit is determined from the input signal and/or the output signal in the target stimulus.
5. The method of claim 1, wherein screening out target circuits to be simulated and target stimuli to be simulated from the stimuli comprises:
receiving a fourth selection instruction of a target object, and determining a circuit selected by the fourth selection instruction as the target circuit;
determining an input signal and/or an output signal in the target circuit;
a target stimulus is determined in the stimulus from an input signal and/or the output signal in the target circuit.
6. The method of claim 1, wherein simulating the target circuit based on the target stimulus generates simulation results, comprising:
Establishing a target corresponding relation between the target excitation and the target circuit;
and simulating the target excitation and the target circuit based on the target corresponding relation, and generating the simulation result.
7. The method of claim 6, wherein the step of providing the first layer comprises,
establishing a target correspondence between the target stimulus and the target circuit, including: establishing a first corresponding relation between the target circuit and a plurality of target excitation;
simulating the target excitation and the target circuit based on the target correspondence, and generating the simulation result, including: and simulating the target circuit by adopting the target excitations based on the first corresponding relation to obtain a plurality of simulation results generated by the target circuit under the target excitations.
8. The method of claim 6, wherein the step of providing the first layer comprises,
establishing a target correspondence between the target stimulus and the target circuit, further comprising: establishing a plurality of second corresponding relations between the target circuits and the target excitation;
simulating the target excitation and the target circuit based on the target correspondence, generating the simulation result, and further comprising: and simulating the target circuits by adopting the target excitation based on the second corresponding relation to obtain a plurality of simulation results generated by each target circuit in the target circuits under the target excitation.
9. The method of any one of claims 1 to 8, wherein the target circuit comprises: logic circuitry, the target stimulus comprising: logic calculating an excitation signal, the simulation result comprising: a logic operation result, wherein the logic operation excitation signal comprises: an input signal and an output signal; the input signal comprises at least two types of inputs: the first type of input signal has a signal identification and a logical value, the second type of input signal has only a signal identification, and the output signal comprises: logic values or input signal identification.
10. A circuit emulation display device, comprising:
a receiving module for receiving an excitation in a predetermined format in a circuit diagram, the predetermined format including at least a text format;
the screening module is used for screening out a target circuit to be simulated and target excitation to be simulated in the excitation;
the generating module is used for selecting the target circuit and the target excitation in the circuit diagram, and simulating the target circuit based on the selected target excitation to generate a simulation result, wherein the target circuit is a local circuit in the circuit diagram;
The display module is used for completing quick simulation on a target display interface and displaying at least the target excitation, the target circuit and the simulation result on the target display interface, wherein the target display interface is an interface where a circuit diagram is located;
further comprises: under the condition that the simulation result comprises a first input excitation waveform and a second input excitation waveform, establishing an association relation between the first input excitation waveform and the second input excitation waveform; modifying the first input excitation waveform to obtain a modified first input excitation waveform; obtaining updated target excitation according to the association relation and the modified first input excitation waveform; and simulating the target circuit based on the updated target excitation to obtain a new simulation result.
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5425036A (en) * | 1992-09-18 | 1995-06-13 | Quickturn Design Systems, Inc. | Method and apparatus for debugging reconfigurable emulation systems |
| CN115640768A (en) * | 2022-09-26 | 2023-01-24 | 华为技术有限公司 | Method, apparatus, device, medium and program product for emulating a circuit |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5425036A (en) * | 1992-09-18 | 1995-06-13 | Quickturn Design Systems, Inc. | Method and apparatus for debugging reconfigurable emulation systems |
| CN115640768A (en) * | 2022-09-26 | 2023-01-24 | 华为技术有限公司 | Method, apparatus, device, medium and program product for emulating a circuit |
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