CN117313599B - Circuit simulation method, device, electronic equipment and medium - Google Patents
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Abstract
The application provides a circuit simulation method, a circuit simulation device, electronic equipment and a medium. The method comprises the following steps: according to a database of a design circuit, GDS files of the circuit to be simulated and adjacent circuits thereof are obtained, wherein the GDS files comprise circuit parameters of the circuit to be simulated and the adjacent circuits thereof, and the circuit to be simulated is a local circuit of the design circuit; inquiring a parasitic parameter inquiry table through a parasitic parameter extraction tool, obtaining parasitic parameters of each device in the GDS file, and converting the GDS file into a SPICE netlist; and taking the starting point and the end point of the circuit to be simulated as ports of the circuit to be simulated, applying excitation to the ports of the circuit to be simulated according to the SPICE netlist, and executing circuit simulation. The method can improve the simulation efficiency of the key circuit.
Description
Technical Field
The present application relates to integrated circuit technology, and in particular, to a circuit simulation method, apparatus, electronic device, and medium.
Background
In the design of large-scale digital integrated circuits, in order to improve the circuit performance, a semi-customized design means is often adopted for the key performance part of the circuit, and because the traditional digital time sequence analysis tool often cannot meet the requirement of precision, related parameters are generally obtained by adopting a circuit simulation mode for part of key circuits in the whole design circuit, and the parameters are reversely marked back to the digital time sequence analysis tool for time sequence analysis of the large-scale circuit.
In the prior art, in order to ensure the simulation precision, a GDS file of an overall design circuit is required to be generated aiming at the simulation of part of key circuits, parasitic parameters are extracted aiming at the GDS file, a complete SPICE netlist is generated, and then a circuit simulation tool is imported to simulate the overall design circuit. The simulation efficiency is low because the objects facing the circuit simulation are too large.
Disclosure of Invention
The application provides a circuit simulation method, a circuit simulation device, electronic equipment and a medium, which are used for improving the simulation efficiency of a key circuit.
In one aspect, the present application provides a circuit simulation method, including:
According to a database of a design circuit, GDS files of the circuit to be simulated and adjacent circuits thereof are obtained, wherein the GDS files comprise circuit parameters of the circuit to be simulated and the adjacent circuits thereof, and the circuit to be simulated is a local circuit of the design circuit;
Inquiring a parasitic parameter inquiry table through a parasitic parameter extraction tool, obtaining parasitic parameters of each device in the GDS file, and converting the GDS file into a SPICE netlist;
and taking the starting point and the end point of the circuit to be simulated as ports of the circuit to be simulated, applying excitation to the ports of the circuit to be simulated according to the SPICE netlist, and executing circuit simulation.
Optionally, the obtaining, according to a design circuit database, the GDS file of the circuit to be simulated and the physically adjacent circuit thereof includes:
establishing a local database according to the design circuit database, wherein the local database comprises logic connection information, device physical information, connection physical information and physical shape information of adjacent power ground wires of the circuit to be simulated and the adjacent circuit;
And acquiring GDS library files of all devices in the circuit to be simulated and the adjacent circuit according to the local database, and merging the GDS library files of all the devices into the GDS file.
Optionally, building a local database according to the design circuit database includes:
acquiring logic connection information of the circuit to be simulated based on the starting point information and the end point information of the circuit to be simulated according to the design circuit database, and generating a first file containing the logic connection information of the circuit to be simulated;
Based on the logic connection information of the circuit to be simulated, acquiring physical position information of each device in the circuit to be simulated, and generating a second file containing the physical position information of each device in the circuit to be simulated;
determining adjacent devices in a preset range of each device in the circuit to be simulated based on the physical position information of each device in the circuit to be simulated, acquiring the logic connection information and the physical position information of the adjacent devices, and generating a third file containing the logic connection information of the adjacent devices and a fourth file containing the physical position information of the adjacent devices;
based on the physical position information of each device in the circuit to be simulated, acquiring the physical shape information and the metal layer information of the connecting wire of each device in the circuit to be simulated, and generating a fifth file containing the physical shape information and the metal layer information of the connecting wire of each device in the circuit to be simulated;
determining adjacent connecting lines and power ground wires of the same metal layer in a preset range of connecting lines of all devices in the circuit to be simulated based on the physical shape information and the metal layer information of the connecting lines of all devices in the circuit to be simulated, acquiring the physical shape information of the adjacent connecting lines and the power ground wires, and generating a sixth file containing the physical shape information of the adjacent connecting lines and a seventh file containing the physical shape information of the power ground wires;
and establishing the local database according to the first file, the second file, the third file, the fourth file, the fifth file, the sixth file and the seventh file.
Optionally, the first file and the third file are Verilog files, and the second file, the fourth file, the fifth file, the sixth file and the seventh file are def files.
Optionally, the creating the local database according to the first file, the second file, the third file, the fourth file, the fifth file, the sixth file, and the seventh file includes:
Merging the first file and the third file into an eighth file containing logic connection information of the circuit to be simulated and the adjacent circuit; merging the second file and the fourth file into a ninth file containing device physical position information of the circuit to be simulated and the adjacent circuit; combining the fifth file, the sixth file and the seventh file into a tenth file containing the connection physical shape information of the circuit to be simulated and the adjacent circuit and the physical shape information of the adjacent power ground wire;
and establishing the local database according to the eighth file, the ninth file and the tenth file.
Optionally, the step of using the starting point and the end point of the circuit to be simulated as ports, applying excitation to the circuit to be simulated according to the SPICE netlist, and executing circuit simulation includes:
Generating an excitation file and a measurement file for the circuit to be simulated according to the port information of the circuit to be simulated;
Reading the excitation file, the measurement file and the SPICE netlist in a circuit simulation tool, and executing circuit simulation to obtain an output simulation result.
In another aspect, the present application provides a circuit simulation apparatus, including:
The system comprises an acquisition module, a calculation module and a calculation module, wherein the acquisition module is used for acquiring GDS files of a circuit to be simulated and adjacent circuits thereof according to a database of the design circuit, the GDS files comprise circuit parameters of the circuit to be simulated and the adjacent circuits thereof, and the circuit to be simulated is a local circuit of the design circuit;
The extraction module is used for inquiring the parasitic parameter lookup table through a parasitic parameter extraction tool, obtaining the parasitic parameters of each device in the GDS file and converting the GDS file into a SPICE netlist;
And the simulation module is used for taking the starting point and the end point of the circuit to be simulated as the ports of the circuit to be simulated, applying excitation to the ports of the circuit to be simulated according to the SPICE netlist, and executing circuit simulation.
Optionally, the acquiring module is specifically configured to:
establishing a local database according to the design circuit database, wherein the local database comprises logic connection information, device physical information, connection physical information and physical shape information of adjacent power ground wires of the circuit to be simulated and the adjacent circuit;
And acquiring GDS library files of all devices in the circuit to be simulated and the adjacent circuit according to the local database, and merging the GDS library files of all the devices into the GDS file.
Optionally, the acquiring module is further specifically configured to:
acquiring logic connection information of the circuit to be simulated based on the starting point information and the end point information of the circuit to be simulated according to the design circuit database, and generating a first file containing the logic connection information of the circuit to be simulated;
Based on the logic connection information of the circuit to be simulated, acquiring physical position information of each device in the circuit to be simulated, and generating a second file containing the physical position information of each device in the circuit to be simulated;
determining adjacent devices in a preset range of each device in the circuit to be simulated based on the physical position information of each device in the circuit to be simulated, acquiring the logic connection information and the physical position information of the adjacent devices, and generating a third file containing the logic connection information of the adjacent devices and a fourth file containing the physical position information of the adjacent devices;
based on the physical position information of each device in the circuit to be simulated, acquiring the physical shape information and the metal layer information of the connecting wire of each device in the circuit to be simulated, and generating a fifth file containing the physical shape information and the metal layer information of the connecting wire of each device in the circuit to be simulated;
determining adjacent connecting lines and power ground wires of the same metal layer in a preset range of connecting lines of all devices in the circuit to be simulated based on the physical shape information and the metal layer information of the connecting lines of all devices in the circuit to be simulated, acquiring the physical shape information of the adjacent connecting lines and the power ground wires, and generating a sixth file containing the physical shape information of the adjacent connecting lines and a seventh file containing the physical shape information of the power ground wires;
and establishing the local database according to the first file, the second file, the third file, the fourth file, the fifth file, the sixth file and the seventh file.
Optionally, the first file and the third file are Verilog files, and the second file, the fourth file, the fifth file, the sixth file and the seventh file are def files.
Optionally, the acquiring module is further specifically configured to:
Merging the first file and the third file into an eighth file containing logic connection information of the circuit to be simulated and the adjacent circuit; merging the second file and the fourth file into a ninth file containing device physical position information of the circuit to be simulated and the adjacent circuit; combining the fifth file, the sixth file and the seventh file into a tenth file containing the connection physical shape information of the circuit to be simulated and the adjacent circuit and the physical shape information of the adjacent power ground wire;
and establishing the local database according to the eighth file, the ninth file and the tenth file.
Optionally, the simulation module is specifically configured to:
Generating an excitation file and a measurement file for the circuit to be simulated according to the port information of the circuit to be simulated;
Reading the excitation file, the measurement file and the SPICE netlist in a circuit simulation tool, and executing circuit simulation to obtain an output simulation result.
In yet another aspect, the present application provides an electronic device, comprising: a processor, and a memory communicatively coupled to the processor; the memory stores computer-executable instructions; the processor executes computer-executable instructions stored in the memory to implement the method as described above.
In yet another aspect, the application provides a computer-readable storage medium having stored therein computer-executable instructions for performing the method as described above when executed by a processor.
According to the circuit simulation method, the device, the electronic equipment and the medium, GDS files of the local key circuit and adjacent circuits are obtained according to the database of the overall design circuit, parasitic parameters are extracted for the GDS files of the local key circuit and the adjacent circuits, a SPICE netlist is generated, the SPICE netlist is imported into a circuit simulation tool, excitation is applied by taking the starting point and the end point of the local key circuit as ports, circuit simulation is executed, the influence of the adjacent devices on the devices in the circuit to be simulated can be considered by generating the GDS files of the local key circuit and the adjacent circuits, the extraction precision of the parasitic parameters is ensured, meanwhile, simulation of non-key circuits is avoided, the simulation time is shortened, and the simulation efficiency of the key circuits is effectively improved; and taking the starting point and the end point of the local key circuit as ports, the simulation excitation can be simply and conveniently applied to the key circuit, and the simulation of the key circuit can be accurately controlled.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
Fig. 1 is a schematic flow chart of a circuit simulation method according to a first embodiment of the present application;
fig. 2 is a schematic flow chart of another circuit simulation method according to the first embodiment of the present application;
FIG. 3 is a schematic flow chart of a first embodiment of the present application for obtaining a local database;
Fig. 4 is a schematic structural diagram of a circuit simulation device according to a second embodiment of the present application;
fig. 5 is a schematic structural diagram of a circuit simulation electronic device according to a third embodiment of the present application.
Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.
Detailed Description
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The modules in the present application refer to functional modules or logic modules. It may be in the form of software, the functions of which are implemented by the execution of program code by a processor; or may be in hardware. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.
In the design of large-scale digital integrated circuits, in order to improve the circuit performance, a semi-customized design means is often adopted for the key performance part of the circuit, and because the traditional digital time sequence analysis tool often cannot meet the requirement of precision, related parameters are generally obtained by adopting a circuit simulation mode for part of key circuits in the whole design circuit, and the parameters are reversely marked back to the digital time sequence analysis tool for time sequence analysis of the large-scale circuit.
In the prior art, simulation of a part of key circuits is usually performed by generating a GDS file for designing a circuit design, extracting parasitic parameters from the GDS file, generating a complete SPICE netlist, and then importing a circuit simulation tool to perform circuit simulation. Although a certain simulation accuracy can be ensured, the object faced by the circuit simulation is too large, so that the simulation efficiency is low.
The technical content provided by the application aims to solve the technical problems of the related technology.
According to the embodiment of the application, the GDS files of the local key circuit and the adjacent circuits are obtained according to the database of the overall design circuit, parasitic parameters are extracted for the GDS files of the local key circuit and the adjacent circuits thereof, a SPICE netlist is generated, the SPICE netlist is imported into a circuit simulation tool, excitation is applied by taking the starting point and the end point of the local key circuit as ports, circuit simulation is executed, the influence of the adjacent devices on the devices in the circuit to be simulated can be considered by generating the GDS files of the local key circuit and the adjacent circuits thereof, the extraction precision of the parasitic parameters is ensured, meanwhile, simulation on non-key circuits is avoided, the simulation time is shortened, and the simulation efficiency of the key circuit is effectively improved; and taking the starting point and the end point of the local key circuit as ports, the simulation excitation can be simply and conveniently applied to the key circuit, and the simulation of the key circuit can be accurately controlled.
The technical scheme of the application is illustrated in the following specific embodiments. The following embodiments may be combined with each other, and the same or similar concepts or processes may not be described in detail in some embodiments.
Example 1
Fig. 1 is a flow chart of a circuit simulation method according to an embodiment of the application. As shown in fig. 1, the circuit simulation method provided in this embodiment may include:
s101, acquiring GDS files of a circuit to be simulated and adjacent circuits thereof according to a database of a design circuit, wherein the GDS files comprise circuit parameters of the circuit to be simulated and the adjacent circuits thereof, and the circuit to be simulated is a local circuit of the design circuit;
S102, inquiring a parasitic parameter lookup table through a parasitic parameter extraction tool, obtaining parasitic parameters of each device in the GDS file, and converting the GDS file into a SPICE netlist;
S103, taking the starting point and the end point of the circuit to be simulated as ports of the circuit to be simulated, applying excitation to the ports of the circuit to be simulated according to the SPICE netlist, and executing circuit simulation.
In practical application, the execution body of the embodiment may be a circuit simulation device, which may be implemented by a computer program, for example, application software, etc.; or may be embodied as a medium storing a related computer program, e.g., a usb disk, a cloud disk, etc.; or may also be implemented by physical means, e.g. chips, servers, etc., integrated or installed with the relevant computer program.
GDS, commonly referred to as Geometry Summary Data, is an input file in semiconductor process simulation software that contains geometric data about the chip structure, shape and hierarchy. After the GSD file is generated, the GSD file can be converted to other formats, such as SPICE netlists, as needed for further simulation and analysis. And taking part of key circuits in the overall design circuit as the circuit to be simulated, and generating a GDS file containing the circuit to be simulated and adjacent circuit parameters thereof based on a database of the design circuit.
Parasitic extraction is the calculation of parasitic effects in the design devices and required wiring interconnections of electronic circuits, including parasitic capacitance, parasitic resistance, and parasitic inductance. The parasitic parameter extraction method in practical application can be various, and the parasitic parameter can be calculated by using a lookup table through a parasitic parameter extraction tool. When converting the GDS file into the SPICE netlist, the parasitic parameters are synthesized into the SPICE netlist.
Compared with the traditional key circuit simulation technology, the simulation of the whole design circuit is needed, the simulation time is long, and because the circuit to be simulated is possibly positioned at the internal position of the whole circuit, the excitation is difficult to apply on the external port. In the embodiment, the SPICE netlist of the circuit to be simulated and the adjacent circuits is input into the circuit simulation tool, and the circuit simulation is carried out only on the circuit to be simulated and the adjacent circuits, so that the simulation time can be effectively shortened, and the simulation efficiency is improved; and the starting point and the end point of the circuit to be simulated can be used as ports, excitation is conveniently applied to the ports of the circuit to be simulated, and the response of the circuit to be simulated is observed and analyzed to obtain the relevant parameters of the circuit to be simulated. And reversely marking the related parameters of the circuit to be simulated to a digital time sequence analysis tool for time sequence analysis of the whole design circuit, so that the accuracy and the efficiency of the time sequence analysis can be improved.
In the example, according to the database of the overall design circuit, the GDS files of the local key circuit and the adjacent circuits are obtained, parasitic parameters are extracted for the GDS files of the local key circuit and the adjacent circuits thereof, a SPICE netlist is generated, the SPICE netlist is imported into a circuit simulation tool, excitation is applied by taking the starting point and the end point of the local key circuit as ports, circuit simulation is executed, the influence of the adjacent devices on the devices in the circuit to be simulated can be considered by generating the GDS files of the local key circuit and the adjacent circuits thereof, the extraction precision of the parasitic parameters is ensured, meanwhile, simulation of non-key circuits is avoided, the simulation time is shortened, and the simulation efficiency of the key circuit is effectively improved; and taking the starting point and the end point of the local key circuit as ports, the simulation excitation can be simply and conveniently applied to the key circuit, and the simulation of the key circuit can be accurately controlled.
The method for generating the GDS file of the circuit to be simulated and the adjacent circuit thereof may be various, in one example, the step of obtaining the GDS file of the circuit to be simulated and the physically adjacent circuit thereof according to the design circuit database includes:
establishing a local database according to the design circuit database, wherein the local database comprises logic connection information, device physical information, connection physical information and physical shape information of adjacent power ground wires of the circuit to be simulated and the adjacent circuit;
And acquiring GDS library files of all devices in the circuit to be simulated and the adjacent circuit according to the local database, and merging the GDS library files of all the devices into the GDS file.
FIG. 2 is a schematic flow chart of another circuit simulation method according to an embodiment of the present application, as shown in FIG. 2, a local database only including the information of the circuit to be simulated and the adjacent circuit is reconstructed according to the overall design circuit database, and the logic connection information, the device physical information, the connection physical information and the physical shape information of the adjacent power ground wire of the circuit to be simulated and the adjacent circuit in the local database are reconstructed; based on the local database, according to the data information of each device in the circuit to be simulated and the adjacent circuit, acquiring GDS library files corresponding to each device, and merging all the acquired GDS library files into a GDS file. After the GDS files of the circuit to be simulated and the adjacent circuits are obtained, parasitic parameters can be extracted based on the parameter extraction flow according to the parameter extraction library file, namely the lookup table, a SPICE netlist is generated, circuit simulation is carried out by combining the starting point information and the end point information of the circuit to be simulated, and the simulation result is observed and analyzed.
In this example, firstly, a local database containing information of a circuit to be simulated and adjacent circuits is reconstructed according to a design database of an overall circuit, GDS library files of each device in the circuit to be simulated and the adjacent circuits are obtained based on the local database, and GDS files of the circuit to be simulated and the adjacent circuits are generated in a merging mode.
In order to simulate a local circuit, data information of the circuit to be simulated and adjacent circuits thereof needs to be extracted from an integral design circuit database, wherein the specific modes for acquiring the information of the circuit to be simulated and the adjacent circuits thereof can be various. In one example, building a local database from the design circuit database includes:
acquiring logic connection information of the circuit to be simulated based on the starting point information and the end point information of the circuit to be simulated according to the design circuit database, and generating a first file containing the logic connection information of the circuit to be simulated;
Based on the logic connection information of the circuit to be simulated, acquiring physical position information of each device in the circuit to be simulated, and generating a second file containing the physical position information of each device in the circuit to be simulated;
determining adjacent devices in a preset range of each device in the circuit to be simulated based on the physical position information of each device in the circuit to be simulated, acquiring the logic connection information and the physical position information of the adjacent devices, and generating a third file containing the logic connection information of the adjacent devices and a fourth file containing the physical position information of the adjacent devices;
based on the physical position information of each device in the circuit to be simulated, acquiring the physical shape information and the metal layer information of the connecting wire of each device in the circuit to be simulated, and generating a fifth file containing the physical shape information and the metal layer information of the connecting wire of each device in the circuit to be simulated;
determining adjacent connecting lines and power ground wires of the same metal layer in a preset range of connecting lines of all devices in the circuit to be simulated based on the physical shape information and the metal layer information of the connecting lines of all devices in the circuit to be simulated, acquiring the physical shape information of the adjacent connecting lines and the power ground wires, and generating a sixth file containing the physical shape information of the adjacent connecting lines and a seventh file containing the physical shape information of the power ground wires;
and establishing the local database according to the first file, the second file, the third file, the fourth file, the fifth file, the sixth file and the seventh file.
Fig. 3 is a schematic flow chart of acquiring a local database according to an embodiment of the present application, as shown in fig. 3, based on a design circuit database, a logic topology structure of a circuit to be simulated is tracked according to start point information and end point information of the circuit to be simulated, where the logic topology structure includes connection information, and in practical application, the logic topology structure of the circuit to be simulated can be tracked through a back-end tool command. And obtaining logic connection information of the circuit to be simulated, generating a first file in a Verilog form, and taking the starting point and the end point of the circuit to be simulated as ports of the circuit to be simulated in the first file.
According to the logic connection information of the circuit to be simulated, the physical position of each device in the circuit to be simulated can be grasped by utilizing a back-end tool, so that the physical position information of each device in the circuit to be simulated is obtained, and a second file is generated in the def form.
Starting from the physical position of each device in the circuit to be simulated, respectively extending a preset distance, searching adjacent devices overlapped with the area in a preset range, acquiring logic connection information of the adjacent devices, and generating a third file in a Verilog form; and acquiring the physical position information of the adjacent devices, and generating a fourth file in the def form. Where the predetermined range may be selected based on the needs of the actual production and is not limited thereto, in one example, other neighboring devices that coincide with this area may be searched for based on the physical locations 5um occupied by all devices on the critical circuit.
And grabbing the physical shape and the metal layer information of the connecting lines of all the devices in the circuit to be simulated according to the physical positions of all the devices in the circuit to be simulated, and generating a fifth file in the def form. Starting from the connection line of the circuit device to be simulated, searching for adjacent connection lines with the metal layer and power ground lines within a preset range, wherein the preset range is as described above; acquiring physical shape information of adjacent connecting lines, and generating a sixth file in def form; and acquiring physical shape information of the power ground wire, and generating a seventh file in the form of def.
In practical applications, the first file, the second file, the third file, the fourth file, the fifth file, the sixth file, and the seventh file may have various forms. In one example, the first file and the third file are Verilog files, and the second file, the fourth file, the fifth file, the sixth file, and the seventh file are def files. Wherein Verilog HDL is a hardware description language that describes the structure and behavior of digital system hardware in textual form, and Verilog files may be used to represent logic circuit diagrams, logic expressions, and logic functions performed by a digital logic system; def full scale Design Exchange Format is a module definition file that can be used to describe the connection and positional relationships of digital circuits after placement and routing. The first file, the second file, the third file, the fourth file, the fifth file, the sixth file, and the seventh file may also be generated in other forms, which are not limited herein.
And establishing a local database only comprising the circuit to be simulated and adjacent circuit information according to the generated first file, second file, third file, fourth file, fifth file, sixth file and seventh file.
In this example, based on a design database, the logic structures of a circuit to be simulated and adjacent circuits are tracked, device information and connection information are grasped, a first file containing logic connection information of the circuit to be simulated, a second file containing physical position information of each device in the circuit to be simulated, a fourth file containing physical position information of the adjacent devices, a fifth file containing physical shape information of the connection of each device in the circuit to be simulated and metal layer information, a sixth file containing physical shape information of the adjacent connection and a seventh file containing physical shape information of a power ground wire are generated, and a local database containing only the circuit to be simulated and adjacent circuit information thereof is built based on each generated file.
Because more files are generated, for convenience of management, in one example, the creating the local database according to the first file, the second file, the third file, the fourth file, the fifth file, the sixth file, and the seventh file includes:
Merging the first file and the third file into an eighth file containing logic connection information of the circuit to be simulated and the adjacent circuit; merging the second file and the fourth file into a ninth file containing device physical position information of the circuit to be simulated and the adjacent circuit; combining the fifth file, the sixth file and the seventh file into a tenth file containing the connection physical shape information of the circuit to be simulated and the adjacent circuit and the physical shape information of the adjacent power ground wire;
and establishing the local database according to the eighth file, the ninth file and the tenth file.
Specifically, as shown in fig. 3, the first file containing the logic connection information of the circuit to be simulated is combined with the third file containing the logic connection information of the adjacent circuit to obtain an eighth file containing the logic connection information of the circuit to be simulated and the adjacent circuit; combining the second file containing the physical position information of each device in the circuit to be simulated with the fourth file containing the physical position information of the adjacent devices to obtain a ninth file containing the physical position information of the devices of the circuit to be simulated and the adjacent circuits; and merging the fifth file containing the connection physical shape information of the circuit to be simulated, the sixth file containing the connection physical shape information of the adjacent circuit and the seventh file containing the physical shape information of the adjacent power ground wire to obtain the tenth file containing the connection physical shape information of the circuit to be simulated and the adjacent circuit and the physical shape information of the adjacent power ground wire. Based on the eighth file, the ninth file and the tenth file, a local database only containing the information of the circuit to be simulated and the adjacent circuit is established.
Illustratively, it is assumed that, based on the designed circuit database, a first file Va, a second file Da, a third file Vb, a fourth file Db, a fifth file Dc, a sixth file Dd, and a seventh file De are generated, the first file Va and the third file Vb are combined, and an eighth file Vab describing logic connection information of a circuit to be simulated and an adjacent circuit is generated; merging the second file Da with the fourth file Db to generate a ninth file Dab for describing the physical position information of devices of the circuit to be simulated and the adjacent circuit; and combining the fifth file Dc, the sixth file Dd and the seventh file De to generate a new tenth file Dcde for describing the connection physical shape information of the circuit to be simulated and the adjacent circuit and the physical shape information of the adjacent power ground wire. The local database is reconstructed from the eighth file Vab, the ninth file Dab and the tenth file Dcde.
In this example, by merging the files, effective management of the data information of the circuit to be emulated and the adjacent circuit is achieved.
Based on the port information of the circuit to be simulated, excitation can be accurately applied to the circuit to be simulated in the circuit simulation process. In one example, the starting point and the end point of the circuit to be simulated are taken as ports, excitation is applied to the circuit to be simulated according to the SPICE netlist, and circuit simulation is executed, including:
Generating an excitation file and a measurement file for the circuit to be simulated according to the port information of the circuit to be simulated;
Reading the excitation file, the measurement file and the SPICE netlist in a circuit simulation tool, and executing circuit simulation to obtain an output simulation result.
Specifically, according to port information of the circuit to be simulated, an excitation file and a measurement file for the circuit to be simulated are generated, wherein the excitation file can comprise different input excitation of the design. And reading in the SPICE netlist in the circuit simulation tool to simulate the circuit to be simulated and the adjacent circuit, reading in the excitation file and the measurement file, applying excitation to the circuit to be simulated and measuring the response of the circuit to be simulated to obtain an output simulation result so as to verify the functions of the key circuit and obtain related parameters.
In this example, according to the port information of the circuit to be simulated, the excitation file and the measurement file are generated, so that excitation can be applied to the port of the circuit to be simulated, and the behavior of the circuit to be simulated in simulation can be accurately controlled.
In the circuit simulation method provided by the embodiment, GDS files of the local key circuit and adjacent circuits thereof are obtained according to the database of the overall design circuit, parasitic parameters are extracted for the GDS files of the local key circuit and the adjacent circuits thereof, a SPICE netlist is generated, the SPICE netlist is imported into a circuit simulation tool, excitation is applied by taking the starting point and the end point of the local key circuit as ports, circuit simulation is performed, the influence of the adjacent devices on the devices in the circuit to be simulated can be considered by generating the GDS files of the local key circuit and the adjacent circuits thereof, the extraction precision of the parasitic parameters is ensured, meanwhile, simulation of non-key circuits is avoided, the simulation time is shortened, and the simulation efficiency of the key circuit is effectively improved; and taking the starting point and the end point of the local key circuit as ports, the simulation excitation can be simply and conveniently applied to the key circuit, and the simulation of the key circuit can be accurately controlled.
Example two
Fig. 4 is a schematic structural diagram of a circuit simulation device according to an embodiment of the application. As shown in fig. 4, the circuit simulation device 400 provided in this embodiment may include:
The obtaining module 41 is configured to query a parasitic parameter lookup table through a parasitic parameter extraction tool, obtain parasitic parameters of each device in the GDS file, and convert the GDS file into a SPICE netlist;
The extracting module 42 is configured to query a parasitic parameter lookup table through a parasitic parameter extracting tool, obtain parasitic parameters of each device in the GDS file, and convert the GDS file into a SPICE netlist;
And the simulation module 43 is configured to take a starting point and an end point of the circuit to be simulated as ports of the circuit to be simulated, apply excitation to the ports of the circuit to be simulated according to the SPICE netlist, and execute circuit simulation.
In practical application, the circuit simulation device may be implemented by a computer program, for example, application software or the like; or may be embodied as a medium storing a related computer program, e.g., a usb disk, a cloud disk, etc.; or may also be implemented by physical means, e.g. chips, servers, etc., integrated or installed with the relevant computer program.
GDS, commonly referred to as Geometry Summary Data, is an input file in semiconductor process simulation software that contains geometric data about the chip structure, shape and hierarchy. After the GSD file is generated, the GSD file can be converted to other formats, such as SPICE netlists, as needed for further simulation and analysis. And taking the key circuit as a circuit to be simulated, and generating a GDS file containing parameters of the circuit to be simulated and adjacent circuits thereof based on a database of the design circuit.
Parasitic extraction is the calculation of parasitic effects in the design devices and required wiring interconnections of electronic circuits, including parasitic capacitance, parasitic resistance, and parasitic inductance. The parasitic parameter extraction method in practical application can be various, and the parasitic parameter can be calculated by using a lookup table through a parasitic parameter extraction tool. When converting the GDS file into the SPICE netlist, the parasitic parameters are synthesized into the SPICE netlist.
Compared with the traditional key circuit simulation technology, the whole circuit needs to be simulated, and because the circuit to be simulated can be positioned in the internal position of the whole circuit, the excitation is difficult to apply on the external port. The simulation is only carried out on SPICE netlists of the circuit to be simulated and adjacent circuits thereof, and the starting point and the end point of the circuit to be simulated can be used as ports, so that excitation can be conveniently applied to the ports of the circuit to be simulated.
In the example, according to the database of the overall design circuit, the GDS files of the local key circuit and the adjacent circuits are obtained, parasitic parameters are extracted for the GDS files of the local key circuit and the adjacent circuits thereof, a SPICE netlist is generated, the SPICE netlist is imported into a circuit simulation tool, excitation is applied by taking the starting point and the end point of the local key circuit as ports, circuit simulation is executed, the influence of the adjacent devices on the devices in the circuit to be simulated can be considered by generating the GDS files of the local key circuit and the adjacent circuits thereof, the extraction precision of the parasitic parameters is ensured, meanwhile, simulation of non-key circuits is avoided, the simulation time is shortened, and the simulation efficiency of the key circuit is effectively improved; and taking the starting point and the end point of the local key circuit as ports, the simulation excitation can be simply and conveniently applied to the key circuit, and the simulation of the key circuit can be accurately controlled.
The method for generating the GDS file of the circuit to be simulated and the adjacent circuit thereof may be various, and in one example, the obtaining module may be specifically configured to:
establishing a local database according to the design circuit database, wherein the local database comprises logic connection information, device physical information, connection physical information and physical shape information of adjacent power ground wires of the circuit to be simulated and the adjacent circuit;
And acquiring GDS library files of all devices in the circuit to be simulated and the adjacent circuit according to the local database, and merging the GDS library files of all the devices into the GDS file.
Specifically, reconstructing a local database only comprising the to-be-simulated circuit and adjacent circuit information according to an integral design database, wherein logic connection information, device physical information, connection physical information and physical shape information of adjacent power ground wires of the to-be-simulated circuit and the adjacent circuit in the local database; based on the local database, according to the data information of each device in the circuit to be simulated and the adjacent circuit, acquiring GDS library files corresponding to each device, and merging all the acquired GDS library files into a GDS file. After the GDS files of the circuit to be simulated and the adjacent circuits are obtained, parasitic parameters can be extracted based on the parameter extraction flow according to the parameter extraction library file, namely the lookup table, a SPICE netlist is generated, circuit simulation is carried out by combining the starting point information and the end point information of the circuit to be simulated, and the simulation result is observed and analyzed.
In this example, firstly, a local database containing information of a circuit to be simulated and adjacent circuits is reconstructed according to a design database of an overall circuit, GDS library files of each device in the circuit to be simulated and the adjacent circuits are obtained based on the local database, and GDS files of the circuit to be simulated and the adjacent circuits are generated in a merging mode.
In order to simulate a local circuit, data information of the circuit to be simulated and adjacent circuits thereof needs to be extracted from an integral design circuit database, wherein the specific modes for acquiring the information of the circuit to be simulated and the adjacent circuits thereof can be various. In one example, the acquisition module may be further specifically configured to:
acquiring logic connection information of the circuit to be simulated based on the starting point information and the end point information of the circuit to be simulated according to the design circuit database, and generating a first file containing the logic connection information of the circuit to be simulated;
Based on the logic connection information of the circuit to be simulated, acquiring physical position information of each device in the circuit to be simulated, and generating a second file containing the physical position information of each device in the circuit to be simulated;
determining adjacent devices in a preset range of each device in the circuit to be simulated based on the physical position information of each device in the circuit to be simulated, acquiring the logic connection information and the physical position information of the adjacent devices, and generating a third file containing the logic connection information of the adjacent devices and a fourth file containing the physical position information of the adjacent devices;
based on the physical position information of each device in the circuit to be simulated, acquiring the physical shape information and the metal layer information of the connecting wire of each device in the circuit to be simulated, and generating a fifth file containing the physical shape information and the metal layer information of the connecting wire of each device in the circuit to be simulated;
determining adjacent connecting lines and power ground wires of the same metal layer in a preset range of connecting lines of all devices in the circuit to be simulated based on the physical shape information and the metal layer information of the connecting lines of all devices in the circuit to be simulated, acquiring the physical shape information of the adjacent connecting lines and the power ground wires, and generating a sixth file containing the physical shape information of the adjacent connecting lines and a seventh file containing the physical shape information of the power ground wires;
and establishing the local database according to the first file, the second file, the third file, the fourth file, the fifth file, the sixth file and the seventh file.
Based on a design circuit database, tracking the logic topology structure of the circuit to be simulated according to the starting point information and the end point information of the circuit to be simulated, wherein the logic topology structure comprises the connection information, and the logic topology structure of the circuit to be simulated can be tracked through a back-end tool command in practical application. And obtaining logic connection information of the circuit to be simulated, generating a first file in a Verilog form, and taking the starting point and the end point of the circuit to be simulated as ports of the circuit to be simulated in the first file.
According to the logic connection information of the circuit to be simulated, the physical position of each device in the circuit to be simulated can be grasped by utilizing a back-end tool, so that the physical position information of each device in the circuit to be simulated is obtained, and a second file is generated in the def form.
Starting from the physical position of each device in the circuit to be simulated, respectively extending a preset distance, searching adjacent devices overlapped with the area in a preset range, acquiring logic connection information of the adjacent devices, and generating a third file in a Verilog form; and acquiring the physical position information of the adjacent devices, and generating a fourth file in the def form. Where the predetermined range may be selected based on the needs of the actual production and is not limited thereto, in one example, other neighboring devices that coincide with this area may be searched for based on the physical locations 5um occupied by all devices on the critical circuit.
And grabbing the physical shape and the metal layer information of the connecting lines of all the devices in the circuit to be simulated according to the physical positions of all the devices in the circuit to be simulated, and generating a fifth file in the def form. Starting from the connection line of the circuit device to be simulated, searching for adjacent connection lines with the metal layer and power ground lines within a preset range, wherein the preset range is as described above; acquiring physical shape information of adjacent connecting lines, and generating a sixth file in def form; and acquiring physical shape information of the power ground wire, and generating a seventh file in the form of def.
In practical applications, the first file, the second file, the third file, the fourth file, the fifth file, the sixth file, and the seventh file may have various forms. In one example, the first file and the third file are Verilog files, and the second file, the fourth file, the fifth file, the sixth file, and the seventh file are def files. Wherein Verilog HDL is a hardware description language that describes the structure and behavior of digital system hardware in textual form, and Verilog files may be used to represent logic circuit diagrams, logic expressions, and logic functions performed by a digital logic system; def full scale Design Exchange Format is a module definition file that can be used to describe the connection and positional relationships of digital circuits after placement and routing. The first file, the second file, the third file, the fourth file, the fifth file, the sixth file, and the seventh file may also be generated in other forms, which are not limited herein.
And establishing a local database only comprising the circuit to be simulated and adjacent circuit information according to the generated first file, second file, third file, fourth file, fifth file, sixth file and seventh file.
In this example, based on a design database, the logic structures of a circuit to be simulated and adjacent circuits are tracked, device information and connection information are grasped, a first file containing logic connection information of the circuit to be simulated, a second file containing physical position information of each device in the circuit to be simulated, a fourth file containing physical position information of the adjacent devices, a fifth file containing physical shape information of the connection of each device in the circuit to be simulated and metal layer information, a sixth file containing physical shape information of the adjacent connection and a seventh file containing physical shape information of a power ground wire are generated, and a local database containing only the circuit to be simulated and adjacent circuit information thereof is built based on each generated file.
In one example, the acquisition module may be further specifically configured to:
Merging the first file and the third file into an eighth file containing logic connection information of the circuit to be simulated and the adjacent circuit; merging the second file and the fourth file into a ninth file containing device physical position information of the circuit to be simulated and the adjacent circuit; combining the fifth file, the sixth file and the seventh file into a tenth file containing the connection physical shape information of the circuit to be simulated and the adjacent circuit and the physical shape information of the adjacent power ground wire;
and establishing the local database according to the eighth file, the ninth file and the tenth file.
Specifically, combining a first file containing logic connection information of a circuit to be simulated with a third file containing logic connection information of an adjacent circuit to obtain an eighth file containing logic connection information of the circuit to be simulated and the adjacent circuit; combining the second file containing the physical position information of each device in the circuit to be simulated with the fourth file containing the physical position information of the adjacent devices to obtain a ninth file containing the physical position information of the devices of the circuit to be simulated and the adjacent circuits; and merging the fifth file containing the connection physical shape information of the circuit to be simulated, the sixth file containing the connection physical shape information of the adjacent circuit and the seventh file containing the physical shape information of the adjacent power ground wire to obtain the tenth file containing the connection physical shape information of the circuit to be simulated and the adjacent circuit and the physical shape information of the adjacent power ground wire. Based on the eighth file, the ninth file and the tenth file, a local database only containing the information of the circuit to be simulated and the adjacent circuit is established.
In this example, by merging the files, effective management of the data information of the circuit to be emulated and the adjacent circuit is achieved.
Based on the port information of the circuit to be simulated, excitation can be accurately applied to the circuit to be simulated in the circuit simulation process. In one example, the simulation module may be specifically configured to:
Generating an excitation file and a measurement file for the circuit to be simulated according to the port information of the circuit to be simulated;
Reading the excitation file, the measurement file and the SPICE netlist in a circuit simulation tool, and executing circuit simulation to obtain an output simulation result.
Specifically, according to port information of the circuit to be simulated, an excitation file and a measurement file for the circuit to be simulated are generated, wherein the excitation file can comprise different input excitation of the design. And reading in the SPICE netlist in the circuit simulation tool to simulate the circuit to be simulated and the adjacent circuit, reading in the excitation file and the measurement file, applying excitation to the circuit to be simulated and measuring the response of the circuit to be simulated to obtain an output simulation result so as to verify the functions of the key circuit and obtain related parameters.
In this example, according to the port information of the circuit to be simulated, the excitation file and the measurement file are generated, so that excitation can be applied to the port of the circuit to be simulated, and the behavior of the circuit to be simulated in simulation can be accurately controlled.
In the circuit simulation device provided by the embodiment, according to the database of the overall design circuit, GDS files of the local key circuit and adjacent circuits thereof are obtained, parasitic parameters are extracted for the GDS files of the local key circuit and the adjacent circuits thereof, a SPICE netlist is generated, the SPICE netlist is imported into a circuit simulation tool, excitation is applied by taking the starting point and the end point of the local key circuit as ports, circuit simulation is performed, and the influence of the adjacent devices on the devices in the circuit to be simulated can be considered by generating the GDS files of the local key circuit and the adjacent circuits thereof, so that the extraction precision of the parasitic parameters is ensured, meanwhile, simulation of non-key circuits is avoided, the simulation time is shortened, and the simulation efficiency of the key circuit is effectively improved; and taking the starting point and the end point of the local key circuit as ports, the simulation excitation can be simply and conveniently applied to the key circuit, and the simulation of the key circuit can be accurately controlled.
Example III
Fig. 5 is a schematic structural diagram of an electronic device provided in an embodiment of the disclosure, as shown in fig. 5, where the electronic device includes:
A processor 291, the electronic device further comprising a memory 292; a communication interface (Communication Interface) 293 and bus 294 may also be included. The processor 291, the memory 292, and the communication interface 293 may communicate with each other via the bus 294. Communication interface 293 may be used for information transfer. The processor 291 may call logic instructions in the memory 292 to perform the methods of the above-described embodiments.
Further, the logic instructions in memory 292 described above may be implemented in the form of software functional units and stored in a computer-readable storage medium when sold or used as a stand-alone product.
The memory 292 is a computer-readable storage medium that may be used to store a software program, a computer-executable program, and program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 291 executes functional applications and data processing by running software programs, instructions and modules stored in the memory 292, i.e., implements the methods of the method embodiments described above.
Memory 292 may include a storage program area that may store an operating system, at least one application program required for functionality, and a storage data area; the storage data area may store data created according to the use of the terminal device, etc. Further, memory 292 may include high-speed random access memory, and may also include non-volatile memory.
The disclosed embodiments provide a non-transitory computer readable storage medium having stored therein computer-executable instructions that, when executed by a processor, are configured to implement the method of the previous embodiments.
Example IV
The disclosed embodiments provide a computer program product comprising a computer program which, when executed by a processor, implements the method provided by any of the embodiments of the disclosure described above.
Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (8)
1. A circuit simulation method, comprising:
According to a database of a design circuit, GDS files of the circuit to be simulated and adjacent circuits thereof are obtained, wherein the GDS files comprise circuit parameters of the circuit to be simulated and the adjacent circuits thereof, and the circuit to be simulated is a local circuit of the design circuit;
Inquiring a parasitic parameter inquiry table through a parasitic parameter extraction tool, obtaining parasitic parameters of each device in the GDS file, and converting the GDS file into a SPICE netlist;
Taking the starting point and the end point of the circuit to be simulated as ports of the circuit to be simulated, applying excitation to the ports of the circuit to be simulated according to the SPICE netlist, and executing circuit simulation;
the step of obtaining the GDS file of the circuit to be simulated and the physically adjacent circuit thereof according to the design circuit database comprises the following steps:
establishing a local database according to the design circuit database, wherein the local database comprises logic connection information, device physical information, connection physical information and physical shape information of adjacent power ground wires of the circuit to be simulated and the adjacent circuit;
And acquiring GDS library files of all devices in the circuit to be simulated and the adjacent circuit according to the local database, and merging the GDS library files of all the devices into the GDS file.
2. The method of claim 1, wherein building a local database from the design circuit database comprises:
acquiring logic connection information of the circuit to be simulated based on the starting point information and the end point information of the circuit to be simulated according to the design circuit database, and generating a first file containing the logic connection information of the circuit to be simulated;
Based on the logic connection information of the circuit to be simulated, acquiring physical position information of each device in the circuit to be simulated, and generating a second file containing the physical position information of each device in the circuit to be simulated;
determining adjacent devices in a preset range of each device in the circuit to be simulated based on the physical position information of each device in the circuit to be simulated, acquiring the logic connection information and the physical position information of the adjacent devices, and generating a third file containing the logic connection information of the adjacent devices and a fourth file containing the physical position information of the adjacent devices;
based on the physical position information of each device in the circuit to be simulated, acquiring the physical shape information and the metal layer information of the connecting wire of each device in the circuit to be simulated, and generating a fifth file containing the physical shape information and the metal layer information of the connecting wire of each device in the circuit to be simulated;
determining adjacent connecting lines and power ground wires of the same metal layer in a preset range of connecting lines of all devices in the circuit to be simulated based on the physical shape information and the metal layer information of the connecting lines of all devices in the circuit to be simulated, acquiring the physical shape information of the adjacent connecting lines and the power ground wires, and generating a sixth file containing the physical shape information of the adjacent connecting lines and a seventh file containing the physical shape information of the power ground wires;
and establishing the local database according to the first file, the second file, the third file, the fourth file, the fifth file, the sixth file and the seventh file.
3. The method of claim 2, wherein the first file and the third file are Verilog files, and the second file, the fourth file, the fifth file, the sixth file, and the seventh file are def files.
4. The method of claim 2, wherein the creating the local database from the first file, the second file, the third file, the fourth file, the fifth file, the sixth file, and the seventh file comprises:
Merging the first file and the third file into an eighth file containing logic connection information of the circuit to be simulated and the adjacent circuit; merging the second file and the fourth file into a ninth file containing device physical position information of the circuit to be simulated and the adjacent circuit; combining the fifth file, the sixth file and the seventh file into a tenth file containing the connection physical shape information of the circuit to be simulated and the adjacent circuit and the physical shape information of the adjacent power ground wire;
and establishing the local database according to the eighth file, the ninth file and the tenth file.
5. The method of any of claims 1-4, wherein the performing circuit simulation with the start point and the end point of the circuit to be simulated as ports, applying stimulus to the circuit to be simulated according to the SPICE netlist, comprises:
Generating an excitation file and a measurement file for the circuit to be simulated according to the port information of the circuit to be simulated;
Reading the excitation file, the measurement file and the SPICE netlist in a circuit simulation tool, and executing circuit simulation to obtain an output simulation result.
6. A circuit emulation device, comprising:
The system comprises an acquisition module, a calculation module and a calculation module, wherein the acquisition module is used for acquiring GDS files of a circuit to be simulated and adjacent circuits thereof according to a database of the design circuit, the GDS files comprise circuit parameters of the circuit to be simulated and the adjacent circuits thereof, and the circuit to be simulated is a local circuit of the design circuit;
The extraction module is used for inquiring the parasitic parameter lookup table through a parasitic parameter extraction tool, obtaining the parasitic parameters of each device in the GDS file and converting the GDS file into a SPICE netlist;
The simulation module is used for taking the starting point and the end point of the circuit to be simulated as the ports of the circuit to be simulated, applying excitation to the ports of the circuit to be simulated according to the SPICE netlist, and executing circuit simulation;
the acquisition module is specifically configured to:
establishing a local database according to the design circuit database, wherein the local database comprises logic connection information, device physical information, connection physical information and physical shape information of adjacent power ground wires of the circuit to be simulated and the adjacent circuit;
And acquiring GDS library files of all devices in the circuit to be simulated and the adjacent circuit according to the local database, and merging the GDS library files of all the devices into the GDS file.
7. An electronic device, comprising: a processor, and a memory communicatively coupled to the processor;
the memory stores computer-executable instructions;
The processor executes computer-executable instructions stored in the memory to implement the method of any one of claims 1-5.
8. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor are adapted to carry out the method of any one of claims 1-5.
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