CN115640768A - Method, apparatus, device, medium and program product for emulating a circuit - Google Patents
Method, apparatus, device, medium and program product for emulating a circuit Download PDFInfo
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Abstract
Embodiments of the present disclosure provide methods, apparatuses, devices, media and program products for emulating a circuit, relating to the field of electronic circuits. In the method, a first simulation result of a model for characterizing the circuit is determined, the model including a set of modules under test, the set of modules under test being excited by a corresponding set of test excitations. A target simulation state snapshot of the model at the target time is obtained from the first simulation result based on identifying in the modified model one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test. Simulating the modified model based on the target simulation state snapshot to obtain a second simulation result. In this way, by taking a target simulation state snapshot based on one of the modified test stimulus and the modified module under test, an accurate prior simulation state may be automatically obtained to accelerate the simulation process, thereby improving simulation efficiency.
Description
Technical Field
Embodiments of the present disclosure generally relate to the field of circuits. More particularly, embodiments of the present disclosure relate to methods, apparatuses, devices, computer-readable storage media and computer program products for simulating a circuit.
Background
In the chip design and development process, a digital simulator is used for simulating and verifying the circuit, so that a large amount of hardware resource consumption can be saved. However, as chip design scales up, it may take a long time to perform a complete simulation of a circuit. In this case, performing a complete simulation (also called a full-scale simulation) after each circuit modification would greatly increase the development cycle of the chip. Therefore, a solution capable of performing simulation for modification of a circuit is required to improve simulation efficiency.
Disclosure of Invention
The embodiment of the disclosure provides a scheme of a simulation circuit.
In a first aspect of the disclosure, a method for simulating a circuit is provided. The method comprises the following steps: a first simulation result for a model characterizing a circuit is determined, where the model includes a set of modules under test and the set of modules under test are excited by a corresponding set of test excitations. The method further comprises the following steps: a target simulation state snapshot of the model at the target time is obtained from the first simulation result based on identifying in the modified model one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test. The method further comprises the following steps: based on the target simulation state snapshot, the modified model is simulated to obtain a second simulation result.
In this way, by taking a target simulation state snapshot based on one of the modified test stimulus and the modified module under test, an accurate prior simulation state may be automatically obtained to accelerate the simulation process, thereby improving simulation efficiency.
In some embodiments of the first aspect, the modified module under test may be identified by: identifying one or more modified files corresponding to the modified model; and determining the modules to be tested in the one or more modified files as modified modules to be tested. In this way, the modified module under test may be quickly identified, thereby speeding up the second simulation process.
In some embodiments of the first aspect, the target simulation state snapshot may be obtained from the first simulation result by: determining a first time in the model before the set of modules under test begin simulation as the target time based on identifying the modified test stimulus in the modified model and determining that the set of modules under test remains unchanged in the model and the modified model; or determining a second moment in the model at which the modified module under test begins simulation as the target moment based on identifying the modified module under test in the modified model and determining that the set of test stimuli remains unchanged in the model and the modified model, and based on determining that the modified module under test satisfies a predetermined condition associated with at least timing.
In this way, a suitable target simulation state snapshot can be automatically and quickly taken, thereby speeding up the simulation process.
In some embodiments of the first aspect, it may be determined that the modified module under test satisfies the predetermined condition by: determining that the timing of the modified module under test remains unchanged in the model and the modified model. In this way, the acquired target simulation state snapshot may be made applicable to the simulation of the modified model.
In some embodiments of the first aspect, it may be determined that the timing of the modified module under test remains unchanged in the model and the modified model by: determining that the timing of the modified module under test remains unchanged in the model and the modified model based on determining that an instantiation relationship and an external connection relationship of the modified module under test remain unchanged in the model and the modified model. In this way, it may be efficiently determined whether the modified module under test satisfies the timing invariant condition.
In some embodiments of the first aspect, one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test may be identified by: identifying a modified plurality of modules under test of the set of modules under test, the modified module under test being the earliest module under test to begin simulation among the modified plurality of modules under test, and wherein determining that the modified module under test satisfies the predetermined condition comprises determining that a corresponding plurality of timings of the modified plurality of modules under test remain unchanged in the model and the modified model. In this way, the acquired target simulation state snapshot may be made applicable to the simulation of the modified model, thereby avoiding simulation errors.
In some embodiments of the first aspect, the method further comprises: obtaining the instantiation relationship and the external connection relationship of the modified module under test from the first simulation result for determining that the timing of the modified module under test remains unchanged in the model and the modified model. In this way, the acquired target simulation state snapshot may be made applicable to the simulation of the modified model.
In some embodiments of the first aspect, the method further comprises: marking a group of modules in the set of modules under test, and wherein the first simulation result includes a corresponding group of simulation state snapshots of the set of modules under test when the marked group of modules start simulation, but does not include a corresponding simulation state snapshot of the set of modules under test when unmarked modules in the set of modules under test start simulation.
In some embodiments of the first aspect, it may also be determined that the modified module under test satisfies the predetermined condition by: determining that the modified module under test is included in the marked set of modules. In this way, the number of simulation state snapshots that need to be recorded at the first simulation can be reduced, thereby conserving resources.
In some embodiments of the first aspect, the one or more modified files may be identified based on at least one of: the modification time of the file; and a file-specific hash value. In this way, the modified file, and thus the modified module under test, may be quickly identified.
In a second aspect of the present disclosure, an apparatus for emulating a circuit is provided. The device comprises: a first simulation unit configured to determine a first simulation result of a model for characterizing a circuit, the model comprising a set of modules under test excited by a corresponding set of test excitations. The device still includes: a snapshot obtaining unit configured to obtain a target simulation state snapshot of the model at a target time from the first simulation result based on identifying one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test in the modified model. The device still includes: a second simulation unit configured to simulate the modified model based on the target simulation state snapshot to obtain a second simulation result.
In some embodiments of the second aspect, the snapshot obtaining unit is configured to identify one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test in the modified model by: identifying one or more modified files corresponding to the modified model; and determining a module under test in the one or more modified files as the modified module under test.
In some embodiments of the second aspect, the snapshot obtaining unit is configured to: determining a first time in the model before the set of modules under test begin simulation as the target time based on identifying the modified test stimulus in the modified model and determining that the set of modules under test remains unchanged in the model and the modified model; or determining a second moment in the model at which the modified module under test begins simulation as the target moment based on identifying the modified module under test in the modified model and determining that the set of test stimuli remains unchanged in the model and the modified model, and based on determining that the modified module under test satisfies a predetermined condition associated with at least timing.
In some embodiments of the second aspect, the snapshot obtaining unit is configured to determine that the modified module under test satisfies the predetermined condition by: determining that the timing of the modified module under test remains unchanged in the model and the modified model.
In some embodiments of the second aspect, the snapshot acquisition unit is configured to determine that the timing of the modified module under test remains unchanged in the model and the modified model by: determining that the timing of the modified module under test remains unchanged in the model and the modified model based on determining that an instantiation relationship and an external connection relationship of the modified module under test remain unchanged in the model and the modified model.
In some embodiments of the second aspect, the snapshot obtaining unit is configured to identify one of the modified test stimulus of the set of test stimuli and the modified module under test of the set of modules under test by: identifying a modified plurality of modules under test in the set of modules under test, the modified module under test being the earliest module under test to begin simulating among the modified plurality of modules under test, and wherein the snapshot acquisition unit is configured to determine that the modified module under test satisfies the predetermined condition by: determining that a corresponding plurality of timings of the modified plurality of modules under test remain unchanged in the model and the modified model.
In some embodiments of the second aspect, the apparatus further comprises: a module data obtaining unit configured to obtain the instantiation relationship and the external connection relationship of the modified module under test from the first simulation result for determining that the timing of the modified module under test remains unchanged in the model and the modified model.
In some embodiments of the second aspect, the apparatus further comprises: a marking unit configured to mark a group of modules in the set of modules under test, and wherein the first simulation result includes a corresponding group of simulation state snapshots of the set of modules under test when the marked group of modules start simulation, but does not include a corresponding simulation state snapshot of the set of modules under test when the unmarked modules in the set of modules under test start simulation.
In some embodiments of the second aspect, the snapshot obtaining unit is configured to determine that the modified module under test is included in the marked set of modules by: determining that the modified module under test is included in the marked set of modules.
In some embodiments of the second aspect, the snapshot obtaining unit is configured to identify the one or more modified files based on at least one of: the modification time of the file; and a file-specific hash value.
In a third aspect of the present disclosure, there is provided an electronic device comprising: at least one computing unit; at least one memory coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, the instructions when executed by the at least one computing unit, causing the apparatus to implement the method provided by the first aspect.
In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored, wherein the computer program is executed by a processor to implement the method provided by the first aspect.
In a fifth aspect of the present disclosure, there is provided a computer program product comprising computer executable instructions which, when executed by a processor, implement part or all of the steps of the method of the first aspect.
It will be appreciated that the electronic device of the third aspect, the computer storage medium of the fourth aspect or the computer program product of the fifth aspect provided above is adapted to perform at least part of the method provided by the first aspect. Therefore, explanations or explanations regarding the first aspect are equally applicable to the third, fourth, and fifth aspects. In addition, the beneficial effects achieved by the second aspect, the third aspect, the fourth aspect and the fifth aspect may refer to the beneficial effects in the corresponding method, and are not described herein again.
Drawings
The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements, and wherein:
FIG. 1 illustrates a schematic diagram of an example environment in which various embodiments of the present disclosure can be implemented;
FIG. 2 shows a schematic diagram of a process of emulating a circuit, according to some embodiments of the present disclosure;
FIG. 3 illustrates a schematic diagram of a process of accelerating a simulation for a modified test stimulus in accordance with some embodiments of the present disclosure;
FIG. 4 illustrates a schematic diagram of a process of accelerating simulation for a modified module under test, in accordance with some embodiments of the present disclosure;
FIG. 5 illustrates a flow diagram of a process for simulating a circuit, according to some embodiments of the present disclosure;
FIG. 6 shows a schematic block diagram of an apparatus for emulating a circuit, according to some embodiments of the present disclosure; and
FIG. 7 illustrates a block diagram of a computing device capable of implementing various embodiments of the present disclosure.
Detailed Description
Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While certain embodiments of the present disclosure are shown in the drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the disclosure are for illustration purposes only and are not intended to limit the scope of the disclosure.
In describing embodiments of the present disclosure, the terms "include" and its derivatives should be interpreted as being inclusive, i.e., "including but not limited to. The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.
Currently, a chip design process may include steps of chip architecture, register Transfer Level (RTL) design, functional simulation, synthesis, static timing analysis, design for test (DFT) design, formal verification or equivalence check, layout and routing, design rule check, GDSII file generation, and the like. The resulting GDSII file may be delivered to a chip manufacturer for production.
As briefly mentioned above, during the functional simulation (also referred to as pre-simulation, hereinafter also simply referred to as simulation) stage, the simulator can be utilized to efficiently analyze and verify the correctness of the design logic of the circuit, thereby improving the efficiency of chip design. However, with the expansion of chip design scale, because the time required for a complete simulation is long, a scheme capable of performing simulation for circuit modification, that is, an incremental simulation technique, is required to improve the simulation efficiency and thus shorten the chip development cycle.
In performing simulation, the use of the simulator may be divided into a simulation compilation phase (i.e., compilation period) and a simulation run phase (i.e., run period). In a simulation compilation stage, a simulator may receive a source file and obtain a simulation file by compilation. The source files may be code files written in a hardware description language, and examples of the hardware description language may include VHDL and Verilog, and the like.
The source files may include a Design Under Test (DUT) file for describing a DUT in a circuit and a Test Bench (TB) file for describing a TB platform. A design under test in a circuit may include one or more modules under test in the circuit that are designed to perform a target function and are tested during a simulation phase. A test platform, also referred to as a test environment, refers to the environment used to test DUTs. The test platform may include a number of modules, such as an interface module for interacting with the DUT, a stimulus module for generating a stimulus, a driver module for driving the stimulus to the DUT, and other modules for monitoring the output of the DUT and verifying whether the output satisfies a condition.
Based on the source files, the emulator may compile the emulation files. In the simulation operation stage, a user can operate simulation software with a simulation file as a main carrier to obtain a simulation result. The simulation result may include analysis data (profiling data) obtained after the simulation is completed.
Currently, some incremental simulation schemes for simulating circuits have been proposed. For example, the inputs and outputs of each circuit block may be recorded for successive clocks in a previous simulation. In simulating the modified circuit model, it may be compared at each time instant whether the inputs of the unmodified circuit module are the same as the inputs at that time instant in the previous simulation. If the input is not changed, the output of the circuit block from the previous simulation can be utilized without re-simulating the circuit block. However, in this scheme, it is necessary to record the input and output of each circuit block at each time in the first simulation, and to compare whether the input of the unmodified circuit block is changed at each time in the second simulation, which consumes a lot of time and memory resources.
In other examples, a snapshot of the simulation state of the circuit model at some point in time (also referred to as a checkpoint) may be recorded in the first simulation. In this way, at the time of the second simulation, the recorded simulation state snapshot can be loaded to avoid re-simulating the state of the circuit model before the checkpoint, thereby accelerating the simulation process. However, in this scenario, if the module under test in the circuit is modified in the second simulation, the previous simulation state snapshot may no longer be applicable to the modified circuit model. Furthermore, in this approach, it may be difficult to rely on the expert experience of the user to set multiple checkpoints in the first simulation to record corresponding simulation state snapshots, and to manually determine a target checkpoint to obtain a suitable simulation state snapshot at the second simulation. For example, since possible modifications to the circuit cannot be predicted at the first simulation, multiple checkpoints distributed evenly in time may typically be set for recording corresponding simulation state snapshots, which may result in some unnecessary simulation state snapshots being recorded, thereby causing a waste of resources. Furthermore, at the time of the second simulation, the user may not be able to determine which checkpoints the modification of the circuit is associated with, and therefore it is difficult to obtain an accurate snapshot of the simulation state to accelerate the second simulation.
To address, at least in part, the above problems, as well as other potential problems, various embodiments of the present disclosure provide a solution for simulating a circuit. In general, according to various embodiments described herein, a first simulation result is determined for a model characterizing a circuit, the model including a set of modules under test, the set of modules under test being excited by a corresponding set of test excitations. A target simulation state snapshot of the model at the target time is obtained from the first simulation result based on identifying in the modified model one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test. Based on the target simulation state snapshot, the modified model is simulated to obtain a second simulation result.
In this way, by determining a target time corresponding to the target simulation state snapshot to be taken based on the identified one of the modified test stimulus and the modified module under test, a more accurate simulation state snapshot may be taken to accelerate the second simulation. In addition, according to the embodiment of the disclosure, whether the input of the module to be tested changes or not needs to be compared at each moment, so that the time and the memory resource required by simulation can be reduced.
Various example embodiments of the present disclosure are described below with reference to the accompanying drawings.
Fig. 1 illustrates a schematic diagram of an example environment in which various embodiments of the present disclosure can be implemented. As shown in FIG. 1, a user 110 may input a source file to a simulator 120 and obtain a compiled simulation file 130 from the simulator 120. The user 110 may also input a compilation option to the emulator 120 to specify a compilation rule for the source file. Based on the simulation file 130, the user 110 may input a simulation command to run the simulation file 130 to obtain a simulation result. In some embodiments, the simulation results may be sent directly to other processing devices without being sent to user 110 (as shown by the dashed lines). Simulator 120 and simulation file 130 may run on any suitable computing device, and the scope of the present disclosure is not limited in this respect.
FIG. 2 shows a schematic diagram of a process 200 of simulating a circuit, according to some embodiments of the present disclosure. The process 200 will be described below with reference to fig. 1. Process 200 may be implemented by any suitable emulation device for emulating a circuit, and the scope of the present disclosure is not limited in this respect. As shown in fig. 2, the simulation apparatus may perform at least two simulations, and may accelerate the second simulation using the simulation result of the first simulation. In a first simulation, at block 201, the simulation device statically compiles a source file with the simulator 120 to obtain a simulation file 202. As described above, the source files may describe a simulation model (hereinafter also simply referred to as a model) used to characterize the circuit under test. The model comprises a module set to be tested in the circuit and an excitation module for exciting the module set to be tested. The excitation module may generate a set of test excitations to excite a corresponding set of modules under test. At block 203, the simulation device runs the simulation file 202 for simulation to determine a simulation result 204. The simulation result 204 may include profiling data of the circuit under test. Simulation results 204 also include a snapshot of the simulation state of the model at least one time. In some embodiments, the recorded at least one time may include a time at which each module in the set of modules under test begins simulation, and need not include every time in the simulation process. Additionally, the recorded at least one time may include a time before the module under test starts the simulation.
In some embodiments, upon static compilation at block 201, the simulation device may mark a set of modules in the set of modules under test. Depending on the actual application, the tagged set of modules (also referred to as tagging modules) may be one or more modules of interest to user 110, such as modules that user 110 believes may change in subsequent simulations. In this case, the simulation result 204 may include only the simulation state snapshot of the module set under test at the time of starting simulation of each labeled module, and need not include the simulation state snapshot at the time of starting simulation of each module. In this way, the simulation state snapshots that need to be recorded at the first simulation can be reduced, thereby reducing resource consumption.
In a second simulation, at block 221, the simulation device recompiles the modified source files corresponding to the modified model using the simulator 120 to obtain simulation files 222. In the compilation process, in some embodiments, the modified test stimulus may be identified in the modified model. For example, one or more of the test stimuli in the set of test stimuli may be modified to increase coverage. Alternatively or additionally, the modified module under test may be identified in the modified model. For example, the module under test may be modified to attempt to meet power consumption, performance and area (PPA) requirements.
Based on identifying one of the modified test stimulus and the modified module under test in the modified model, the simulation device runs simulation file 222 at block 223. While running simulation file 222, the simulation device takes target simulation state snapshot 224 of the model at the target time from simulation results 204 and runs simulation file 222 based on target simulation state snapshot 224 to obtain new simulation results 225. In other words, the simulation device begins a second simulation with the target simulation state snapshot 225.
In some embodiments, if only modified test stimuli are identified in the modified model, i.e., the set of modules under test is not modified, a first time before the set of modules under test starts simulation in the first simulated model may be determined as the target time, i.e., the second simulation is accelerated based on a snapshot of the simulation state of the model at the first time.
In some embodiments, the first time is a time when initialization of the model is completed or after completion. Initialization of the model may include a memory allocation process. Additionally or alternatively, the initialization of the model may include a signal initialization process. In this way, by loading the simulation state snapshot of the model at the first time, redundant memory allocation and/or signal initialization processes may be avoided, thereby reducing simulation overhead.
FIG. 3 shows a schematic diagram of a process 300 of accelerating simulation for modified test stimulus, in accordance with some embodiments of the present disclosure. As shown in FIG. 3, the TB 310 interacts with the DUT320 to test the DUT 320. The TB 310 may deliver a set of test stimuli to the DUT320 to stimulate a set of modules under test in the DUT 320. The set of modules under test may include module 321 and module 322.
In the first simulation, the initialization of the model, for example, the memory allocation and/or the signal initialization, is performed first before the module under test is simulated. After initialization of the model is completedA set of modules under test is simulated based on the delivered set of test stimuli. And recording the simulation state snapshot of the model at least one moment in time during the first simulation. As shown in FIG. 3, a snapshot of the simulation state of the model at time 0 at or after the initialization is complete is recorded. The simulation state snapshots of the model at the beginning of the simulation at block 321 and block 322 are recorded. Specifically, the module 321 is at T 0 Time of day is simulated and the model is at T 0 Time of day simulation state snapshot S 0 Is recorded, block 322 at T 1 Time of day is simulated and the model is at T 1 Time of day simulation state snapshot S 1 Is recorded. It should be understood that the time when the simulation is started by the module may also include a time near the start of the simulation before the simulation is started.
At the time of the second simulation, based on the determination at block 221 that only the modified test stimulus is included in the modified model, the simulation device obtains from the simulation results 204 a simulation state snapshot of the model at a first time (i.e., time 0, shown in dashed lines) in the first simulation as the target simulation state snapshot 224 shown in FIG. 2. In the example shown in FIG. 3, the target simulation state snapshot 224 records the simulation state snapshot of the model after initialization is complete.
With continued reference to FIG. 2, in some embodiments, if only the modified module under test is identified in the modified model, i.e., the test stimulus set is not modified, the simulation apparatus may determine whether the modified module under test satisfies a predetermined condition associated with at least timing. If it is determined that the modified module under test satisfies the predetermined condition, at block 223, the simulation apparatus may obtain, from the simulation result 204 of the first simulation, a simulation state snapshot of the model at a second time when the modified module under test starts to simulate, as the target simulation state snapshot 224. Based on target simulation state snapshot 224, the simulation device may run simulation file 222 to obtain new simulation results 225.
In some embodiments, at block 221, a modified module under test may be identified with a file corresponding to the modified model. In general, a source file may include one or more files describing a module under test, and each file may include code describing one or more modules under test. In some embodiments, the modified file may be identified in a plurality of files corresponding to the modified model, and one or more of the to-be-tested modules in the modified file may be determined to be modified to-be-tested modules.
In some embodiments, the modified file may be identified based on a modification time of the file. For example, if a file is determined to be modified after a first simulation, the file may be determined to be a modified file. Conversely, if the modification time of the file is determined to be before the first simulation, the file may be determined to be an unmodified file. Alternatively or additionally, the modified file may be identified based on a file-specific hash value. If the hash value of the file changes, it may be determined that the file is a modified file. For example, the hash value of the file may be calculated using a suitable algorithm, such as the MD5 algorithm.
In some embodiments, at block 221, the simulation device may load the module data 226 generated at the first simulation to determine whether the modified module under test satisfies a predetermined condition associated with at least timing. Module data 226 may also be included in the simulation results 204. In some embodiments, if it is determined that the timing of the modified module under test remains unchanged in the model at the time of the first simulation and the modified model at the time of the second simulation, it may be determined that the modified module under test satisfies the predetermined condition. In other words, if the modification of the model does not involve a change in the timing of the module under test, the modified module under test may be considered to satisfy the predetermined condition.
In some embodiments, it may be determined whether the timing of the module under test has changed based on data in module data 226 indicating the instantiation and external connection relationships of the module under test. For each module to be tested, the instantiation relationship and the external connection relationship between the module and other modules to be tested can be determined in the compiling stage. The external connection relationship may include a pin connection relationship and a flying lead connection relationship between modules, and the like. If any one of the instantiation relationship and the external connection relationship of the module to be tested is determined to be changed, the time sequence of the module can be considered to be changed. Conversely, if it is determined that neither the instantiation nor the external connection of the module under test has changed, it may be assumed that the timing of the module will not change.
In some embodiments, as described above, the predetermined condition is also associated with whether the module under test is a tagged module if a group of modules is tagged in the set of modules under test and the simulation results 204 include only simulation state snapshots of the model at the time the group of tagged modules began the simulation and not simulation state snapshots of the model at other times. Therefore, in addition to detecting whether the timing sequence is changed, the simulation device also detects whether the module to be tested is a marking module. If it is determined that the modified module under test is included in the set of labeled modules, i.e., the modified module under test is determined to be a labeled module, it may be determined that the modified module under test satisfies the predetermined condition. Conversely, if it is determined that the modified module under test is not a flagged module, it may be determined that the modified module under test does not satisfy the predetermined condition. In this way, simulation errors due to the corresponding simulation state snapshot not being included in simulation results 204 may be avoided.
In some embodiments, if only one modified module under test is identified in the modified model and the module satisfies the predetermined condition, the time when the module starts simulation in the first simulation may be determined as the second time, i.e., the target time. In some embodiments, if a modified plurality of modules under test are identified in the modified model, it is necessary to determine whether the modified plurality of modules under test all satisfy a predetermined condition, such as a timing invariant and a flag module. If the modified one or more modules under test do not satisfy the predetermined condition, the compilation process may be stopped to prevent subsequent simulation errors. The simulation error is due to, for example, the corresponding simulation state snapshot not being included in the simulation result 204. The simulation error may also be due to the fact that the acquired target simulation state snapshot 224 is no longer applicable to the modified model.
If it is determined that the modified modules to be tested all satisfy the predetermined condition, the corresponding time of the module to be tested, which is earliest to start simulation, of the modified modules to be tested may be determined as the second time and the target time. In this way, it may be ensured that the acquired target simulation state snapshot 224 does not include simulation of any modified module under test, thereby avoiding simulation errors.
FIG. 4 shows a schematic diagram of a process 400 for accelerating simulation for a modified module under test, in accordance with some embodiments of the present disclosure. As described with reference to fig. 3, TB 310 interacts with DUT320 to test DUT 320. The TB 310 may deliver a set of test stimuli to the DUT320 to stimulate a set of modules under test in the DUT 320. The set of modules under test may include module 321 and module 322.
In the first simulation, the initialization of the model, for example, the memory allocation and/or the signal initialization, is performed first before the module under test is simulated. After initialization of the model is complete, the set of modules under test is simulated based on the delivered set of test stimuli. And recording the simulation state snapshot of the model at least one moment in time during the first simulation. As shown in FIG. 3, a simulation state snapshot of the model at time 0 at or after initialization is complete is recorded. The simulation state snapshot of the model at the time that module 321 and module 322 begin simulation is recorded. Specifically, module 321 is at T 0 Time of day is simulated and the model is at T 0 Time of day simulation state snapshot S 0 Is recorded, block 322 at T 1 Time of day is simulated and the model is at T 1 Time of day simulation state snapshot S 1 Is recorded.
At the second simulation, if it is determined at block 221 that only modified module under test 322 is included in the modified model and that modified module under test 322 satisfies the predetermined condition, the model under simulation at T in the first simulation may be obtained from simulation results 204 1 The simulation state snapshot of the time (i.e., the time that the module under test 322 begins simulation, shown in dashed lines) serves as the target simulation state snapshot 224 shown in FIG. 2. Based on the simulation state snapshot 224, the simulation device continues to simulate the modified model at block 223 to obtain simulation results 225.
In other examples, although not shown in FIG. 4, if it is determined at block 221 that only modified module under test 321 is included in the modified model and that modified module under test 321 satisfies the predetermined condition, then the method may proceed fromThe simulation result 204 obtains the model T in the first simulation 0 The simulation state snapshot at the time (i.e., the time when the module under test 321 starts to simulate) is taken as the target simulation state snapshot 224 shown in fig. 2.
In still other examples, if it is determined at block 221 that modified modules under test 321 and 322 are included in the modified model and that modified modules under test 321 and 322 satisfy the predetermined condition, the model in the first simulation at T may be obtained from simulation result 204 0 The simulation state snapshot at the time (i.e., the time when the module under test 321 starts to simulate) is taken as the target simulation state snapshot 224 shown in fig. 2.
In this way, by utilizing the previous target simulation state snapshot, the simulation overhead before the target time can be saved, thereby improving the simulation efficiency and shortening the verification period. And secondly, because only the simulation state snapshot of the model when the module to be tested starts simulation is recorded in the first simulation, but not the simulation state snapshots of the model at all times, the resource required for recording the simulation state snapshot in the first simulation can be reduced. In addition, the time when the modified module to be tested starts simulation or the time when initialization is completed is determined as the target time to obtain the target simulation state snapshot of the target time, so that the simulation state snapshot of the key time for modification of the model can be automatically determined, and more accurate simulation state snapshot can be obtained to accelerate simulation.
FIG. 5 illustrates a flow diagram of a process 500 of simulating a circuit, according to some embodiments of the present disclosure. Process 500 may be implemented by any suitable computing device. At block 510, a first simulation result of a model for characterizing a circuit is determined, the model including a set of modules under test excited by a corresponding set of test excitations.
At block 520, a target simulation state snapshot of the model at a target time is obtained from the first simulation result based on identifying in the modified model one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test.
In some embodiments, identifying in the modified model one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test comprises: identifying one or more modified files corresponding to the modified model; and determining a module under test in the one or more modified files as the modified module under test.
In some embodiments, obtaining the target simulation state snapshot from the first simulation result based on identifying in the modified model one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test comprises: determining a first time in the model before the set of modules under test begin simulation as the target time based on identifying the modified test stimulus in the modified model and determining that the set of modules under test remains unchanged in the model and the modified model; or based on identifying the modified module under test in the modified model and determining that the set of test stimuli remains unchanged in the model and the modified model, and based on determining that the modified module under test satisfies a predetermined condition associated with at least timing, determining a second time instant in the model at which the modified module under test begins simulation as the target time instant.
In some embodiments, determining that the modified module under test satisfies the predetermined condition comprises: determining that the timing of the modified module under test remains unchanged in the model and the modified model.
In some embodiments, determining that the modified timing of the module under test remains unchanged in the model and the modified model comprises: determining that the timing of the modified module under test remains unchanged in the model and the modified model based on determining that instantiation and external connectivity relationships of the modified module under test remain unchanged in the model and the modified model.
In some embodiments, identifying one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test includes identifying a modified plurality of modules under test in the set of modules under test that was the earliest to begin simulation among the modified plurality of modules under test, and wherein determining that the modified module under test satisfies the predetermined condition includes determining that a corresponding plurality of timings of the modified plurality of modules under test remain unchanged in the model and the modified model.
At block 530, the modified model is simulated based on the target simulation state snapshot to obtain a second simulation result.
In some embodiments, process 500 further includes: obtaining the instantiation relationship and the external connection relationship of the modified module under test from the first simulation result for determining that the timing of the modified module under test remains unchanged in the model and the modified model.
In some embodiments, process 500 further includes: marking a group of modules in the set of modules under test, and wherein the first simulation result includes a corresponding group of simulation state snapshots of the set of modules under test when the marked group of modules start simulation, but does not include a corresponding simulation state snapshot of the set of modules under test when unmarked modules in the set of modules under test start simulation.
In some embodiments, determining that the modified module under test satisfies a predetermined condition further comprises: determining that the modified module under test is included in the marked set of modules.
In some embodiments, identifying one or more modified files corresponding to the modified model comprises identifying the one or more modified files based on at least one of: the modification time of the file; and a file-specific hash value.
The principles and details of the simulation circuit are described above with reference to fig. 1-5. It should be understood that the above-described processes 200 and 500 are exemplary only and are not to be construed as limiting the scope of the present disclosure.
Examples of the inventionApparatus and device
Fig. 6 shows a block diagram of an apparatus 600 for simulating a circuit according to an embodiment of the disclosure, the apparatus 600 may comprise a plurality of modules for performing the corresponding steps in the processes 200 and 500 as discussed in fig. 2 and 5. As shown in fig. 6, the apparatus 600 includes: a first simulation unit 610 configured to determine a first simulation result of a model for characterizing the circuit, the model comprising a set of modules under test, the set of modules under test being excited by a corresponding set of test excitations. The apparatus 600 further comprises: a snapshot obtaining unit 620 configured to obtain a target simulation state snapshot of the model at the target time from the first simulation result based on identifying one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test in the modified model. The apparatus 600 further comprises: a second simulation unit 630 configured to simulate the modified model based on the target simulation state snapshot to obtain a second simulation result.
In some embodiments, snapshot obtaining unit 620 is configured to identify in the modified model one of the modified test stimulus of the set of test stimuli and the modified module under test of the set of modules under test by: identifying one or more modified files corresponding to the modified model; and determining a module under test in the one or more modified files as the modified module under test.
In some embodiments, the snapshot obtaining unit 620 is configured to: determining a first time in the model before the set of modules under test begin simulation as the target time based on identifying the modified test stimulus in the modified model and determining that the set of modules under test remain unchanged in the model and the modified model; or determining a second moment in the model at which the modified module under test begins simulation as the target moment based on identifying the modified module under test in the modified model and determining that the set of test stimuli remains unchanged in the model and the modified model, and based on determining that the modified module under test satisfies a predetermined condition associated with at least timing.
In some embodiments, snapshot obtaining unit 620 is configured to determine that the modified module under test satisfies the predetermined condition by: determining that the timing of the modified module under test remains unchanged in the model and the modified model.
In some embodiments, snapshot acquisition unit 620 is configured to determine that the timing of the modified module under test remains unchanged in the model and the modified model by: determining that the timing of the modified module under test remains unchanged in the model and the modified model based on determining that instantiation and external connectivity relationships of the modified module under test remain unchanged in the model and the modified model.
In some embodiments, snapshot obtaining unit 620 is configured to identify one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test by: identifying a modified plurality of modules under test in the set of modules under test, the modified module under test being the earliest module under test to begin simulating among the modified plurality of modules under test, and wherein the snapshot acquisition unit is configured to determine that the modified module under test satisfies the predetermined condition by: determining that a corresponding plurality of timings of the modified plurality of modules under test remain unchanged in the model and the modified model.
In some embodiments, the apparatus 600 further comprises: a module data obtaining unit configured to obtain the instantiation relationship and the external connection relationship of the modified module under test from the first simulation result for determining that the timing of the modified module under test remains unchanged in the model and the modified model.
In some embodiments, the apparatus 600 further comprises: a marking unit configured to mark a group of modules in the set of modules under test, and wherein the first simulation result includes a corresponding group of simulation state snapshots of the set of modules under test when the marked group of modules start simulation, and does not include a corresponding simulation state snapshot of the set of modules under test when unmarked modules in the set of modules under test start simulation.
In some embodiments, snapshot obtaining unit 620 is configured to determine that the modified module under test is included in the marked set of modules by: determining that the modified module under test is included in the marked set of modules.
In some embodiments, snapshot obtaining unit 620 is configured to identify the one or more modified files based on at least one of: the modification time of the file; and a file-specific hash value.
Fig. 7 illustrates a schematic block diagram of an example device 700 that may be used to implement embodiments of the present disclosure. As shown, the device 700 includes a computing unit 701, which may perform various appropriate actions and processes according to computer program instructions stored in a Random Access Memory (RAM) 703 and/or a Read Only Memory (ROM) 702, or loaded from a storage unit 708 into the RAM 703 and/or the ROM 702. In the RAM 703 and/or the ROM 702, various programs and data required for the operation of the device 700 may be further stored. The computing unit 701 and the RAM 703 and/or ROM 702 are connected to each other by a bus 704. An input/output (I/O) interface 705 is also connected to bus 704.
Various components in the device 700 are connected to the I/O interface 705, including: an input unit 706 such as a keyboard, a mouse, or the like; an output unit 707 such as various types of displays, speakers, and the like; a storage unit 708 such as a magnetic disk, optical disk, or the like; and a communication unit 709 such as a network card, modem, wireless communication transceiver, etc. The communication unit 709 allows the device 700 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.
In the above embodiments, all or part of the implementation may be realized by software, hardware, firmware or any combination thereof, and when the implementation is realized by software, all or part of the implementation may be realized in the form of a computer program product. The computer program product comprises one or more computer program instructions which, when loaded and executed on a server or terminal, cause the processes or functions described in accordance with embodiments of the application to be performed, in whole or in part. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (e.g., coaxial cable, fiber optics, digital subscriber line) or wirelessly (e.g., infrared, wireless, microwave, etc.). The computer readable storage medium can be any available medium that can be accessed by a server or a terminal or a data storage device, such as a server, a data center, etc., that includes one or more of the available media. The usable medium may be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape, etc.), an optical medium (such as a Digital Video Disk (DVD), etc.), or a semiconductor medium (such as a solid state disk, etc.).
Further, while operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Claims (23)
1. A method for simulating a circuit, comprising:
determining a first simulation result of a model for characterizing a circuit, the model comprising a set of modules under test, the set of modules under test being excited by a corresponding set of test excitations;
based on identifying one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test in the modified model, obtaining a target simulation state snapshot of the model at a target time from the first simulation result; and
simulating the modified model based on the target simulation state snapshot to obtain a second simulation result.
2. The method of claim 1, wherein identifying in the modified model one of a modified test stimulus in the set of test stimuli and a modified module under test in the set of modules under test comprises:
identifying one or more modified files corresponding to the modified model; and
determining a module under test in the one or more modified files as the modified module under test.
3. The method of claim 1 or 2, wherein obtaining the target simulation state snapshot from the first simulation result based on identifying in the modified model one of a modified test stimulus in the set of test stimuli and a modified module under test in the set of modules under test comprises:
determining a first time in the model before the set of modules under test begin simulation as the target time based on identifying the modified test stimulus in the modified model and determining that the set of modules under test remains unchanged in the model and the modified model; or
Determining a second time instant in the model at which the modified module under test begins simulation as the target time instant based on identifying the modified module under test in the modified model and determining that the set of test stimuli remains unchanged in the model and the modified model, and based on determining that the modified module under test satisfies a predetermined condition associated with at least timing.
4. The method of claim 3, wherein determining that the modified module under test satisfies the predetermined condition comprises:
determining that the timing of the modified module under test remains unchanged in the model and the modified model.
5. The method of claim 4, wherein determining that timing of the modified module under test remains unchanged in the model and the modified model comprises:
determining that the timing of the modified module under test remains unchanged in the model and the modified model based on determining that instantiation and external connectivity relationships of the modified module under test remain unchanged in the model and the modified model.
6. The method according to any one of claims 3 to 5,
wherein identifying one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test comprises identifying a modified plurality of modules under test in the set of modules under test that was the earliest to begin simulation among the modified plurality of modules under test, and
wherein determining that the modified module under test satisfies the predetermined condition comprises determining that a corresponding plurality of timings of the modified plurality of modules under test remain unchanged in the model and the modified model.
7. The method of claim 5 or 6, further comprising:
obtaining the instantiation relationship and the external connection relationship of the modified module under test from the first simulation result for determining that the timing of the modified module under test remains unchanged in the model and the modified model.
8. The method of any of claims 3 to 7, further comprising marking a set of modules in the set of modules under test, and wherein the first simulation result comprises a corresponding set of simulation state snapshots of the set of modules under test when the marked set of modules begin simulation and does not comprise a corresponding simulation state snapshot of the set of modules under test when unmarked modules begin simulation in the set of modules under test.
9. The method of claim 8, wherein determining that the modified module under test satisfies a predetermined condition further comprises:
determining that the modified module under test is included in the marked set of modules.
10. The method of any of claims 2 to 9, wherein identifying one or more modified files corresponding to the modified model comprises identifying the one or more modified files based on at least one of:
the modification time of the file; and
a file-specific hash value.
11. An apparatus for simulating a circuit, comprising:
a first simulation unit configured to determine a first simulation result of a model for characterizing a circuit, the model comprising a set of modules under test excited by a corresponding set of test excitations;
a snapshot obtaining unit configured to obtain a target simulation state snapshot of the model at a target time from the first simulation result based on identifying one of a modified test stimulus in the set of test stimuli and a modified module under test in the set of modules under test in the modified model; and
a second simulation unit configured to simulate the modified model based on the target simulation state snapshot to obtain a second simulation result.
12. The apparatus of claim 11, wherein the snapshot acquisition unit is configured to identify one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test in the modified model by:
identifying one or more modified files corresponding to the modified model; and
determining a module under test in the one or more modified files as the modified module under test.
13. The apparatus according to claim 11 or 12, wherein the snapshot obtaining unit is configured to:
determining a first time in the model before the set of modules under test begin simulation as the target time based on identifying the modified test stimulus in the modified model and determining that the set of modules under test remains unchanged in the model and the modified model; or alternatively
Determining a second time instant in the model at which the modified module under test begins simulation as the target time instant based on identifying the modified module under test in the modified model and determining that the set of test stimuli remains unchanged in the model and the modified model, and based on determining that the modified module under test satisfies a predetermined condition associated with at least timing.
14. The apparatus of claim 13, wherein the snapshot obtaining unit is configured to determine that the modified module under test satisfies the predetermined condition by:
determining that the timing of the modified module under test remains unchanged in the model and the modified model.
15. The apparatus of claim 14, wherein the snapshot acquisition unit is configured to determine that the timing of the modified module under test remains unchanged in the model and the modified model by:
determining that the timing of the modified module under test remains unchanged in the model and the modified model based on determining that an instantiation relationship and an external connection relationship of the modified module under test remain unchanged in the model and the modified model.
16. The apparatus of any one of claims 13 to 15,
wherein the snapshot acquisition unit is configured to identify one of the modified test stimulus in the set of test stimuli and the modified module under test in the set of modules under test by: identifying a modified plurality of modules under test in the set of modules under test, the modified modules under test being the ones of the modified plurality of modules under test that began the simulation earliest, and
wherein the snapshot obtaining unit is configured to determine that the modified module under test satisfies the predetermined condition by: determining that a corresponding plurality of timings of the modified plurality of modules under test remain unchanged in the model and the modified model.
17. The apparatus of claim 15 or 16, further comprising:
a module data obtaining unit configured to obtain the instantiation relationship and the external connection relationship of the modified module under test from the first simulation result for determining that the timing of the modified module under test remains unchanged in the model and the modified model.
18. The apparatus of any of claims 13 to 17, further comprising:
a marking unit configured to mark a group of modules in the set of modules under test, and wherein the first simulation result includes a corresponding group of simulation state snapshots of the set of modules under test when the marked group of modules start simulation, and does not include a corresponding simulation state snapshot of the set of modules under test when unmarked modules in the set of modules under test start simulation.
19. The apparatus of claim 18, wherein the snapshot obtaining unit is configured to determine that the modified module under test is included in the marked set of modules by:
determining that the modified module under test is included in the marked set of modules.
20. The apparatus according to any of claims 12 to 19, wherein the snapshot obtaining unit is configured to identify the one or more modified files based on at least one of:
the modification time of the file; and
a file-specific hash value.
21. An electronic device, comprising:
at least one computing unit;
at least one memory coupled to the at least one computing unit and storing instructions for execution by the at least one computing unit, the instructions when executed by the at least one computing unit, cause the electronic device to perform the method of any of claims 1-10.
22. A computer-readable storage medium, on which a computer program is stored which, when being executed by a processor, carries out the method according to any one of claims 1-10.
23. A computer program product comprising computer executable instructions, wherein the computer executable instructions, when executed by a processor, implement the method according to any one of claims 1-10.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116244482A (en) * | 2023-05-09 | 2023-06-09 | 北京芯愿景软件技术股份有限公司 | Circuit simulation display method and device |
| CN116992804A (en) * | 2023-09-26 | 2023-11-03 | 深圳鲲云信息科技有限公司 | Chip verification method and computing device |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN116244482A (en) * | 2023-05-09 | 2023-06-09 | 北京芯愿景软件技术股份有限公司 | Circuit simulation display method and device |
| CN116244482B (en) * | 2023-05-09 | 2023-10-13 | 北京芯愿景软件技术股份有限公司 | Circuit simulation display method and device |
| CN116992804A (en) * | 2023-09-26 | 2023-11-03 | 深圳鲲云信息科技有限公司 | Chip verification method and computing device |
| CN116992804B (en) * | 2023-09-26 | 2024-01-05 | 深圳鲲云信息科技有限公司 | Chip verification method and computing device |
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