CN116243558A - Photoetching method based on thick photoresist application, LED chip and manufacturing method thereof - Google Patents

Photoetching method based on thick photoresist application, LED chip and manufacturing method thereof Download PDF

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Publication number
CN116243558A
CN116243558A CN202310245841.8A CN202310245841A CN116243558A CN 116243558 A CN116243558 A CN 116243558A CN 202310245841 A CN202310245841 A CN 202310245841A CN 116243558 A CN116243558 A CN 116243558A
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layer
etching
led chip
positive photoresist
substrate
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刘伟
刘伟文
曹衍灿
邬新根
刘英策
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Xiamen Changelight Co Ltd
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Xiamen Changelight Co Ltd
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0035—Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
    • H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
    • H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005—Processes
    • H01L33/0093—Wafer bonding; Removal of the growth substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Abstract

The invention provides a photoetching method based on thick photoresist application, an LED chip and a manufacturing method thereof, which weaken the Poisson facula influence of pattern crossing points through weak exposure when the thick photoresist is applied, avoid pattern distortion and cancel SiO in the subsequent etching process 2 The production cost is greatly reduced by a metal hard mask process; and through the cyclic operation of low-temperature curing and developing, the uniformity of the thick photoresist and the uniformity of the line width after developing are improved. Further, ICP etching is performed by taking the aluminum disc as a bearing disc, so that the structure to be etched forms the preset structureThe aluminum bearing plate with low use cost, strong plasticity and higher heat conduction performance can well solve the problems of poor heat conduction performance and low etching rate of the traditional silicon carbide bearing plate due to the arrangement of the graph; thereby greatly improving productivity and effectively reducing manufacturing cost.

Description

Photoetching method based on thick photoresist application, LED chip and manufacturing method thereof
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a photoetching method based on thick photoresist application, an LED chip and a manufacturing method thereof.
Background
With the continuous development of semiconductor light emitting technology, the application of LEDs is more and more varied, and particularly, the development of LEDs in display technology is advanced. Meanwhile, due to the high resolution requirement of the LED display screen, the distance between LED chips and the size of the chips are also smaller and smaller, such as Mi n i-LEDs and other micro-light emitting devices.
The LED is a semiconductor device for converting electric energy into light energy, and is widely used in the fields of lighting, display, backlight, etc. because of its advantages of small size, long lifetime, rich colors, low energy consumption, etc. Mi n i-LED is used as a sub-millimeter light-emitting diode, the size of the Mi n i-LED is generally 80-200 um, the Mi n i-LED is a new generation of l ed technology, the Mi n i-LED has the characteristics of high efficiency, high reliability, high brightness and quick response time of small-spacing LEDs, and the power consumption and the cost of the small-spacing LEDs are lower; however, as the chip size is reduced, the channel ratio is higher and higher, which directly affects the light emitting area of the chip, and thus, it is highly desirable to prepare an etched channel with a high aspect ratio.
In the existing manufacturing field, it is generally required to apply a thick photoresist as an etching mask layer for full exposure, and to use SiO2 or metal as a hard mask layer to avoid the influence on the epitaxial layer caused by the uncleanness of the thick photoresist development.
It should be noted that in the prior art, in different semiconductor processes, in order to adapt to the special process requirements, a thick photoresist (i.e., a thick photoresist) is usually coated for exposure in some photolithography steps; for example, in the process of 0.13um process node, it is sometimes required to coat the photoresist with a thickness of 6um or more and a thickness of 2um or less, and we define the photoresist with a thickness of more than or equal to three times the general thickness value as a "thick photoresist".
When the development rate at the exposure amount approaches the maximum value, the exposure amount is referred to as full/overexposure, and conversely, weak exposure.
However, as shown in fig. 1 and 2, the above method still has the following disadvantages:
1. by using the thick photoresist as a mask layer, the exposure energy required by the thick photoresist is extremely high, and the strong diffraction brought by the exposure energy can cause the intersection of the channels to form serious poisson light spots, and the etched poisson light spot areas are still abnormal in etching.
2. The thick photoresist is affected by the depth of the adhesive layer, and the exposure degree of the upper surface and the lower surface of the thick photoresist has obvious difference, so that after the photoresist is developed and hardened later, the sidewall of a photoresist reflow channel is very inclined, so that the width of the channel is too wide, and the light-emitting area is seriously affected.
3. SiO is adopted 2 Or the metal is used as a mask protection layer, so that the cost is high, and the process is complex.
In view of this, the present inventors have specifically devised a photolithography method based on thick photoresist application, an LED chip and a method for manufacturing the same, which results therefrom.
Disclosure of Invention
The invention aims to provide a photoetching method based on thick photoresist application, an LED chip and a manufacturing method thereof, so as to improve the etching morphology of a high aspect ratio channel.
In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:
a method of photolithography based on thick photoresist applications, comprising: providing a structure to be etched, wherein the structure to be etched comprises a semiconductor material layer; and etching the structure to be etched to form a preset pattern with an intersection, wherein the etching process comprises the following steps:
s01, forming a positive photoresist layer on the surface of the structure to be etched;
s02, forming an exposure area on the positive photoresist layer through weak exposure;
s03, curing the positive photoresist layer;
s04, developing the positive photoresist layer to remove the photoresist corresponding to the exposure area;
s05, repeatedly executing the steps S03 to S04 to form a positive photoresist layer with uniform preset patterns;
s06, taking the positive photoresist layer with the uniform preset pattern as a mask, and forming the preset pattern by etching the structure to be etched.
Preferably, the step S06 includes: and taking the positive photoresist layer with the uniform preset pattern as a mask, and performing ICP etching by taking the aluminum disc as a bearing disc to enable the structure to be etched to form the preset pattern.
Preferably, said step S03 is performed by lowering the ambient temperature to effect said curing of said positive photoresist layer.
Preferably, the multi-step etching is achieved by adjusting at least one of ICP source power, bias source power, and gas flow.
Preferably, the positive photoresist layer is scanned by a plasma prior to the multi-step etch.
Preferably, the total number of times of executing the steps S03 to S04 is n, wherein n is a positive integer, and n is more than or equal to 2; when the nth execution step S03 is performed, the corresponding ambient temperature is T n T is then n ≥T n-1 。
Preferably T n -T n-1 ≥5℃。
Preferably, the step S04 is performed at room temperature.
Preferably, the positive photoresist layer has a coefficient of thermal expansion of not more than 50 x 10 -6 /℃。
Preferably, the positive photoresist layer comprises a plurality of photoresist sublayers, and the thermal expansion coefficient of the photoresist sublayers on the top surface is not higher than 50×10 -6 /℃。
Preferably, the preset pattern comprises a channel with an intersection and an aspect ratio greater than 1.
Preferably, the thickness of the positive photoresist layer is 6 to 50um, inclusive.
Preferably, the positive photoresist layer comprises EPG-562 photoresist.
The invention also provides a manufacturing method of the LED chip, which adopts the etching method of any one of the above to form a plurality of LED light-emitting units which are mutually isolated through channels, and the LED light-emitting units are of a horizontal structure, and the manufacturing method comprises the following steps:
a01, providing a substrate;
a02, growing an epitaxial lamination layer, wherein the epitaxial lamination layer comprises a first type semiconductor layer, an active layer and a second type semiconductor layer which are sequentially stacked on the surface of the substrate;
a03, exposing part of the first semiconductor layer by etching the epitaxial lamination, so as to form a plurality of grooves and table tops, wherein the grooves are opposite to the table tops;
a04, deep etching the epitaxial lamination until the surface of the substrate is exposed by adopting the photoetching method of any one of the above steps to form a plurality of sub-epitaxial lamination which are mutually arranged at intervals through channels;
a05, manufacturing a first electrode and a second electrode, wherein the first electrode is deposited on the groove and is far away from the side wall of the groove; the second electrode is deposited on the table top, and the first electrode and the second electrode are arranged far away.
Preferably, the included angle between the channel and the epitaxial lamination is 55-90 degrees, including the end point value.
The invention also provides an LED chip comprising the LED chip with the horizontal structure, wherein the LED chip is obtained by the manufacturing method of any one of the above.
The invention also provides another manufacturing method of the LED chip, which adopts the etching method of any one of the above to form a plurality of LED light-emitting units mutually isolated through channels, wherein the LED light-emitting units are of vertical structures, and the manufacturing method comprises the following steps:
b01, providing a substrate;
b02, growing an epitaxial lamination layer, wherein the epitaxial lamination layer comprises a first type semiconductor layer, an active layer and a second type semiconductor layer which are sequentially stacked on the surface of the substrate;
b03, deeply etching the epitaxial lamination until the surface of the substrate is exposed by adopting the photoetching method of any one of the above steps to form a plurality of sub-epitaxial lamination which are mutually arranged at intervals through channels;
b04, providing a conductive substrate, and bonding the surface of the epitaxial lamination layer with the conductive substrate through a bonding layer to form a whole;
b05, stripping the substrate to expose the first semiconductor layer;
and B06, manufacturing a first electrode on the exposed surface of the first semiconductor layer.
Preferably, the included angle between the channel and the epitaxial lamination is 55-90 degrees, including the end point value.
Preferably, the LED chip is obtained by the manufacturing method of any one of the above.
According to the technical scheme, the photoetching method applied to the base Yu Houguang resistor is used for etching the structure to be etched to form a preset pattern with an intersection; firstly, forming a positive photoresist layer on the surface of a structure to be etched, secondly, after forming an exposure area on the positive photoresist layer under the weak exposure effect, curing the positive photoresist layer again, and then developing the positive photoresist layer to remove the photoresist corresponding to the exposure area; then, the curing and developing are repeatedly performed; forming a positive photoresist layer having a uniform preset pattern; and finally, taking the positive photoresist layer with the uniform preset pattern as a mask, and forming the preset pattern with the intersection by etching the structure to be etched. Therefore, when the thick photoresist is applied, the Poisson light spot influence of the pattern intersection is weakened through weak exposure, so that the S iO can be canceled in the subsequent etching process while the pattern distortion is avoided 2 The metal hard mask process greatly reduces the production cost; and through the cyclic operation of low-temperature curing and developing, the uniformity of the thick photoresist and the uniformity of the line width after developing are improved.
Further, the aluminum plate is used as a bearing plate for ICP etching, so that the structure to be etched forms the preset pattern, and the bearing plate made of aluminum has low use cost, strong plasticity and higher heat conduction performance, so that the problems of poor heat conduction performance and low etching rate of the traditional silicon carbide bearing plate can be well solved; thereby greatly improving productivity and effectively reducing manufacturing cost.
Then, by adjusting at least one of the ICP source power, the bias source power, and the gas flow rate to achieve multi-step etching, ICP etch depth uniformity and post-etch line width uniformity can be ensured.
Further, before the multi-step etching, the positive photoresist layer is scanned by plasma, so that the photoresist pattern is ensured to have no residual film and the evenness of the photoresist is improved.
Finally, the total times of executing the steps S03 to S04 is n, wherein n is a positive integer, and n is more than or equal to 2; when the nth execution step S03 is performed, the corresponding ambient temperature is T n T is then n ≥T n-1 The method comprises the steps of carrying out a first treatment on the surface of the By adjusting the curing temperature for multiple times, the side wall morphology of the photoresist can be well improved while the etching resistance of the photoresist is improved.
The invention also provides an LED chip and a manufacturing method thereof, wherein a plurality of LED light-emitting units which are mutually isolated through the channels are formed through the photoetching method, so that regular and flat channels are formed, and the risks of overlapping the grooves and the electrode grooves and affecting the performance of the LED chip are avoided; meanwhile, the problem of large inclination of the LED chip channel can be effectively solved by the photoetching method, and a channel with steep side edges is obtained, so that the size of the channel can be effectively reduced, the effective area and the light-emitting area of the LED chip can be obtained to the maximum extent, the photoetching method is particularly suitable for miniature LED chips (such as Mini/Micro-LEDs and the like), the productivity of the LED chip can be greatly improved, and the manufacturing cost can be effectively reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a topography of an LED chip after forming a cross channel by deep etching in the prior art;
FIG. 2 is a diagram of an FIB test after forming a cross channel by deep etching of an LED chip according to the prior art;
FIG. 3 is a flow chart of a photolithography method according to embodiment 1 of the present invention;
FIG. 4 is a graph showing the development rate of the EPG-562 photoresist (10 um thick) provided in example 1 of the present invention at different exposure levels;
fig. 5.1 to 5.7 are schematic structural diagrams corresponding to the method for manufacturing an LED chip according to embodiment 2 of the present invention;
fig. 6.1 to 6.7 are schematic structural diagrams corresponding to the method for manufacturing an LED chip according to embodiment 3 of the present invention;
fig. 7 is a topography of the LED chip provided in embodiment 2 after deep etching to form a trench;
FIG. 8 is a FIB test chart of the LED chip of embodiment 2 after deep etching to form a trench;
the symbols in the drawings illustrate:
l1, L2 … … Ln: a sub-epitaxial stack;
1. the semiconductor device comprises a substrate, 2, a first type semiconductor layer, 3, an active layer, 4, a second type semiconductor layer, 5.1, a groove, 5.2, a mesa, 6, a channel, 7, a transparent conductive layer, 8, an insulating layer, 9, a second electrode, 10, a first electrode, 11 and a conductive substrate.
Detailed Description
In order to make the contents of the present invention more clear, the contents of the present invention will be further described with reference to the accompanying drawings. The present invention is not limited to this specific embodiment. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Example 1
As shown in fig. 3, a lithography method based on thick photoresist application, comprising: providing a structure to be etched, wherein the structure to be etched comprises a semiconductor material layer; and etching the structure to be etched to form a preset pattern with an intersection, wherein the etching process comprises the following steps:
s01, forming a positive photoresist layer on the surface of the structure to be etched;
based on the above embodiments, in one embodiment of the present application, the positive photoresist layer comprises an EPG-562 photoresist.
Based on the above embodiments, in one embodiment of the present application, the thickness of the positive photoresist layer is 6 to 50um, including the endpoint values.
Based on the above embodiments, in one embodiment of the present application, the thermal expansion coefficient of the positive photoresist layer is not higher than 50×10 -6 /℃。
Based on the above embodiments, in one embodiment of the present application, the positive photoresist layer includes a plurality of photoresist sublayers, and the thermal expansion coefficient of the photoresist sublayers on the top surface is not higher than 50×10 -6 /℃。
S02, forming an exposure area on the positive photoresist layer through weak exposure;
when the development rate at the exposure amount approaches the maximum value, the exposure amount is referred to as full/overexposure, and conversely, weak exposure.
As shown in the schematic diagram of the development rate change of the EPG-562 photoresist (with a thickness of 10 um) under different exposure amounts in fig. 4, in one embodiment of the present application, the exposure energy corresponding to the portion with a larger gradient (i.e., within the dashed line frame) in the graph is selected based on the above embodiment.
Further, based on the EPG-562 photoresist application, the exposure energy can be selected from: the exposure energy corresponding to the thickness of each micron of photoresist is 14-17 mj/cm 2 Performing weak exposure, and accumulating the total exposure energy according to the total thickness of the photoresist; the invention is not limited in this regard.
S03, curing the positive photoresist layer to improve the flatness of the thick photoresist;
based on the above embodiments, in one embodiment of the present application, the step S03 is performed by reducing an ambient temperature to achieve the curing of the positive photoresist layer.
Based on the above embodiments, in one embodiment of the present application, the ambient temperature T1 corresponding to the first curing is preferably 20 to 100 ℃ and the curing time is 5 to 100s.
S04, developing the positive photoresist layer to remove the photoresist corresponding to the exposure area;
on the basis of the above-described embodiments, in one embodiment of the present application, the first development is performed by the developer at room temperature to perform the step S04.
The developer includes TMAH developer, TBAH developer, and the like, and the present application is not limited thereto.
S05, repeatedly executing the steps S03 to S04 to form a positive photoresist layer with uniform preset patterns;
based on the above embodiments, in one embodiment of the present application, the total number of times of executing steps S03 to S04 is n, where n is a positive integer, and n is greater than or equal to 2; when the nth execution step S03 is performed, the corresponding ambient temperature is T n T is then n ≥T n-1 。
Based on the above embodiments, in one embodiment of the present application, T n -T n-1 ≥5℃。
Based on the above embodiments, in one embodiment of the present application, the ambient temperature T2 corresponding to the second curing is preferably 50 to 120 ℃ and the curing time is 10 to 100s. And after the second solidification, cooled to room temperature to perform the second development. The developer used for the second development may be the same as or different from the developer corresponding to the first development, and the present application is not limited thereto.
Note that, the specific range of the number n is not limited in this embodiment; similarly, the curing temperatures corresponding to the nth curing of the third curing and the fourth curing … … are T n -T n-1 The operation is performed at 5 ℃ or more, which is not limited in this embodiment.
S06, taking the positive photoresist layer with the uniform preset pattern as a mask, and forming the preset pattern by etching the structure to be etched.
On the basis of the above embodiment, in one embodiment of the present application, the step S06 includes: and taking the positive photoresist layer with the uniform preset pattern as a mask, and performing ICP etching by taking the aluminum disc as a bearing disc to enable the structure to be etched to form the preset pattern.
Based on the above embodiments, in one embodiment of the present application, the multi-step etching is implemented by adjusting at least one of ICP source power, bias source power, and gas flow rate during ICP etching.
Based on the above embodiments, in one embodiment of the present application, the positive photoresist layer is scanned by a plasma prior to the multi-step etch.
Note that the number of etching steps is not limited in this embodiment. In one embodiment of the present application, the multi-step etching is achieved by adjusting the upper electrode power, the lower electrode power, and the gas flow rate in the ICP etching process, specifically, the etching step includes 2 steps of etching:
first, by the method of the first step of adding a catalyst to the catalyst at O 2 Performing plasma scanning on the positive photoresist layer in Ar atmosphere; then, the first etching is performed with an upper electrode power of 800 to 1800W, an upper electrode power of 100 to 700W, and a gas flow rate of 100 to 250 sccm.
Second, by Cl 2 /BCl 3 And performing the second deep etching by using gas, wherein the power of the upper electrode is 800-1800W, the power of the upper electrode is 300-800W, and the gas flow is not less than 200sccm.
On the basis of the above embodiment, in one embodiment of the present application, the preset pattern includes a channel 6 having an intersection and an aspect ratio greater than 1.
According to the technical scheme, the photoetching method applied to the base Yu Houguang resistor is used for etching the structure to be etched to form a preset pattern with an intersection; firstly, forming a positive photoresist layer on the surface of a structure to be etched, secondly, after forming an exposure area on the positive photoresist layer under the weak exposure effect, curing the positive photoresist layer again, and then developing the positive photoresist layer to remove the photoresist corresponding to the exposure area; then, the curing and developing are repeatedly performed; to form a uniform preset patternA positive photoresist layer in the shape; and finally, taking the positive photoresist layer with the uniform preset pattern as a mask, and forming the preset pattern with the intersection by etching the structure to be etched. Therefore, when the thick photoresist is applied, the Poisson light spot influence of the pattern intersection is weakened through weak exposure, so that the S iO can be canceled in the subsequent etching process while the pattern distortion is avoided 2 The metal hard mask process greatly reduces the production cost; and through the cyclic operation of low-temperature curing and developing, the uniformity of the thick photoresist and the uniformity of the line width after developing are improved.
Further, the aluminum plate is used as a bearing plate for ICP etching, so that the structure to be etched forms the preset pattern, and the bearing plate made of aluminum has low use cost, strong plasticity and higher heat conduction performance, so that the problems of poor heat conduction performance and low etching rate of the traditional silicon carbide bearing plate can be well solved; thereby greatly improving productivity and effectively reducing manufacturing cost.
Then, by adjusting at least one of the ICP source power, the bias source power, and the gas flow rate to achieve multi-step etching, ICP etch depth uniformity and post-etch line width uniformity can be ensured.
Further, before the multi-step etching, the positive photoresist layer is scanned by plasma, so that the photoresist pattern is ensured to have no residual film and the evenness of the photoresist is improved.
Finally, repeatedly executing the steps S03 to S04 for n times, wherein n is a positive integer, and n is more than or equal to 2; when the nth execution step S03 is performed, the corresponding ambient temperature is T n T is then n ＞T n-1 The method comprises the steps of carrying out a first treatment on the surface of the By adjusting the curing temperature for multiple times, the side wall morphology of the photoresist can be well improved while the etching resistance of the photoresist is improved.
Example 2
The embodiment of the invention also provides a manufacturing method of the LED chip, which adopts the etching method described in the embodiment 1 to form a plurality of LED light-emitting units mutually isolated through the channels 6, wherein the LED light-emitting units are of a horizontal structure, and the manufacturing method comprises the following steps:
a01, as shown in FIG. 5.1, a substrate 1 is provided;
a02, as shown in FIG. 5.2, growing an epitaxial stack comprising a first type semiconductor layer 2, an active layer 3 and a second type semiconductor layer 4 stacked in sequence on the surface of the substrate 1;
a03, as shown in fig. 5.3, etching the epitaxial lamination to expose part of the first semiconductor layer 2, thereby forming a plurality of grooves 5.1 and a table top 5.2, wherein the grooves 5.1 are opposite to the table top 5.2;
a04, as shown in fig. 5.4, deep etching the epitaxial lamination to expose the surface of the substrate 1 by adopting the photoetching method described in any one of the above steps to form a plurality of sub-epitaxial lamination which are mutually arranged at intervals through the channels 6;
for ease of illustration, fig. 5.4 illustrates only 2 sub-epitaxial stacks (L1, L2), which may be included in the thousands of sub-epitaxial stacks during actual fabrication of the product, as the case may be, and this is not limiting in this application.
A05, as shown in fig. 5.7, manufacturing a first electrode 10 and a second electrode 9, wherein the first electrode 10 is deposited on the groove 5.1 and is far away from the side wall of the groove 5.1; the second electrode 9 is deposited on the mesa 5.2 and the first electrode 10 and the second electrode 9 are arranged remotely.
Before the first electrode 10 and the second electrode 9 are fabricated, as shown in fig. 5.5, the transparent conductive layer 7 may be fabricated on the mesa 5.2 to serve as a current spreading; next, as shown in fig. 5.6, an insulating layer 8 is fabricated on the sidewall of the epitaxial stack to serve as an insulating protection and/or mirror for the electrode and the sidewall; this embodiment is not limited thereto.
Based on the above embodiments, in one embodiment of the present application, the included angle between the channel 6 and the epitaxial layer stack is 55 ° to 90 °, including the end point value.
The embodiment of the invention also provides an LED chip which comprises the LED chip with the horizontal structure, and the LED chip is obtained by the manufacturing method of any one of the above.
The embodiment of the invention also provides an LED chip and a manufacturing method thereof, wherein a plurality of LED light-emitting units which are mutually isolated through the channels 6 are formed by the photoetching method described in the embodiment 1, and as shown in fig. 7 and 8, regular and flat channels 6 are formed, so that the risks of overlapping the channels and the electrode grooves 5.1 and affecting the performance of the LED chip are avoided; meanwhile, the problem of large inclination of the LED chip channel 6 can be effectively solved by the photoetching method, and the channel 6 with steep side edges is obtained, so that the size of the channel 6 can be effectively reduced, the effective area and the light-emitting area of the LED chip can be obtained to the maximum extent, the photoetching method is particularly suitable for miniature LED chips (such as Mini/Micro-LEDs and the like), the productivity of the LED chip can be greatly improved, and the manufacturing cost can be effectively reduced.
Example 3
The embodiment of the invention also provides another manufacturing method of an LED chip, which adopts the etching method described in the embodiment 1 to form a plurality of LED light-emitting units mutually isolated through the channel 6, wherein the LED light-emitting units are of a vertical structure, and the manufacturing method comprises the following steps:
b01, as shown in FIG. 6.1, a substrate 1 is provided;
b02, as shown in fig. 6.2, growing an epitaxial stack comprising a first type semiconductor layer 2, an active layer 3 and a second type semiconductor layer 4 stacked in order on the surface of the substrate 1;
b03, as shown in fig. 6.3, deep etching the epitaxial stack layer to expose the surface of the substrate 1 by adopting the photolithography method described in any one of the above, so as to form a plurality of sub epitaxial stack layers which are mutually arranged at intervals through the channels 6;
for ease of illustration, fig. 6.3 illustrates only 3 sub-epitaxial stacks (L1, L2, L3), which may be included in the thousands of sub-epitaxial stacks during actual fabrication of the product, as the case may be, and this is not limiting in this application.
B04, as shown in fig. 6.4 and 6.5, providing a conductive substrate 11, and bonding the conductive substrate 11 to form a whole on the surface of the epitaxial lamination through a bonding layer;
b05, as shown in fig. 6.6, peeling off the substrate 1 to expose the first semiconductor layer 2;
as shown in fig. 6.7, a first electrode 10 is formed on the exposed surface of the first type semiconductor layer 2.
In this embodiment, the conductive substrate 11 may be used as the second electrode 9 of the LED chip to be in contact with the outside.
Based on the above embodiments, in one embodiment of the present application, the included angle between the channel 6 and the epitaxial layer stack is 55 ° to 90 °, including the end point value.
On the basis of the above embodiments, in one embodiment of the present application, the LED chip is obtained by the manufacturing method described in any one of the above.
The embodiment of the invention also provides an LED chip and a manufacturing method thereof, wherein a plurality of LED light-emitting units which are mutually isolated through the channels 6 are formed by the photoetching method in the embodiment 1, so that the regular and flat channels 6 are formed, and the risks of overlapping the channels and the electrodes and affecting the performance of the LED chip are avoided; meanwhile, the problem of large inclination of the LED chip channel 6 can be effectively solved by the photoetching method, and the channel 6 with steep side edges is obtained, so that the size of the channel 6 can be effectively reduced, the effective area and the light-emitting area of the LED chip can be obtained to the maximum extent, the photoetching method is particularly suitable for miniature LED chips (such as Mi n i/M micro-LEDs and the like), the productivity can be greatly improved, and the manufacturing cost can be effectively reduced.
In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or apparatus that comprises such element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (18)

1. A method of photolithography based on thick photoresist applications, comprising: providing a structure to be etched, wherein the structure to be etched comprises a semiconductor material layer; and etching the structure to be etched to form a preset pattern with an intersection, wherein the etching process comprises the following steps:
s01, forming a positive photoresist layer on the surface of the structure to be etched;
s02, forming an exposure area on the positive photoresist layer through weak exposure;
s03, curing the positive photoresist layer;
s04, developing the positive photoresist layer to remove the photoresist corresponding to the exposure area;
s05, repeatedly executing the steps S03 to S04 to form a positive photoresist layer with uniform preset patterns;
s06, taking the positive photoresist layer with the uniform preset pattern as a mask, and forming the preset pattern by etching the structure to be etched.
2. The method of claim 1, wherein said step S06 comprises: and taking the positive photoresist layer with the uniform preset pattern as a mask, and performing ICP etching by taking the aluminum disc as a bearing disc to enable the structure to be etched to form the preset pattern.
3. The method of claim 1, wherein said step S03 is performed by lowering the ambient temperature to effect said curing of said positive photoresist layer.
4. The method of claim 2, wherein the multi-step etching is performed by adjusting at least one of upper electrode power, lower electrode power, and gas flow during the ICP etching.
5. The method of claim 1, wherein the total number of times steps S03 through S04 are performed is n, wherein n is a positive integer and n is equal to or greater than 2; when the nth execution step S03 is performed, the corresponding ambient temperature is T n T is then n ≥T n-1 。
6. A method of photolithography for substrate Yu Houguang resist according to claim 5, wherein T n -T n-1 ≥5℃。
7. The method of claim 1, wherein said step S04 is performed at room temperature.
8. The method of claim 1, wherein the positive photoresist layer has a coefficient of thermal expansion of not more than 50 x 10 -6 /℃。
9. The method of claim 1, wherein the positive photoresist layer comprises a plurality of photoresist sub-layers, and the top surface of the photoresist sub-layers has a thermal expansion coefficient not higher than 50 x 10 -6 /℃。
10. The method of claim 1, wherein the predetermined pattern comprises a trench having an intersection and an aspect ratio greater than 1.
11. A method of lithographically applying the substrate Yu Houguang resist of claim 1, wherein the positive photoresist layer has a thickness of from 6 to 50um, inclusive.
12. A method of photolithography for substrate Yu Houguang resist application according to claim 1 wherein the positive photoresist layer comprises EPG-562 photoresist.
13. A method for manufacturing an LED chip, characterized in that a plurality of LED light emitting units isolated from each other by a trench are formed by using the etching method according to any one of claims 1 to 12, and the LED light emitting units are of a horizontal structure, the method comprising the steps of:
a01, providing a substrate;
a02, growing an epitaxial lamination layer, wherein the epitaxial lamination layer comprises a first type semiconductor layer, an active layer and a second type semiconductor layer which are sequentially stacked on the surface of the substrate;
a03, exposing part of the first semiconductor layer by etching the epitaxial lamination, so as to form a plurality of grooves and table tops, wherein the grooves are opposite to the table tops;
a04, deep etching the epitaxial lamination to expose the surface of the substrate by adopting the photoetching method of any one of claims 1 to 12 to form a plurality of sub-epitaxial lamination which are mutually arranged at intervals through channels;
a05, manufacturing a first electrode and a second electrode, wherein the first electrode is deposited on the groove and is far away from the side wall of the groove; the second electrode is deposited on the table top, and the first electrode and the second electrode are arranged far away.
14. The method of claim 13, wherein the channel and the epitaxial layer stack have an included angle of 55 ° to 90 °, inclusive.
15. An LED chip comprising a horizontal structure LED chip, characterized in that the LED chip is obtained by the manufacturing method according to any one of claims 13 to 14.
16. A method for manufacturing an LED chip, characterized in that a plurality of LED light emitting units isolated from each other by a trench are formed by using the etching method according to any one of claims 1 to 12, and the LED light emitting units are of a vertical structure, the method comprising the steps of:
b01, providing a substrate;
b02, growing an epitaxial lamination layer, wherein the epitaxial lamination layer comprises a first type semiconductor layer, an active layer and a second type semiconductor layer which are sequentially stacked on the surface of the substrate;
b03, deep etching the epitaxial lamination to expose the surface of the substrate by adopting the photoetching method of any one of claims 1 to 12 to form a plurality of sub-epitaxial lamination which are mutually arranged at intervals through channels;
b04, providing a conductive substrate, and bonding the surface of the epitaxial lamination layer with the conductive substrate through a bonding layer to form a whole;
b05, stripping the substrate to expose the first semiconductor layer;
and B06, manufacturing a first electrode on the exposed surface of the first semiconductor layer.
17. The method of claim 16, wherein the channel and the epitaxial layer stack have an included angle of 55 ° to 90 °, inclusive.
18. An LED chip comprises an LED chip with a vertical structure; characterized in that the LED chip is obtained by the manufacturing method according to any one of claims 16 to 17.
CN202310245841.8A 2023-03-15 2023-03-15 Photoetching method based on thick photoresist application, LED chip and manufacturing method thereof Pending CN116243558A (en)

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