CN116232323A - Signal conditioning circuit and data processing method - Google Patents
Signal conditioning circuit and data processing method Download PDFInfo
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- CN116232323A CN116232323A CN202111515907.8A CN202111515907A CN116232323A CN 116232323 A CN116232323 A CN 116232323A CN 202111515907 A CN202111515907 A CN 202111515907A CN 116232323 A CN116232323 A CN 116232323A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
Abstract
The invention provides a signal conditioning circuit and a data processing method, which comprises a first chopper circuit, a second chopper circuit and a first switching circuit, wherein the first chopper circuit is used for receiving differential signals and carrying out chopper processing on the differential signals based on first switching signals; the modulator is connected to the output end of the first chopper circuit and is used for shaping noise and outputting a first digital signal; the decimation filter is connected with the output end of the modulator, samples the one-bit digital signal output by the modulator and outputs a second digital signal with sign bits; the second chopper circuit is connected with the output end of the decimation filter and is used for chopping the second digital signal based on the second switching signal; the data processing circuit is connected to the output end of the second chopper circuit and is used for averaging the data output by the second chopper circuit. The signal conditioning circuit adopts the chopper circuit, so that the offset voltage of the signal conditioning circuit is effectively reduced, and the effective bit number of digital-to-analog conversion is increased.
Description
Technical Field
The invention relates to the field of signal conditioning circuits of high-precision sensors, in particular to a signal conditioning circuit and a data processing method.
Background
With the development of IC technology, an integrated high-precision sensor with digital function output is an important trend, and the integrated sensor mainly comprises a sensor and a signal conditioning circuit, wherein the sensor is used for detecting signals such as temperature, pressure, speed, ambient light, distance and the like, changing the signals into current or voltage signals, the output signals are very weak, usually only a few millivolts, and even microvolts, and noise is also provided, and the signal conditioning circuit is used for amplifying, filtering and converting the electric signals output by the sensor into digital output signals. The common signal conditioning circuit mainly comprises a reference circuit, a signal amplifying circuit, an analog-to-digital conversion circuit, a filter circuit, a control circuit and the like, however, input offset exists in the signal amplifying circuit and an operational amplifier or a comparator in the analog-to-digital conversion circuit, and the input signal of the amplifying circuit (namely the output signal of a sensor) is very weak, so that the detection precision is affected, the signal conditioning circuit is difficult to apply to occasions with higher precision requirements, and even the actual input signal and the input offset voltage cannot be distinguished, and the detection cannot be completed.
Therefore, how to improve the current circuit to increase the detection accuracy and resolution thereof has become one of the problems to be solved by those skilled in the art.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a signal conditioning circuit and a data processing method, which are used for solving the problem of low detection accuracy of the circuit in the prior art.
To achieve the above and other related objects, the present invention provides a signal conditioning circuit comprising
A first chopper circuit that receives the differential signal and chops the differential signal based on a first switching signal;
the sigma-delta ADC modulator is connected to the output end of the first chopper circuit and is used for shaping noise and outputting a first digital signal;
a decimation filter, coupled to the output of the sigma-delta ADC modulator, for sampling the first digital signal output by the sigma-delta ADC modulator and outputting a second digital signal with sign bits;
the second chopper circuit is connected with the output end of the decimation filter and is used for carrying out chopper processing on the second digital signal based on a second switching signal; wherein the frequency of the first switching signal is the same as the frequency of the second switching signal;
and the data processing circuit is connected with the output end of the second chopper circuit and is used for averaging the data output by the second chopper circuit and outputting the averaged data.
Preferably, the frequency of the first switch signal and the frequency of the second switch signal are smaller than the refresh frequency of the decimation filter.
Preferably, the periods of the first switching signal and the second switching signal satisfy formula (1):
T CP ＝2*T ADC_CLK *n*m (1)
wherein T is CP Representing a period of the first switching signal and the second switching signal; t (T) ADC_CLK Representing a period of a clock signal of the sigma-delta ADC modulator; n represents the value of the oversampling rate; m represents the number of digital signals output by the corresponding decimation filter in 1/2 period of the first switch signal.
Preferably, the first chopper circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; the grid electrode of the first PMOS tube, the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the fourth PMOS tube are input with the first switch signal; the grid electrode of the first NMOS tube, the grid electrode of the second PMOS tube, the grid electrode of the third PMOS tube and the grid electrode of the fourth NMOS tube are used for inputting inverse signals of the first switch signals; the source electrode of the first PMOS tube, the drain electrode of the first NMOS tube, the source electrode of the second PMOS tube and the drain electrode of the second NMOS tube are connected together and used for inputting a first differential signal; the source electrode of the third PMOS tube, the drain electrode of the third NMOS tube, the source electrode of the fourth PMOS tube and the drain electrode of the fourth NMOS tube are connected together and used for inputting a second differential signal; the drain electrode of the first PMOS tube, the source electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the source electrode of the third NMOS tube are connected together and led out to form a first output end; the drain electrode of the second PMOS tube, the source electrode of the second NMOS tube, the drain electrode of the fourth PMOS tube and the source electrode of the fourth NMOS tube are connected together and led out to form a second output end.
More preferably, the first chopper circuit has the same circuit configuration as the second chopper circuit.
Preferably, the signal conditioning circuit further includes a programmable gain amplifier disposed between the first chopper circuit and the sigma-delta ADC modulator, for amplifying the chopper-processed differential signal.
More preferably, the programmable gain amplifier includes a first high gain operational amplifier, a second high gain operational amplifier, a first capacitor, a second capacitor, a first resistor, a second resistor, and a third resistor; the positive input end of the first high-gain operational amplifier is the positive input end of the programmable gain amplifier, and the positive input end of the second high-gain operational amplifier is the negative input end of the programmable gain amplifier; the first capacitor is arranged between the output end and the inverting input end of the first high-gain operational amplifier; the second capacitor is arranged between the output end and the inverting input end of the second high-gain operational amplifier; the first resistor is arranged between the inverting input end of the first high-gain operational amplifier and the inverting input end of the second high-gain operational amplifier; the second resistor is arranged between the output end and the inverting input end of the first high-gain operational amplifier; the third resistor is arranged between the inverting input end and the output end of the second high-gain operational amplifier.
More preferably, the capacitance values of the first capacitor and the second capacitor are the same.
More preferably, the sum of the resistance values of the first resistor, the second resistor and the third resistor is a certain value.
More preferably, the differential gain of the programmable gain amplifier satisfies formula (2):
wherein AV represents the differential gain of the programmable gain amplifier; r1 represents the resistance value of the first resistor; r2 represents the resistance value of the second resistor; r3 represents the resistance value of the third resistor.
More preferably, the refresh time of the decimation filter satisfies the formula (3):
T AD ＝T ADC_CLK *n (3)
wherein T is AD Representing a refresh time of the decimation filter; t (T) ADC_CLK Representing a period of a clock signal of the sigma-delta ADC modulator; n represents the value of the oversampling rate.
A data processing method, the data processing method comprising the steps of:
s1: chopping the differential signals;
s2: converting the analog signal subjected to chopper processing into the first digital signal;
s3: sampling the first digital signal to generate a second digital signal;
s4: chopping the second digital signal based on a second switching signal;
s5: the chopped signals are collected and the first b data after the rising and falling edges of the second switching signal are removed, and the remaining data is averaged, where b is a non-zero positive integer.
Preferably, step S6 further comprises: the minimum and maximum values in the remaining data are removed and then averaged.
As described above, the signal conditioning circuit and the data processing method of the present invention have the following advantages:
the signal conditioning circuit effectively reduces the offset voltage of the signal conditioning circuit by arranging the chopper circuit, can be applied to a high-precision sensor, and effectively improves the resolution of a fully-integrated sensor.
2, the signal conditioning circuit does not need to be provided with a large capacitor and a large resistor, so that the circuit is easier to integrate in the sensor.
And 3, after the signals in the signal conditioning circuit are chopped, the direction of the input signals is changed, and the accuracy of analog-to-digital conversion is not reduced.
Drawings
Fig. 1 is a schematic diagram of a signal conditioning circuit according to the present invention.
Fig. 2 is a schematic diagram of a chopper circuit according to the present invention.
Fig. 3 is a schematic diagram showing the relationship between the differential signal and the switching signal.
Fig. 4 shows a schematic diagram of a programmable gain amplifier according to the present invention.
Fig. 5 is a schematic diagram showing the relationship among the chopper switch signal, the oversampling rate, and the modulator clock signal in accordance with the present invention.
Description of element reference numerals
1. First chopper circuit
2. Programmable gain amplifier
3. Sigma-delta ADC modulator
4. Decimation filter
5. Second chopper circuit
6. Data processing circuit
S1 to S5 steps
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.
Please refer to fig. 1-5. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.
Example 1
The present embodiment provides a signal conditioning circuit including a first chopper circuit 1, a programmable gain amplifier 2, a sigma-delta ADC modulator 3, a decimation filter 4, a second chopper circuit 5, and a data processing circuit 6.
As shown in fig. 1, the first chopper circuit 1 receives a differential signal, and performs a chopping process on the input differential signal based on a first switching signal CP 1.
Specifically, the differential signals include a first differential signal VINP and a second differential signal VINN, which constitute a differential relationship. When the first switching signal CP1 is at the first level, the first differential signal VINP is output to the non-inverting input terminal of the programmable gain amplifier 2 through chopping, and the second differential signal VINN is output to the inverting input terminal of the programmable gain amplifier 2 through chopping. When the first switching signal CP1 is at the second level, the first differential signal VINP is output to the inverting input terminal of the programmable gain amplifier 2 through the chopping process, and the second differential signal VINN is output to the non-inverting input terminal of the programmable gain amplifier 2 through the chopping process. Wherein the first level is a high level and the second level is a low level; or the first level is a low level and the second level is a high level. As shown in fig. 2 and 3, in the present embodiment, the first level is a high level CP, the first differential signal VINP is input to the non-inverting input terminal of the programmable gain amplifier 2, the second differential signal VINN is input to the inverting input terminal of the programmable gain amplifier 2, and Δv=v+ -V- =vinp-VINN. The second level is a low level cp_n, the first differential signal VINP is input to an inverting input terminal of the programmable gain amplifier 2, and the second differential signal VINN is input to a non-inverting input terminal of the programmable gain amplifier 2, Δv=v+ -V- =vinn-VINP.
More specifically, the period of the first switching signal CP1 satisfies formula (1):
T CP ＝2*T ADC_CLK *n*m (1)
wherein T is CP Representing the period of the first switching signal CP 1; t (T) ADC_CLK Representing the period of the clock signal of the sigma-delta ADC modulator 3; n represents the value of the over-sampling rate (OSR); m represents the number of digital signals output by the decimation filter 4 in 1/2 period of the first switching signal CP 1.
Specifically, as shown in fig. 2, the first chopper circuit 1 includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, and a fourth NMOS transistor MN4; the grid electrode of the first PMOS tube MP1, the grid electrode of the second NMOS tube MN2, the grid electrode of the third NMOS tube MN3 and the grid electrode of the fourth PMOS tube MP4 are connected with the low level CP_N; the grid electrode of the first NMOS tube MN1, the grid electrode of the second PMOS tube MP2, the grid electrode of the third PMOS tube MP3 and the grid electrode of the fourth NMOS tube MN4 are connected with the high level CP; the source electrode of the first PMOS transistor MP1, the drain electrode of the first NMOS transistor MN1, the source electrode of the second PMOS transistor MP2, and the drain electrode of the second NMOS transistor MN2 are connected together, and are used for inputting the first differential signal VINP; the source electrode of the third PMOS transistor MP3, the drain electrode of the third NMOS transistor MN3, the source electrode of the fourth PMOS transistor MP4, and the drain electrode of the fourth NMOS transistor MN4 are connected together, and are used for inputting the second differential signal VINN; the drain electrode of the first PMOS transistor MP1, the source electrode of the first NMOS transistor MN1, the drain electrode of the third PMOS transistor MP3, and the source electrode of the third NMOS transistor MN3 are connected together and led out as a first output terminal v+ connected to the non-inverting input terminal of the programmable gain amplifier 2; the drain electrode of the second PMOS transistor MP2, the source electrode of the second NMOS transistor MN2, the drain electrode of the fourth PMOS transistor MP4, and the source electrode of the fourth NMOS transistor MN4 are connected together and led out as a second output terminal V-connected to the inverting input terminal of the programmable gain amplifier 2.
As shown in fig. 1, the programmable gain amplifier 2 is connected to an output terminal of the first chopper circuit 1, and is configured to amplify the differential signal subjected to the chopping process.
Specifically, as shown in fig. 4, the programmable gain amplifier 2 includes a first high gain operational amplifier AMP1, a second high gain operational amplifier AMP2, a first capacitor C1, a second capacitor C2, a first resistor R1, a second resistor R2, and a third resistor R3; the non-inverting input end of the first high-gain operational amplifier AMP1 is the non-inverting input end of the programmable gain amplifier 2, and the non-inverting input end of the second high-gain operational amplifier AMP2 is the inverting input end of the programmable gain amplifier 2; the first capacitor C1 is disposed between the output terminal and the inverting input terminal of the first high-gain operational amplifier AMP 1; the second capacitor C2 is disposed between the output terminal and the inverting input terminal of the second high-gain operational amplifier AMP 2; the first resistor R1 is disposed between the inverting input terminal of the first high-gain operational amplifier AMP1 and the inverting input terminal of the second high-gain operational amplifier AMP 2; the second resistor R2 is arranged between the output end and the inverting input end of the first high-gain operational amplifier AMP 1; the third resistor R3 is disposed between the inverting input terminal and the output terminal of the second high gain operational amplifier AMP 2.
More specifically, the capacitance value of the first capacitor C1 and the second capacitor C2 is the same.
More specifically, the resistance values of the first resistor R1, the second resistor R2, and the third resistor R3 may be adjustable, so as to ensure that the sum of the resistance values of the first resistor R1, the second resistor R2, and the third resistor R3 is a certain value.
More specifically, the differential gain of the programmable gain amplifier 3 satisfies the formula (2):
wherein AV represents the differential gain of the programmable gain amplifier 3; r1 represents the resistance value of the first resistor R1; r2 represents the resistance value of the second resistor R2; r3 represents the resistance value of the third resistor R3.
It should be noted that, when the differential signal is sufficiently large, the signal conditioning circuit may not require the programmable gain amplifier 3.
As shown in fig. 1, the sigma-delta ADC modulator 3 is connected to the output of the programmable gain amplifier 2, and is configured to shape noise and output a first digital signal, where the number of bits of the first digital signal is one.
Specifically, in this embodiment, the sigma-delta ADC modulator 3 is a conventional 2-order sigma-delta modulator, and other devices and circuit structures capable of implementing noise shaping to output a digital signal are suitable for the present invention, which is not described herein in detail.
As shown in fig. 1, the decimation filter 4 is connected to the output end of the sigma-delta ADC modulator 3, and is configured to sample a one-bit digital signal output by the sigma-delta ADC modulator 3 and output a second digital signal with sign bits, where the number of bits of the second digital signal is at least one.
More specifically, the frequency of the first switching signal CP1 is smaller than the refresh frequency of the decimation filter 4.
More specifically, the refresh time of the decimation filter 4 satisfies the formula (3)
T AD ＝T ADC_CLK *n (3)
Wherein T is AD Representing a refresh time of the decimation filter; t (T) ADC_CLK Representing a period of a clock signal of the sigma-delta ADC modulator; n represents the value of the oversampling rate. The relationship among the clock signal of the sigma-delta ADC modulator 3, the decimation filter 4 and the first switching signal CP1 is shown in fig. 5, wherein the multi-bit data outputted from the decimation filter 4 is denoted as AD, and the multi-bit data outputted from the second chopper circuit is denoted as D.
The rate of data refresh of the decimation filter 4 is variable and is achieved by configuring different over-sampling rates (OSR).
As shown in fig. 1, the second chopper circuit 5 is connected to the output terminal of the decimation filter 4, and performs chopping processing on the second digital signal based on a second switching signal CP 2; wherein, the frequency of the first switching signal CP1 is the same as the frequency of the second switching signal CP 2. The invention adopts the chopper circuit to process the signals in the circuit, effectively reduces the offset voltage in the signal conditioning circuit, increases the effective bit number of the analog-to-digital conversion, can be applied to a high-precision sensor integrated circuit, and improves the resolution of the sensor.
Specifically, the first chopper circuit 1 has the same circuit structure as the second chopper circuit 5; the periods of the first switching signal CP1 and the second switching signal CP2 are the same; and are not described in detail herein.
As shown in fig. 1, the data processing circuit 6 is connected to the output end of the second chopper circuit 5, and is configured to average the data output by the second chopper circuit 5 and output the averaged data.
The signal conditioning circuit in the prior art mostly uses a low-pass filter to eliminate the offset voltage in the circuit, but the low-pass filter needs a larger resistor and is not easy to integrate, and the chopper circuit is adopted to eliminate the offset voltage, so that the offset voltage does not need a larger resistor and is easier to integrate. In addition, when the input signal is chopper-processed, the direction of the input signal is changed without degrading the accuracy of analog-to-digital conversion.
Example two
The present embodiment provides a data processing method, which is implemented based on the signal conditioning circuit in the first embodiment, and includes the following steps:
s1: and carrying out chopping treatment on the differential signals.
Specifically, the first differential signal VINP and the second differential signal VINN are input to the first chopper circuit 1, and the input differential signal is subjected to chopping processing based on the first switching signal CP 1. When the first switching signal CP1 is at a high level, the first differential signal VINP is output to the non-inverting input terminal of the programmable gain amplifier 2 after being subjected to chopping, and the second differential signal VINN is output to the inverting input terminal of the programmable gain amplifier 2 after being subjected to chopping, where Δv=v+ -V- =vinp-VINN. When the first switching signal is at a low level, the first differential signal VINP is output to the inverting input terminal of the programmable gain amplifier 2 after being subjected to chopping, and the second differential signal VINN is output to the non-inverting input terminal of the programmable gain amplifier 2 after being subjected to chopping, where Δv=v+ -v=vinn-VINP.
S2: amplifying the chopped signal.
Specifically, the programmable gain amplifier 2 amplifies the input differential signal subjected to chopper processing and outputs the amplified signal to the sigma-delta ADC modulator 3.
S3: the electrical signal processed in step S2 is converted into said first digital signal.
Specifically, the sigma-delta ADC modulator 3 converts the input differential signal into a one-bit digital signal, referred to as a first digital signal, wherein the clock signal of the sigma-delta ADC modulator 3 is adc_clk.
S4: and sampling the first digital signal to generate a second digital signal.
Specifically, the decimation filter 4 performs 1/OSR sampling processing on the first digital signal, and generates at least one signed bit second digital signal to the second chopper circuit 5.
S5: and chopping the second digital signal based on the second switching signal.
Specifically, the second chopper circuit 5 chops the second digital signal based on the second switching signal CP2 to eliminate the offset voltage.
S6: the chopped signals are collected and the first b data after the rising and falling edges of the second switching signal are removed, and the remaining data is averaged, where b is a non-zero positive integer.
As an implementation manner of the present invention, the data processing circuit 6 collects the output values in a period a (period of the second switching signal CP 2) after the chopping process, the number of the output values in 1/2 periods of the second switching signal CP2 is m, the first b data after the rising edge and the falling edge of the second switching signal CP2 do not participate in the calculation, and a is greater than or equal to 1, b is greater than or equal to 4, and in the actual calculation, the value of b can be set according to the required precision. The remaining data was averaged.
Specifically, the average value satisfies the formula (4):
wherein DOUT represents an average value of the data processing circuit outputs.
As an example, when a=1, b=4, the average value satisfies the formula (5):
as another implementation manner of the present invention, the data processing circuit 6 collects the output values in a period of a chopped periods (period of the second switching signal CP 2), the number of the output values in 1/2 periods of the second switching signal CP2 is m, the first b data after the rising edge and the falling edge of the second switching signal CP2 do not participate in the calculation, the minimum value and the maximum value in the remaining data are removed, and then an average value is obtained, wherein a is equal to or greater than 1, b is equal to or greater than 4, and in actual calculation, the value of b can be set according to the required precision.
The average value satisfies the formula (6):
wherein MAX D(x) Representing the maximum value in the remaining data; MIN (MIN) D(x`) Representing the minimum in the remaining data.
In summary, the present invention provides a signal conditioning circuit and a data processing method, including a first chopper circuit, receiving a differential signal, and performing chopper processing on the differential signal based on a first switch signal; the sigma-delta ADC modulator is connected to the output end of the first chopper circuit and is used for shaping noise and outputting a first digital signal, and the bit number of the first digital signal is one; a decimating filter, connected to the output end of the sigma-delta ADC modulator, for sampling the one-bit digital signal output by the sigma-delta ADC modulator and outputting a second digital signal with sign bits, where the number of bits of the second digital signal is at least one; the second chopper circuit is connected with the output end of the decimation filter and is used for carrying out chopper processing on the second digital signal based on a second switching signal; wherein the frequency of the first switching signal is the same as the frequency of the second switching signal; and the data processing circuit is connected with the output end of the second chopper circuit and is used for averaging the data output by the second chopper circuit and outputting the averaged data. The signal conditioning circuit effectively reduces the offset voltage of the signal conditioning circuit by arranging the chopper circuit, can be applied to a high-precision sensor, and effectively improves the resolution of a fully integrated sensor. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (13)
1. A signal conditioning circuit, the signal conditioning circuit comprising at least:
a first chopper circuit that receives the differential signal and chops the differential signal based on a first switching signal;
the sigma-delta ADC modulator is connected to the output end of the first chopper circuit and is used for shaping noise and outputting a first digital signal;
a decimation filter, coupled to the output of the sigma-delta ADC modulator, for sampling the first digital signal output by the sigma-delta ADC modulator and outputting a second digital signal with sign bits;
the second chopper circuit is connected with the output end of the decimation filter and is used for carrying out chopper processing on the second digital signal based on a second switching signal; wherein the frequency of the first switching signal is the same as the frequency of the second switching signal;
and the data processing circuit is connected with the output end of the second chopper circuit and is used for averaging the data output by the second chopper circuit and outputting the averaged data.
2. The signal conditioning circuit of claim 1, wherein: the frequency of the first switch signal and the frequency of the second switch signal are smaller than the refreshing frequency of the decimation filter.
3. The signal conditioning circuit according to claim 1 or 2, wherein: the period of the first switching signal and the second switching signal satisfies formula (1):
T CP ＝2*T ADC_CLK *n*m (1)
wherein T is CP Representing a period of the first switching signal and the second switching signal; t (T) ADC_CLK Representing a period of a clock signal of the sigma-delta ADC modulator; n represents the value of the oversampling rate; m represents the number of digital signals output by the corresponding decimation filter in 1/2 period of the first switch signal.
4. The signal conditioning circuit of claim 1, wherein: the first chopper circuit comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube and a fourth NMOS tube; the grid electrode of the first PMOS tube, the grid electrode of the second NMOS tube, the grid electrode of the third NMOS tube and the grid electrode of the fourth PMOS tube are input with the first switch signal; the grid electrode of the first NMOS tube, the grid electrode of the second PMOS tube, the grid electrode of the third PMOS tube and the grid electrode of the fourth NMOS tube are used for inputting inverse signals of the first switch signals; the source electrode of the first PMOS tube, the drain electrode of the first NMOS tube, the source electrode of the second PMOS tube and the drain electrode of the second NMOS tube are connected together and used for inputting a first differential signal; the source electrode of the third PMOS tube, the drain electrode of the third NMOS tube, the source electrode of the fourth PMOS tube and the drain electrode of the fourth NMOS tube are connected together and used for inputting a second differential signal; the drain electrode of the first PMOS tube, the source electrode of the first NMOS tube, the drain electrode of the third PMOS tube and the source electrode of the third NMOS tube are connected together and led out to form a first output end; the drain electrode of the second PMOS tube, the source electrode of the second NMOS tube, the drain electrode of the fourth PMOS tube and the source electrode of the fourth NMOS tube are connected together and led out to form a second output end.
5. The signal conditioning circuit of claim 4, wherein: the first chopper circuit and the second chopper circuit have the same circuit structure.
6. The signal conditioning circuit of claim 1, wherein: the signal conditioning circuit further comprises a programmable gain amplifier, which is arranged between the first chopper circuit and the sigma-delta ADC modulator and is used for amplifying the chopped differential signal.
7. The signal conditioning circuit of claim 6, wherein: the programmable gain amplifier comprises a first high gain operational amplifier, a second high gain operational amplifier, a first capacitor, a second capacitor, a first resistor, a second resistor and a third resistor; the positive input end of the first high-gain operational amplifier is the positive input end of the programmable gain amplifier, and the positive input end of the second high-gain operational amplifier is the negative input end of the programmable gain amplifier; the first capacitor is arranged between the output end and the inverting input end of the first high-gain operational amplifier; the second capacitor is arranged between the output end and the inverting input end of the second high-gain operational amplifier; the first resistor is arranged between the inverting input end of the first high-gain operational amplifier and the inverting input end of the second high-gain operational amplifier; the second resistor is arranged between the output end and the inverting input end of the first high-gain operational amplifier; the third resistor is arranged between the inverting input end and the output end of the second high-gain operational amplifier.
8. The signal conditioning circuit of claim 7, wherein: the capacitance values of the first capacitor and the second capacitor are the same.
9. The signal conditioning circuit of claim 7, wherein: the sum of the resistance values of the first resistor, the second resistor and the third resistor is a certain value.
10. The signal conditioning circuit of claim 7, wherein: the differential gain of the programmable gain amplifier satisfies equation (2):
wherein AV represents the differential gain of the programmable gain amplifier; r1 represents the resistance value of the first resistor; r2 represents the resistance value of the second resistor; r3 represents the resistance value of the third resistor.
11. The signal conditioning circuit of claim 10, wherein: the refresh time of the decimation filter satisfies equation (3):
T AD ＝T ADC_CLK *n (3)
wherein T is AD Representing a refresh time of the decimation filter; t (T) ADC_CLK Representing a period of a clock signal of the sigma-delta ADC modulator; n represents the value of the oversampling rate.
12. A data processing method based on a signal conditioning circuit implementation as claimed in any one of claims 1 to 11, characterized in that: the data processing method comprises the following steps:
s1: chopping the differential signals;
s2: converting the analog signal subjected to chopper processing into the first digital signal;
s3: sampling the first digital signal to generate a second digital signal;
s4: chopping the second digital signal based on a second switching signal;
s5: the chopped signals are collected and the first b data after the rising and falling edges of the second switching signal are removed, and the remaining data is averaged, where b is a non-zero positive integer.
13. The data processing method according to claim 12, wherein: step S5 further includes:
the minimum and maximum values in the remaining data are removed and then averaged.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111515907.8A CN116232323A (en) | 2021-12-02 | 2021-12-02 | Signal conditioning circuit and data processing method |
| PCT/CN2022/134019 WO2023098558A1 (en) | 2021-12-02 | 2022-11-24 | Signal conditioning circuit and data processing method |
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| CN202111515907.8A CN116232323A (en) | 2021-12-02 | 2021-12-02 | Signal conditioning circuit and data processing method |
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| CN116232323A true CN116232323A (en) | 2023-06-06 |
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| US6927717B1 (en) * | 2004-02-12 | 2005-08-09 | Linear Technology Corporation | Buffered oversampling analog-to-digital converter with improved DC offset performance |
| US7724170B2 (en) * | 2007-12-02 | 2010-05-25 | The Chinese University Of Hong Kong | Sensor interface devices and amplifiers |
| CN101394163B (en) * | 2008-10-09 | 2011-06-15 | 豪威国际控股有限公司 | Signal conditioning circuit and dual sampling-hold circuit |
| US8633843B2 (en) * | 2012-06-19 | 2014-01-21 | Infineon Technologies Ag | System and method for chopping oversampled data converters |
| CN105915219B (en) * | 2016-04-08 | 2019-07-12 | 中国科学院微电子研究所 | A kind of analog to digital conversion circuit |
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