CN116231451A - Preparation method of vertical cavity surface emitting laser and vertical cavity surface emitting laser - Google Patents
Preparation method of vertical cavity surface emitting laser and vertical cavity surface emitting laser Download PDFInfo
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Abstract
The invention relates to a preparation method of a vertical cavity surface emitting laser and the vertical cavity surface emitting laser. The method comprises the following steps: providing a first conductive semiconductor layer and an active layer which are sequentially stacked; epitaxially growing a first semiconductor material on the active layer and reducing the conductivity of the first semiconductor material to form a current injection barrier layer; etching a current injection hole with a preset size on the current injection blocking layer, wherein the current injection hole penetrates through the current injection blocking layer to expose the upper surface of the active layer; forming a current injection layer on the current injection blocking layer, wherein the current injection layer fills the current injection hole of the current injection blocking layer; and forming a second conductive semiconductor layer on the current injection layer. The preparation method of the vertical cavity surface emitting laser and the vertical cavity surface emitting laser provided by the invention improve the reliability of the VCSEL array device.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and in particular, to a method for manufacturing a vertical cavity surface emitting laser and a vertical cavity surface emitting laser.
Background
A Vertical-Cavity Surface-Emitting Laser (VCSEL) is a semiconductor whose Laser light is emitted perpendicularly to the top Surface, unlike an edge-Emitting Laser light which is emitted from the edge, typically in a separate chip process of dicing. Moreover, VCSELs have outstanding advantages in terms of threshold current, lifetime, large array integration, etc.
The oxidation limiting structure VCSEL remarkably reduces the threshold current of the device by using an oxidation limiting process, improves the current injection efficiency, and enables the VCSEL to realize stable continuous lasing. Therefore, an oxidation-limited structure VCSEL has become a mainstream in the industry, and the structure VCSEL is obtained by selectively oxidizing AlxGa1-xAs of different Al compositions with water vapor under high temperature conditions by using a wet oxidation process. However, to obtain current injection holes with a relatively uniform pore size, the uniformity of the epitaxial material and the control of the oxidation process are highly desirable. Particularly for large-sized wafers, even if strictly controlled, it is difficult to obtain current injection holes with good uniformity, for example, in VCSEL array devices of 6-inch wafers and above, the uniformity of the current injection holes formed by the oxidation process is poor, and the problem is serious. For example, poor uniformity of the current injection holes may result in different current injection densities of different current injection holes in the same VCSEL array device, such that different single-tube turn-on times or powers in the VCSEL array device may be significantly different, or even different amounts of heat may be generated, resulting in poor reliability of the entire VCSEL array device.
Disclosure of Invention
In view of this, embodiments of the present application provide a method for manufacturing a vertical cavity surface emitting laser and a vertical cavity surface emitting laser for solving at least one of the problems in the background art.
In order to achieve the above purpose, the technical scheme of the application is realized as follows:
in a first aspect, an embodiment of the present application provides a method for preparing a vertical cavity surface emitting laser, where the method includes:
providing a first conductive semiconductor layer and an active layer which are sequentially stacked;
epitaxially growing a first semiconductor material on the active layer and reducing the conductivity of the first semiconductor material to form a current injection barrier layer;
etching a current injection hole with a preset size on the current injection blocking layer, wherein the current injection hole penetrates through the current injection blocking layer to expose the upper surface of the active layer;
forming a current injection layer on the current injection blocking layer, wherein the current injection layer fills the current injection hole of the current injection blocking layer;
and forming a second conductive semiconductor layer on the current injection layer.
Optionally, the method for forming the current injection layer includes:
and epitaxially growing a second semiconductor material on the current injection blocking layer, wherein a current injection channel is formed by the part of the second semiconductor material filled in the current injection hole.
Optionally, the epitaxially growing a second semiconductor material, comprising;
setting a first growth temperature and a first growth pressure to enable a mode of growing a second semiconductor material to be a 3D mode;
setting a second growth temperature and a second growth pressure after the current injection hole is filled, so that a mode of growing a second semiconductor material is changed from a 3D mode to a 2D mode; the first growth temperature is less than the second growth temperature, and the first growth pressure is greater than the second growth pressure.
Optionally, the cross-sectional area of the current injection hole decreases in a direction approaching the current injection barrier layer.
Optionally, the refractive index of the second semiconductor material is greater than the refractive index of the first semiconductor material.
Optionally, after the epitaxially growing the second semiconductor material, the method further comprises;
epitaxially growing a third semiconductor material to form a first buffer layer; wherein the second conductive semiconductor layer is epitaxially grown along an upper surface of the first buffer layer.
Optionally, thicknesses of the current injection layer and the first buffer layer satisfy the following expression:
if the refractive index of the current injection layer is greater than the refractive index of the first buffer layer, then:
N 1 ×b＝λ/2；
if the refractive index of the current injection layer is smaller than that of the first buffer layer, then:
N 1 ×b+N 2 ×c＝λ/4；
the N is 1 B is the thickness of the current injection layer, N is the refractive index of the current injection layer 2 And c is the thickness of the first buffer layer, and lambda is the wavelength.
Optionally, the epitaxially growing a first semiconductor material on the active layer and reducing conductivity of the first semiconductor material to form a current injection barrier layer includes:
during epitaxial growth of the first semiconductor material, no doping or compensation doping is performed in the first semiconductor material to improve the insulating properties of the first semiconductor material.
Optionally, the epitaxially growing a first semiconductor material on the active layer and reducing conductivity of the first semiconductor material to form a current injection barrier layer includes:
during the epitaxial growth of the first semiconductor material, a gas containing oxygen atoms is introduced.
In a second aspect, embodiments of the present application provide a vertical cavity surface emitting laser, including:
a first conductive semiconductor layer;
an active layer stacked on the first conductive semiconductor layer;
a current injection blocking layer laminated on the upper surface of the active layer and formed with a current injection hole exposing a partial region of the upper surface of the active layer; the current injection blocking layer is made of a first semiconductor material;
the current injection layer is positioned on the current injection blocking layer and fills the current injection hole of the current injection blocking layer; and a second conductive semiconductor layer located above the current injection layer.
Optionally, the current injection layer is made of a second semiconductor material, and a portion of the second semiconductor material filled in the current injection hole forms a current injection channel.
Optionally, the cross-sectional area of the current injection hole decreases in a direction approaching the current injection barrier layer.
Optionally, the vertical cavity surface emitting laser further comprises:
a first buffer layer between the current injection layer and the second conductive semiconductor layer; the first buffer layer is composed of a third semiconductor material.
The embodiment of the application provides a preparation method of a vertical cavity surface emitting laser and the vertical cavity surface emitting laser, wherein the method comprises the steps of providing a first conductive semiconductor layer and an active layer which are sequentially laminated; epitaxially growing a first semiconductor material on the active layer and reducing the conductivity of the first semiconductor material to form a current injection barrier layer; etching a current injection hole with a preset size on the current injection blocking layer, wherein the current injection hole penetrates through the current injection blocking layer to expose the upper surface of the active layer; forming a current injection layer on the current injection blocking layer, wherein the current injection layer fills the current injection hole of the current injection blocking layer; and forming a second conductive semiconductor layer on the current injection layer. The current injection hole is formed by etching on the current injection blocking layer, and then epitaxial growth is continued after the current injection hole is formed, so that a current injection channel and a second conductive semiconductor layer are formed, the current injection hole overcomes the problem that the current injection hole formed by an oxidation process is poor in consistency in the same VCSEL array device, and the reliability of the VCSEL array device is improved. Thus, the preparation method of the vertical cavity surface emitting laser and the vertical cavity surface emitting laser provided by the embodiment of the application improve the reliability of the VCSEL array device.
Additional aspects and advantages of the application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the application.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
fig. 1 is a schematic flow chart of a method for manufacturing a vertical cavity surface emitting laser according to an embodiment of the present application;
fig. 2 to 8 are schematic cross-sectional views of various processes in the method for manufacturing a vertical cavity surface emitting laser according to the embodiment of the present application.
Reference numerals illustrate:
20. a base layer; 21. a second buffer layer; 30. a first conductive semiconductor layer; 40. an active layer; 50. a current injection barrier layer; 61. a current injection hole; 62. a current injection channel; 63. a current injection layer; 70. a first buffer layer; 80. a second conductive semiconductor layer; 90. an ohmic contact layer.
Detailed Description
Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application may be practiced without one or more of these details. In other instances, well-known features have not been described in detail so as not to obscure the application; that is, not all features of an actual implementation are described in detail herein, and well-known functions and constructions are not described in detail.
In the drawings, the size of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like numbers refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on" … …, "" adjacent to "… …," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" … …, "" directly adjacent to "… …," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application. When a second element, component, region, layer or section is discussed, it does not necessarily mean that the first element, component, region, layer or section is present in the present application.
Spatially relative terms, such as "under … …," "under … …," "below," "under … …," "above … …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under … …" and "under … …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
For a thorough understanding of the present application, detailed steps and detailed structures will be presented in the following description in order to explain the technical aspects of the present application. Preferred embodiments of the present application are described in detail below, however, the present application may have other implementations in addition to these detailed descriptions.
In view of the technical problems in the prior art, an embodiment of the present application provides a method for manufacturing a vertical cavity surface emitting laser, fig. 1 is a schematic flow diagram of the method for manufacturing a vertical cavity surface emitting laser provided in the embodiment of the present application, and fig. 2 to 8 are schematic diagrams of each process in the method for manufacturing a vertical cavity surface emitting laser provided in the embodiment of the present application, and in combination with fig. 1 to 8, the method includes:
step 101: providing a first conductive semiconductor layer 30 and an active layer 40 stacked in this order, see fig. 2;
step 102: epitaxially growing a first semiconductor material on the active layer 40 and reducing the conductivity of the first semiconductor material to form a current injection barrier layer 50, see fig. 3;
step 103: etching a current injection hole 61 having a predetermined size on the current injection blocking layer 50, the current injection hole 61 penetrating through the current injection blocking layer 50 to expose an upper surface of the active layer 40, see fig. 4;
step 104: forming a current injection layer 63 on the current injection blocking layer 50, the current injection layer 63 filling the current injection hole 61 of the current injection blocking layer 50, see fig. 5;
step 105: a second conductive semiconductor layer 80 is formed on the current injection layer 63, see fig. 6 and 7.
The preparation method of the vertical cavity surface emitting laser provided by the embodiment of the application can be used for preparing the vertical cavity surface emitting laser, and the vertical cavity surface emitting laser is mainly used as an example for description. It can be appreciated that the fabrication methods of the embodiments of the present application may also be used in the fabrication of other semiconductor devices. The preparation method of the embodiment of the application is used for forming a part of structures related to current injection, so that only the part of structures related to the current injection is shown, and other structures may be partially shown or not shown.
Illustratively, in step 101, the first conductive semiconductor layer 30 and the active layer 40 may be an N-type distributed bragg reflector (Distributed Bragg Rreflection, DBR) layer and a quantum well (quantum well) layer, respectively, for a vertical cavity surface emitting laser, and may be other layers for other types of semiconductor devices.
The first conductive semiconductor layer 30 may be an epitaxial layer (EPI) epitaxially grown on the base layer 20, for example. The first conductive semiconductor layer 30 has a first conductive type, for example, P-type or N-type. The first conductive type may be formed by doping P-type or N-type impurities in the first conductive semiconductor layer 30.
Illustratively, in step 102 and step 103, the current injection blocking layer 50 is made of an insulating material with low conductivity, and is used to enclose the current injection hole 61, and limit the current flow, so that the current flow path is more concentrated, the current is concentrated, the current density is increased, and the quantum well is excited to generate stronger laser.
Illustratively, the current injection holes 61 are etched in the current injection barrier layer 50, that is, formed by a photolithographic process. Illustratively, in order to completely remove the current injection blocking layer 50 within the current injection hole 61, an overetch of a preset depth, which may be 20 angstroms, is required.
Illustratively, in step 105, for a vertical cavity surface emitting laser, the second conductive semiconductor layer 80 may be a P-type distributed bragg reflector (Distributed Bragg Rreflection, DBR) layer.
In this embodiment, the second conductive semiconductor layer 80 is epitaxially grown after the current injection hole 61 is formed by the photolithography process, so that the problem that the current injection hole 61 formed by the oxidation process is inconsistent in the same VCSEL array device is overcome, and the reliability of the VCSEL array device is improved. Thus, the preparation method of the vertical cavity surface emitting laser provided by the embodiment of the application improves the reliability of the VCSEL array device.
Further, the preparation method of the embodiment of the application can overcome the following defects of the oxidation process:
1) The aperture shape of the current injection hole 61 formed by the oxidation process is difficult to control, so that the lateral optical field limit of the device is poor, the divergence angle is large, and the performance of the vertical cavity surface emitting laser is affected;
2) The aluminum-containing semiconductor material with high Al content is oxidized to Al 2 O 3 In the process of the process, a volume shrinkage effect can be generated, so that a cavity can be generated in the oxidized epitaxial layer, the oxide layer is easy to collapse and deform, and the device is invalid.
In some embodiments, the epitaxially growing a first semiconductor material on the active layer 40 and reducing the conductivity of the first semiconductor material to form a current injection barrier layer 50 includes:
during epitaxial growth of the first semiconductor material, no doping or compensation doping is performed in the first semiconductor material to improve the insulating properties of the first semiconductor material.
Illustratively, the first semiconductor material may be a semi-insulating material such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), gallium indium phosphide (GaInP), aluminum indium phosphide (AlInP), etc., so as to achieve the purpose of limiting current, and the first semiconductor material may be made as close to the intrinsic semiconductor as possible by comparing the molar ratios of group V and group III, so as to improve the insulation property, and further achieve the purpose of limiting current. Illustratively, the group III/V is a compound formed by group III of B, al, ga, in and V of N, P, as and Sb of the periodic table, mainly comprises gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN) and the like, and has the characteristics of higher photoelectric conversion efficiency and suitability for manufacturing photoelectric devices. In this embodiment, in a certain numerical range, the molar ratio of the group V and the group III is high, and the insulating property of the first semiconductor material can be improved. In some embodiments, the molar ratio of groups V and III in the first semiconductor material may have a value of greater than 40.
Illustratively, the MO source (metal organic source) is a high purity metal-organic compound used in the semiconductor industry due to the unavoidable introduction of the MO source during epitaxial growth of the first semiconductor material. For example, in the production of compound semiconductors such as gallium nitride and gallium arsenide, it is necessary to use volatile metal-organic compounds as raw materials, introduce the corresponding metal elements in vapor form, and deposit and grow the semiconductor material onto the substrate. The MO source contains many methyl groups (CH 3) containing carbon (C) as a dopant impurity that biases the semiconductor grown to P-conductivity, i.e., exhibits weak P-type. Thus, the insulation performance of the current injection blocking layer 50 may be lowered. Therefore, in the epitaxial growth process of the first semiconductor material, the embodiment does not dope or compensates for doping in the first semiconductor material so as to improve the insulating property of the first semiconductor material. By not doping or compensating doping, e.g. compensating silicon element, the first semiconductor material can be made as close as possible to the intrinsic semiconductor, improving the insulating properties of the current injection barrier layer 50, i.e. reducing the conductivity of the first semiconductor material.
In some embodiments, the epitaxially growing a first semiconductor material on the active layer 40 and reducing the conductivity of the first semiconductor material to form a current injection barrier layer 50 includes:
during the epitaxial growth of the first semiconductor material, a gas containing oxygen atoms is introduced.
Illustratively, as is the case for the purpose of undoped or compensating for elemental silicon. During epitaxial growth of the first semiconductor material. The oxygen atom-containing gas is introduced to improve the insulating performance of the current injection barrier layer 50. Specifically, the first semiconductor material is epitaxially grown while the gas containing oxygen atoms is continuously supplied for 5 seconds to 600 seconds. Thus, the insulating property of the first semiconductor material can be greatly improved, and the resistivity can reach more than 10-9 ohm/square meter.
In some embodiments, the method for forming the current injection layer 63 includes:
a second semiconductor material is epitaxially grown on the current injection blocking layer 50, and a current injection channel 62 is formed at a portion of the second semiconductor material filled in the current injection hole 61.
Illustratively, the second semiconductor material may be a semiconductor material that is lattice matched to the first semiconductor material, e.g., the lattice size of the second semiconductor material is relatively close to the lattice size of the first semiconductor material. This also enables the formation of a good current injection layer 63 and the formation of a good current injection channel 62 on the basis of the current injection barrier layer 50 by epitaxial growth, see fig. 5.
In some embodiments, the epitaxially growing a second semiconductor material includes;
setting a first growth temperature and a first growth pressure to enable a mode of growing a second semiconductor material to be a 3D mode;
setting a second growth temperature and a second growth pressure after the current injection hole 61 is filled, so that a mode of growing the second semiconductor material is changed from a 3D mode to a 2D mode; the first growth temperature is less than the second growth temperature, and the first growth pressure is greater than the second growth pressure.
Illustratively, the 3D mode may also be referred to as an island mode, typically growing rapidly in the machine direction, while the lateral discontinuities may be achieved by setting a relatively low growth temperature, as well as a relatively high growth pressure. Thus, for the surface of the material layer with uneven surface, for example, the upper surface of the current injection blocking layer 50 is etched with the current injection holes 61, the current injection holes 61 can be filled by rapid growth in the longitudinal direction, and the growth efficiency can be improved. The 2D mode, i.e. layer-by-layer up stacking, is typically achieved by setting a relatively high growth temperature, and a relatively low growth pressure. The upper surface of the current injection layer 63 may be made to be gradually flattened after the 3D mode is converted into the 2D mode. In addition, through the growth process of the first 3D mode and the second 2D mode, the lattice matching degree of the junction of the current injection barrier layer 50 and the current injection layer 63 can be improved, namely the problem of poor lattice matching degree of materials at the junction of the two growth steps is solved, and the growth quality of the current injection layer 63 is improved. The two times of growth are referred to as growth forming the current injection blocking layer 50 and growth forming the current injection layer 63, respectively. Illustratively, the lattice match difference may be a lattice size difference greater than 0.15%.
In some embodiments, the first growth temperature may be 450 ℃ to 600 ℃, and the first growth pressure may be 200mbar to 800mbar;
in some embodiments, the second growth temperature may be 601-800 ℃ and the second growth pressure may be 50-200 mbar.
In some embodiments, the cross-sectional area of the current injection hole 61 decreases in a direction toward the current injection barrier layer 50.
That is, the cross-sectional area of the current injection hole 61 is gradually reduced from top to bottom, so that the higher order mode of the laser light can be limited, the mode of the laser light can be maintained at the fundamental mode, the power of the vertical cavity surface emitting laser can be increased, and the divergence angle can be reduced, according to the optical correlation principle. In some embodiments, as shown in fig. 4, the shape of the current injection hole 61 may be inverted trapezoidal, i.e., the upper base of the trapezoid is below and the lower base is above. In some embodiments, the base angle of the base of the lower base of the trapezoid is 10 ° -70 °.
In some embodiments, the refractive index of the second semiconductor material is greater than the refractive index of the first semiconductor material.
Illustratively, the second semiconductor material may be a material having a refractive index greater than that of the first semiconductor material in any combination of gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), aluminum gallium arsenide phosphide (AlGaAsP), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), aluminum indium phosphide (AlInP), indium aluminum arsenide (inaias), indium phosphide (InP), and group iii/v compound semiconductor materials. The current injection hole 61 formed by the high refractive index material can well limit the light field distribution, reduce the divergence angle and facilitate the generation of stronger laser. In some embodiments, the refractive index of the second semiconductor material may be: 3.4 to 3.7.
In some embodiments, after the epitaxially growing the second semiconductor material, the method further comprises;
epitaxially growing a third semiconductor material to form a first buffer layer 70; wherein the second conductive semiconductor layer 80 is epitaxially grown along the upper surface of the first buffer layer 70, see fig. 6 and 7.
Illustratively, since the current injection layer 63 is subjected to the growth process of the first 3D mode and the second 2D mode, the first buffer layer 70 is formed by epitaxially growing the third semiconductor material, and then the second conductive semiconductor layer 80 is formed by epitaxially growing the third semiconductor material, so that the lattice difference between the junction of the third conductive semiconductor layer and the current injection layer 63 can be reduced, the growth quality of the second conductive semiconductor layer 80 can be improved, and the performance of the vertical cavity surface emitting laser can be further improved. Illustratively, the lattice size of the third semiconductor material may be between the lattice size of the material of the current injection layer 63 and the lattice size of the material of the third conductive semiconductor layer.
In some embodiments, prior to forming the first buffer layer 70, the method further comprises:
the current injection layer 63 is planarized.
The planarization treatment may be, for example, by introducing a certain amount of carbon tetrachloride (CCl) after the formation of the current injection layer 63 4 ) Through H 2 And CCl 4 The etching action of (a) causes the material surface to become flat. It will be appreciated that other planarization processes are also possible.
In some embodiments, the thicknesses of the current injection layer 63 and the first buffer layer 70 satisfy the following expression:
if the refractive index of the current injection layer 63 is greater than the refractive index of the first buffer layer 70, then:
N 1 ×b＝λ/2 (1)
if the refractive index of the current injection layer 63 is smaller than the refractive index of the first buffer layer 70, then:
N 1 ×b+N 2 ×c＝λ/4 (2)
the N is 1 B is the thickness of the current injection layer 63, the N is the refractive index of the current injection layer 63 2 The refractive index of the first buffer layer 70, c is the thickness of the first buffer layer 70, and λ is the wavelength.
Illustratively, by the above expressions (1) and (2), the thicknesses of the current injection layer 63 and the first buffer layer 70 may be determined. As can be appreciated, the thicknesses of the current injection layer 63 and the first buffer layer 70 are set according to expressions (1) and (2), the divergence angle can be reduced, the light concentration can be improved, and the light intensity can be enhanced.
In some embodiments, the current injection blocking layer 50 has a thickness a, and a.ltoreq.b. In this way, the light field is limited in the transverse direction and the propagation of light in the longitudinal direction is not affected. In some embodiments, 10nm < a <100nm, thus better achieving the above objective.
In some embodiments, prior to forming the first conductive semiconductor layer 30, the method further comprises:
the second buffer layer 21 is formed.
Illustratively, by the second buffer layer 21, the problem of the poor lattice matching degree between the base layer 20 and the first conductive semiconductor layer 30 can be reduced, and the growth quality of the first conductive semiconductor layer 30 can be improved.
In some embodiments, as shown in fig. 8, after forming the second conductive semiconductor layer 80, the method further comprises:
an ohmic contact layer 90 is formed.
The ohmic contact layer 90 is used for external conductive connection, which will not be described in detail.
The embodiment of the application also provides a vertical cavity surface emitting laser, as shown in fig. 8, which includes:
a first conductive semiconductor layer 30;
an active layer 40 stacked on the first conductive semiconductor layer 30;
a current injection blocking layer 50 laminated on the upper surface of the active layer 40 and formed with a current injection hole 61, the current injection hole 61 exposing a partial region of the upper surface of the active layer 40; the current injection blocking layer 50 is composed of a first semiconductor material;
a current injection layer 63 which is positioned on the current injection blocking layer 50 and fills the current injection hole 61 of the current injection blocking layer;
and a second conductive semiconductor layer 80 located above the current injection layer 63.
Illustratively, for a vertical cavity surface emitting laser, the first conductive semiconductor layer 30 and the active layer 40 may be an N-type distributed bragg reflector (Distributed Bragg Rreflection, DBR) layer and a quantum well (quantum well) layer, respectively, as well as other layers for other types of semiconductor devices.
The first conductive semiconductor layer 30 may be an epitaxial layer (EPI) epitaxially grown on the base layer 20, for example. The first conductive semiconductor layer 30 has a first conductive type, for example, P-type or N-type. The first conductive type may be formed by doping P-type or N-type impurities in the first conductive semiconductor layer 30.
Illustratively, the current injection blocking layer 50 is made of an insulating material, and is used for enclosing the current injection hole 61, limiting the current flow, concentrating the current flow path, concentrating the current, increasing the current density, and exciting the quantum well to generate stronger laser light.
Illustratively, the current injection holes 61 are etched in the current injection barrier layer 50, that is, formed by a photolithographic process. Illustratively, in order to completely remove the current injection blocking layer 50 within the current injection hole 61, an overetch of a preset depth, which may be 20 angstroms, is required.
For a vertical cavity surface emitting laser, the second conductive semiconductor layer 80 may be a P-type distributed bragg reflector (Distributed Bragg Rreflection, DBR) layer, for example.
In this embodiment, the current injection hole 61 is formed by a photolithography process, and the current injection hole 61 is formed before the second conductive semiconductor layer 80, so that the problem that the current injection hole 61 formed by an oxidation process is inconsistent in the same VCSEL array device is overcome, and the reliability of the VCSEL array device is improved. Thus, the vertical cavity surface emitting laser provided by the embodiment of the application improves the reliability of the VCSEL array device.
Further, the vertical cavity surface emitting laser of the embodiment of the application has the following advantages:
1) The control of the aperture shape of the current injection hole 61 is accurate, the lateral light field limit of the laser is good, and the performance of the vertical cavity surface emitting laser is improved;
2) The situation that the oxidation process is easy to cause the epitaxial layer to generate a cavity and the oxidation layer is easy to collapse and deform, thereby causing the failure of the device is avoided.
In some embodiments, the current injection layer 63 is composed of a second semiconductor material, and a portion of the second semiconductor material filled in the current injection hole 61 forms a current injection channel 62.
Illustratively, the second semiconductor material may be a semiconductor material that is lattice matched to the first semiconductor material, e.g., the lattice size of the second semiconductor material is relatively close to the lattice size of the first semiconductor material. Thus, the current injection channel 62 and the current injection layer 63 formed by epitaxial growth on the basis of the current injection barrier layer 50 can improve the quality of growth.
In some embodiments, the cross-sectional area of the current injection hole 61 decreases in a direction toward the current injection barrier layer 50.
That is, the cross-sectional area of the current injection hole 61 is gradually reduced from top to bottom, so that the higher order mode of the laser light can be limited, the mode of the laser light can be maintained at the fundamental mode, the power of the vertical cavity surface emitting laser can be increased, and the divergence angle can be reduced, according to the optical correlation principle. In some embodiments, the shape of the current injection hole 61 may be inverted trapezoidal, i.e., the upper base of the trapezoid is below and the lower base is above. In some embodiments, the base angle of the lower base of the trapezoid is 10 ° -70 °.
In some embodiments, the refractive index of the second semiconductor material is greater than the refractive index of the first semiconductor material.
Illustratively, the second semiconductor material may be a material having a refractive index greater than that of the first semiconductor material in any combination of gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), aluminum gallium arsenide phosphide (AlGaAsP), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), aluminum indium phosphide (AlInP), indium aluminum arsenide (inaias), indium phosphide (InP), and group iii/v compound semiconductor materials. The current injection hole 61 formed by the high refractive index material can well limit the light field distribution, reduce the divergence angle and facilitate the generation of stronger laser. In some embodiments, the refractive index of the second semiconductor material may be: 3.4 to 3.7.
In some embodiments, the vertical cavity surface emitting laser further comprises:
a first buffer layer 70, the first buffer layer 70 being located between the current injection layer 63 and the second conductive semiconductor layer 80; the first buffer layer 70 is composed of a third semiconductor material.
Illustratively, since the current injection layer 63 is subjected to the growth process of the first 3D mode and the second 2D mode, the first buffer layer 70 is formed by epitaxially growing the third semiconductor material, and then the second conductive semiconductor layer 80 is formed by epitaxially growing the third semiconductor material, so that the lattice difference between the junction of the third conductive semiconductor layer and the current injection layer 63 can be reduced, the growth quality of the second conductive semiconductor layer 80 can be improved, and the performance of the vertical cavity surface emitting laser can be further improved. Illustratively, the lattice size of the third semiconductor material may be between the lattice size of the material of the current injection layer 63 and the lattice size of the material of the third conductive semiconductor layer.
In some embodiments, the thicknesses of the current injection layer 63 and the first buffer layer 70 satisfy the following expression:
if the refractive index of the second semiconductor material is greater than the refractive index of the third semiconductor material, expression (1) is satisfied
If the refractive index of the second semiconductor material is smaller than the refractive index of the third semiconductor material, expression (2) is satisfied
The N is 1 B is the thickness of the current injection layer 63, the N is the refractive index of the second semiconductor material 2 The refractive index of the third semiconductor material, c is the thickness of the first buffer layer 70, and λ is the wavelength.
Illustratively, by the above expressions (1) and (2), the thicknesses of the current injection layer 63 and the first buffer layer 70 may be determined. As can be appreciated, the thicknesses of the current injection layer 63 and the first buffer layer 70 are set according to expressions (1) and (2), the divergence angle can be reduced, the light concentration can be improved, and the light intensity can be enhanced.
In some embodiments, the current injection blocking layer 50 has a thickness a, and a.ltoreq.b. In this way, the light field is limited in the transverse direction and the propagation of light in the longitudinal direction is not affected. In some embodiments, 10nm < a <100nm, thus better achieving the above objective.
In some embodiments, the first semiconductor material may be a semi-insulating material such as gallium arsenide (GaAs), aluminum gallium arsenide (AlGaAs), aluminum gallium indium phosphide (AlGaInP), gallium indium phosphide (GaInP), aluminum indium phosphide (AlInP), etc., so as to achieve the purpose of limiting current, and the first semiconductor material may be made as close to the intrinsic semiconductor as possible by comparing the molar ratio of V-group to III-group, so as to improve the insulation, and further achieve the purpose of limiting current. Illustratively, the group III/V is a compound formed by group III of B, al, ga, in and V of N, P, as and Sb of the periodic table, mainly comprises gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN) and the like, and has the characteristics of higher photoelectric conversion efficiency and suitability for manufacturing photoelectric devices. In this embodiment, in a certain numerical range, the molar ratio of the group V and the group III is high, and the insulating property of the first semiconductor material can be improved. In some embodiments, the molar ratio of groups V and III in the first semiconductor material may have a value of greater than 40.
It should be noted that, the embodiment of the vertical cavity surface emitting laser provided in the present application and the embodiment of the method for manufacturing the vertical cavity surface emitting laser belong to the same concept; the features of the embodiments described in the present invention may be combined arbitrarily without any conflict. However, it should be further described that, in the vertical cavity surface emitting laser provided in the embodiments of the present application, each technical feature combination may already solve the technical problem to be solved in the present application; therefore, the vertical cavity surface emitting laser provided by the embodiment of the application can be not limited by the preparation method of the vertical cavity surface emitting laser provided by the embodiment of the application, and any vertical cavity surface emitting laser prepared by the preparation method capable of forming the vertical cavity surface emitting laser structure provided by the embodiment of the application is within the scope of protection of the application.
It should be understood that the above examples are illustrative and are not intended to encompass all possible implementations encompassed by the claims. Various modifications and changes may be made in the above embodiments without departing from the scope of the disclosure. Likewise, the individual features of the above embodiments can also be combined arbitrarily to form further embodiments of the invention which may not be explicitly described. Therefore, the above examples merely represent several embodiments of the present invention and do not limit the scope of protection of the patent of the present invention.
Claims (13)
1. A method of fabricating a vertical cavity surface emitting laser, the method comprising:
providing a first conductive semiconductor layer and an active layer which are sequentially stacked;
epitaxially growing a first semiconductor material on the active layer and reducing the conductivity of the first semiconductor material to form a current injection barrier layer;
etching a current injection hole with a preset size on the current injection blocking layer, wherein the current injection hole penetrates through the current injection blocking layer to expose the upper surface of the active layer;
forming a current injection layer on the current injection blocking layer, wherein the current injection layer fills the current injection hole of the current injection blocking layer;
and forming a second conductive semiconductor layer on the current injection layer.
2. The method of manufacturing a vertical cavity surface emitting laser according to claim 1, wherein the method of forming the current injection layer comprises:
and epitaxially growing a second semiconductor material on the current injection blocking layer, wherein a current injection channel is formed by the part of the second semiconductor material filled in the current injection hole.
3. The method of fabricating a vertical cavity surface emitting laser according to claim 2, wherein epitaxially growing the second semiconductor material comprises;
setting a first growth temperature and a first growth pressure to enable a mode of growing a second semiconductor material to be a 3D mode;
setting a second growth temperature and a second growth pressure after the current injection hole is filled, so that a mode of growing a second semiconductor material is changed from a 3D mode to a 2D mode; the first growth temperature is less than the second growth temperature, and the first growth pressure is greater than the second growth pressure.
4. The method of manufacturing a vertical cavity surface emitting laser according to claim 2, wherein a cross-sectional area of the current injection hole decreases in a direction approaching the current injection blocking layer.
5. The method of manufacturing a vertical cavity surface emitting laser according to claim 2, wherein a refractive index of the second semiconductor material is larger than a refractive index of the first semiconductor material.
6. The method of any one of claims 2-5, wherein after epitaxially growing the second semiconductor material, the method further comprises;
epitaxially growing a third semiconductor material to form a first buffer layer; wherein the second conductive semiconductor layer is epitaxially grown along an upper surface of the first buffer layer.
7. The method of manufacturing a vertical cavity surface emitting laser according to claim 6, wherein thicknesses of the current injection layer and the first buffer layer satisfy the following expression:
if the refractive index of the current injection layer is greater than the refractive index of the first buffer layer, then:
N 1 ×b＝λ/2；
if the refractive index of the current injection layer is smaller than that of the first buffer layer, then:
N 1 ×b+N 2 ×c＝λ/4；
the N is 1 B is the thickness of the current injection layer, N is the refractive index of the current injection layer 2 And c is the thickness of the first buffer layer, and lambda is the wavelength.
8. The method of claim 1, wherein epitaxially growing a first semiconductor material on the active layer and reducing conductivity of the first semiconductor material to form a current injection barrier layer, comprises:
during epitaxial growth of the first semiconductor material, no doping or compensation doping is performed in the first semiconductor material to improve the insulating properties of the first semiconductor material.
9. The method of claim 1, wherein epitaxially growing a first semiconductor material on the active layer and reducing conductivity of the first semiconductor material to form a current injection barrier layer, comprises:
during the epitaxial growth of the first semiconductor material, a gas containing oxygen atoms is introduced.
10. A vertical cavity surface emitting laser, comprising:
a first conductive semiconductor layer;
an active layer stacked on the first conductive semiconductor layer;
a current injection blocking layer laminated on the upper surface of the active layer and formed with a current injection hole exposing a partial region of the upper surface of the active layer; the current injection blocking layer is made of a first semiconductor material;
the current injection layer is positioned on the current injection blocking layer and fills the current injection hole of the current injection blocking layer; and a second conductive semiconductor layer located above the current injection layer.
11. The vcl laser of claim 10, wherein the current injection layer is formed of a second semiconductor material, and a portion of the second semiconductor material filled in the current injection hole forms a current injection channel.
12. The vcl as defined in claim 10, wherein the cross-sectional area of the current injection hole decreases in a direction toward the current injection barrier layer.
13. The vcl as defined in claim 10, wherein the vcl further comprises:
a first buffer layer between the current injection layer and the second conductive semiconductor layer; the first buffer layer is composed of a third semiconductor material.
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