CN116230761A - Two-dimensional reconfigurable transistor, preparation method thereof and regulation and control method - Google Patents
Two-dimensional reconfigurable transistor, preparation method thereof and regulation and control method Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
Abstract
The invention provides a two-dimensional reconfigurable transistor and a preparation method and a regulation method thereof, wherein the transistor comprises an insulating substrate, a source electrode, a bottom gate dielectric layer, a two-dimensional semiconductor layer, a top gate dielectric layer, a drain electrode and a top gate electrode; the source electrode and the bottom gate electrode are positioned above the insulating substrate, the bottom gate dielectric layer covers the bottom gate electrode, the two-dimensional semiconductor layer is positioned above the bottom gate dielectric layer and is in contact with the source electrode, the top gate dielectric layer covers the two-dimensional semiconductor layer, the drain electrode is in contact with the two-dimensional semiconductor layer, and the top gate electrode is positioned above the top gate dielectric layer and is not in contact with the drain electrode. When the two-dimensional reconfigurable transistor regulated by the vertical double grid voltage is applied to a future integrated circuit, a large number of transistors can be saved under the same calculation force condition, the occupied area of the integrated circuit is reduced, the cost of the integrated circuit and the whole energy consumption are reduced, and the development requirements of applications such as artificial intelligence, the Internet of things and the like in the future are met.
Description
Technical Field
The invention relates to the technical field of two-dimensional semiconductor materials, in particular to a two-dimensional reconfigurable transistor, a preparation method thereof and a regulation and control method thereof.
Background
With the vigorous development of the emerging electronic application industries such as artificial intelligence, big data, edge computing and the like, the requirement for efficient information processing is urgent, and a possible solution is provided by a reconfigurable technology capable of remarkably improving the utilization rate of electronic elements. However, once the conventional silicon-based field effect transistor is successfully manufactured, the conventional silicon-based field effect transistor only has single electrical characteristics (N type/P type), the field effect characteristics of the conventional silicon-based field effect transistor cannot be dynamically converted through electrical operation, a large amount of transistor resources are consumed to construct a complex circuit structure, reconfigurable high-efficiency computing capacity can be obtained, and the overall occupied area and power consumption of the circuit are increased. Therefore, there is a need to develop new reconfigurable technologies to reduce the number of transistors necessary for functional modules and to achieve more efficient computing power.
The two-dimensional semiconductor material is one of the promising basic electronic materials in the post-molar age due to the band gap adjustability, atomic-level thickness and the lack of dangling bonds. Different from the traditional scheme, the two-dimensional material has unique upper and lower double-surface channel layered transportation characteristics, namely the 'one person can live two persons' can be realized by simultaneously applying grid control voltages on the upper and lower surfaces of the channel of a single transistor, the redundancy of functional circuits is reduced, the utilization efficiency of the transistor is improved, and higher integration density is realized. In addition, the unique bipolar field effect characteristic and the controllable polarity change characteristic of the grid voltage of the two-dimensional material enable a single two-dimensional transistor to realize various switching characteristics under voltage operation, and the application potential of the two-dimensional transistor in the field of reconfigurable technology is shown. However, there is currently no report on the two-dimensional reconfigurable transistor obtained by vertical double gate voltage operation.
Disclosure of Invention
In order to solve the technical problems, the invention provides a two-dimensional reconfigurable transistor, a preparation method and a regulation method thereof, and the polarity of source contact and drain contact is independently controlled through upper and lower double grids to obtain various switching characteristics such as a P-type field effect transistor, an N-type field effect transistor, a forward bias diode, a reverse bias diode and the like. The preparation method provided by the invention avoids the problem of unstable polarity of materials caused by chemical doping, physical doping, defect regulation and other means, and provides a novel way for constructing the reconfigurable transistor with simple, convenient and feasible, lossless and reversible high area efficiency.
To achieve the above object, the present invention provides a two-dimensional reconfigurable transistor including:
an insulating substrate, a source electrode, a bottom gate dielectric layer, a two-dimensional semiconductor layer, a top gate dielectric layer, a drain electrode and a top gate electrode; the source electrode and the bottom gate electrode are located above the insulating substrate, the bottom gate dielectric layer covers the bottom gate electrode and is not in contact with the source electrode, the two-dimensional semiconductor layer is located above the bottom gate dielectric layer and is in contact with the source electrode, the top gate dielectric layer covers the two-dimensional semiconductor layer, the drain electrode is in contact with the two-dimensional semiconductor layer, and the top gate electrode is located above the top gate dielectric layer and is not in contact with the drain electrode.
Preferably, the two-dimensional semiconductor layer is made of a two-dimensional layered material with bipolar field effect characteristics, and the thickness of the two-dimensional semiconductor layer is 2-10nm.
Preferably, the insulating substrate is a silicon wafer with an oxide layer, flexible insulating PET or sapphire substrate.
Preferably, the materials of the source electrode, the bottom gate electrode, the drain electrode and the top gate electrode comprise metal electrode materials and two-dimensional semi-metal materials, the thickness is 20-50nm, the materials of the bottom gate dielectric layer and the top gate dielectric layer adopt two-dimensional lamellar boron nitride, silicon oxide, aluminum oxide or hafnium oxide, and the thickness is 20-40nm.
In order to achieve the above object, the present invention also provides a method for manufacturing a two-dimensional reconfigurable transistor, comprising:
depositing source and bottom gate electrodes based on an insulating substrate;
depositing a bottom gate dielectric layer on the bottom gate electrode to complete the whole coverage;
placing a two-dimensional semiconductor layer above the bottom gate dielectric layer and in direct contact with the source electrode;
depositing a top gate dielectric layer over the two-dimensional semiconductor layer for partial coverage;
and depositing a top gate electrode above the top gate dielectric layer, and depositing a drain electrode above the two-dimensional semiconductor layer which is not covered by the top gate dielectric layer, thereby completing the preparation of the two-dimensional reconfigurable transistor regulated and controlled by the vertical double gate electrode.
Preferably, the process of performing the deposition comprises:
patterning treatment is carried out by using an electron beam exposure process or an ultraviolet exposure process, and then deposition is completed by using a thermal evaporation process.
Preferably, the total or partial coverage of the dielectric layer is based on an atomic deposition process.
Preferably, a dry transfer process is employed when the two-dimensional semiconductor layer is disposed over the bottom gate dielectric layer.
In order to achieve the above object, the present invention further provides a method for controlling a two-dimensional reconfigurable transistor, including:
when the two-dimensional reconfigurable transistor operates, the drain electrode provides bias voltage for the voltage application end, the source electrode is grounded, and the combination mode of the gate electrode comprises the following steps: the bottom gate electrode and the top gate electrode apply positive voltages, the bottom gate electrode and the top gate electrode apply negative voltages, the bottom gate electrode applies positive voltages and the top gate electrode applies negative voltages, the bottom gate electrode applies negative voltages and the top gate electrode applies positive voltages;
electrons flow from the source to the drain and holes flow from the drain to the source when a positive voltage is applied to the drain; when a negative voltage is applied to the source, electrons flow from the drain to the source, and holes flow from the source to the drain;
if positive voltage is applied to the bottom gate electrode, the drain electrode is in N-type contact, so that hole transmission is blocked; if negative voltage is applied to the bottom gate electrode, the drain electrode is in P-type contact to block electron transmission;
if the top gate electrode applies a positive voltage, the source electrode appears as an N-type contact; if the top gate electrode applies a negative voltage, the source electrode behaves as a P-type contact.
Compared with the prior art, the invention has the following advantages and technical effects:
when the two-dimensional reconfigurable transistor regulated by the vertical double grid voltage is applied to a future integrated circuit, a large number of transistors can be saved under the same calculation force condition, the occupied area of the integrated circuit is reduced, the cost of the integrated circuit and the whole energy consumption are reduced, and the development requirements of applications such as artificial intelligence, the Internet of things and the like in the future are met;
the two-dimensional reconfigurable transistor with the vertical double-grid voltage regulation and control provides a new design scheme for a digital circuit with an entirely new architecture, realizes 'the activity of one person to a plurality of persons', can greatly reduce the consumption of transistor resources, and is beneficial to the miniaturization of future electronic products;
the preparation method provided by the invention is compatible with the existing semiconductor technology and has universality.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application, illustrate and explain the application and are not to be construed as limiting the application. In the drawings:
FIG. 1 is a schematic diagram of a two-dimensional reconfigurable transistor with vertical dual-gate voltage regulation according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an energy band of a source-drain metal in contact with a tungsten diselenide channel material under positive and negative bias conditions when positive voltages are applied to both bottom and top gate electrodes in an embodiment of the present invention;
FIG. 3 is a schematic diagram of an energy band of a source-drain metal in contact with a tungsten diselenide channel material under positive and negative bias conditions when negative voltages are applied to both bottom and top gate electrodes in an embodiment of the present invention;
FIG. 4 is a schematic diagram of the energy band of the source/drain metal in contact with the tungsten diselenide channel material under positive and negative bias conditions when a positive voltage is applied to the bottom gate electrode and a negative voltage is applied to the top gate electrode according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the energy band of the source/drain metal in contact with the tungsten diselenide channel material under positive and negative bias conditions when a negative voltage is applied to the bottom gate electrode and a positive voltage is applied to the top gate electrode according to an embodiment of the present invention;
FIG. 6 is a graph showing the voltammetry characteristics of the bottom gate electrode and the top gate electrode in accordance with one embodiment of the present invention, wherein the voltages applied to the bottom gate electrode and the top gate electrode are positive, negative, positive-negative, negative-positive, and combinations thereof;
the semiconductor device comprises a substrate, a source electrode, a two-dimensional semiconductor layer, a top gate dielectric layer, a top gate electrode, a drain electrode, a bottom gate dielectric layer, a bottom gate electrode and a bottom gate electrode, wherein the substrate is 1, the substrate is 2, the source electrode, the two-dimensional semiconductor layer, the top gate dielectric layer, the top gate electrode, the drain electrode, the bottom gate dielectric layer and the bottom gate electrode are respectively arranged on the substrate and the substrate.
Detailed Description
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
It should be noted that the steps illustrated in the flowcharts of the figures may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in an order other than that illustrated herein.
The structure of the two-dimensional reconfigurable transistor is shown in fig. 1, wherein 1 is an insulating substrate, 2 is a source electrode, 3 is a two-dimensional semiconductor layer, 4 is a top gate dielectric layer, 5 is a top gate electrode, 6 is a drain electrode, 7 is a bottom gate dielectric layer, and 8 is a bottom gate electrode.
The source electrode 2 and the bottom gate electrode 8 are positioned above the insulating substrate 1, the bottom gate dielectric layer 7 only completely covers the bottom gate electrode 8, the bottom gate dielectric layer 7 is of an L-shaped structure, the long sides of the bottom gate dielectric layer 7 are respectively contacted with the two-dimensional semiconductor layer 3 and the bottom gate electrode 8, the long sides of the bottom gate dielectric layer 7 are shorter than the two-dimensional semiconductor layer 3, and the short sides of the bottom gate dielectric layer 7 are respectively contacted with the source electrode 2 and the bottom gate electrode 8; the two-dimensional semiconductor layer 3 is located above the bottom gate dielectric layer 7 and is in contact with the source electrode 2, the top gate dielectric layer 4 partially covers the two-dimensional semiconductor layer 3 and leaves a drain contact area, the drain electrode 6 is in contact with the two-dimensional semiconductor layer 3, the top gate electrode 5 is located above the top gate dielectric layer 4 and is not in contact with the drain electrode 6, the top gate dielectric layer 4 is of an L-shaped structure, long sides of the top gate electrode 5 and the two-dimensional semiconductor layer 3 are respectively in contact, and short sides of the top gate electrode 5 and the drain electrode 6 are respectively in contact. It is noted that the top gate electrode 5 does not participate in modulating the drain contact region, and the bottom gate electrode 8 does not participate in modulating the source contact region.
The embodiment provides a tungsten diselenide reconfigurable transistor with vertical double-gate voltage regulation, which comprises the following specific preparation steps:
(1) Pre-deposition of source 2 and bottom gate electrode 8: spin-coating a layer of PMMA colloid on an insulating substrate 1, drying at 180 ℃ for 1min, carrying out patterning treatment by utilizing an electron beam exposure technology, depositing a metal electrode by a thermal evaporation process, wherein the electrode material is pure gold, and completing the pre-deposition of a source electrode and a bottom gate electrode, wherein the thickness is 30nm;
(2) Deposition of bottom gate dielectric layer 7: spin-coating PMMA colloid on a substrate with a source electrode 2 and a bottom gate electrode 8, drying at 180 ℃ for 1min, carrying out patterning treatment by utilizing an electron beam alignment technology, growing a bottom gate dielectric layer 7 by an atomic layer deposition process, realizing the complete coverage of the bottom gate electrode 8, ensuring that the source electrode 2 is exposed, wherein the dielectric layer is made of hafnium oxide, and the thickness of the bottom gate dielectric layer 7 is 25nm;
(3) Preparing a few-layer tungsten diselenide nano sheet by using a mechanical stripping method: the 3M blue film adhesive tape is stuck on the tungsten diselenide crystal and is torn off slowly, a thicker multilayer tungsten diselenide sample is remained on the adhesive tape, the thickness of the tungsten diselenide sample is thinned by lightly folding for 2-3 times, a molybdenum diselenide sample master tape is obtained, the thinned tungsten diselenide master tape is lightly pressed on a silicon wafer and is torn off slowly, a few layers of tungsten diselenide nano-sheets are left on the silicon wafer, the operation is repeated for a plurality of times, boron nitride nano-sheets with different thicknesses can be obtained, and the thickness of the tungsten diselenide sample selected in the embodiment is 3nm;
(4) Assembly of the two-dimensional semiconductor layer 3: spin-coating a PPC colloid on a silicon wafer with a few layers of tungsten diselenide samples, drying at 100 ℃ for 1min to form a PPC film with the thickness of 500nm, slowly tearing off the PPC film with the tungsten diselenide samples from the silicon wafer by using a 3M adhesive tape, fixing the PPC film on a customized carrier plate with PDMS, and finally, precisely stacking the tungsten diselenide samples on the PPC film on the upper surface of a bottom gate dielectric layer 7 by using a precise transfer platform and forming contact with a source electrode 2 to complete the assembly of a two-dimensional semiconductor layer 3;
(5) Deposition of top gate dielectric layer 4: adopting the atomic layer deposition process same as that in the step (2) to grow a top gate dielectric layer 4 on the upper surface of the two-dimensional semiconductor layer 3, reserving a contact area between a drain electrode 6 and the two-dimensional semiconductor layer 3, and completing local coverage, wherein the dielectric layer is made of hafnium oxide and has a thickness of 25nm;
(6) Depositing a top gate electrode 5 and a drain electrode 6: and (3) depositing a bottom gate electrode 5 on the upper surface of the top gate dielectric layer by adopting the same process as the step (1), depositing a drain electrode 6 at the position of a drain contact area reserved above the two-dimensional semiconductor layer 3, wherein the electrode materials are pure gold, the thickness is 30nm, and finally, the preparation of the vertical double-gate voltage controlled tungsten diselenide reconfigurable transistor is completed.
When the device provided by the embodiment is in operation, the drain electrode 6 is connected with a voltage source to apply bias voltage, and the source electrode 2 is always grounded; the bottom gate electrode 8 and the top gate electrode 5 are connected with two independent voltage sources to apply gate voltages to respectively control the contact polarities of the drain electrode and the source electrode, and the method comprises the following specific regulation and control modes:
(1) When a positive bias is applied to the drain, electrons flow from the source to the drain, holes flow from the drain to the source, and the fermi level of the drain metal moves downward relative to the source metal; when negative bias is applied to the drain electrode, electrons flow from the drain electrode to the source electrode, holes flow from the source electrode to the drain electrode, and the fermi level of the drain electrode metal moves upwards relative to the source electrode metal;
(2) FIG. 2 is a schematic diagram of the energy band of a device in which source and drain metals are in contact with tungsten diselenide channel materials under positive and negative bias when positive voltages are applied to both bottom and top gate electrodes;
when positive voltages are applied to the bottom gate electrode and the top gate electrode, the source electrode and the drain electrode are in N-type contact, namely under the action of a forward electrostatic field, electron accumulation promotes the fermi level of the tungsten diselenide channel material to be close to a conduction band, reduces an electron potential barrier, increases a hole potential barrier, is beneficial to electron transmission and prevents hole transmission;
(3) FIG. 3 is a schematic diagram of the energy band of the device in contact with the tungsten diselenide channel material when negative voltages are applied to both the bottom gate electrode and the top gate electrode;
when negative voltage is applied to the bottom gate electrode and the top gate electrode, the source electrode and the drain electrode are in P-type contact, namely under the action of a negative electrostatic field, the Fermi level of the tungsten diselenide channel material is promoted to be close to a valence band by hole accumulation, a hole potential barrier is reduced, an electron potential barrier is increased, the transmission of holes is facilitated, and the transmission of electrons is blocked;
(4) FIG. 4 is a schematic diagram of the energy band of the device in which the source and drain metals are in contact with the tungsten diselenide channel material under positive and negative bias when a positive voltage is applied to the bottom gate electrode and a negative voltage is applied to the top gate electrode;
when a positive voltage is applied to the bottom gate electrode, the drain electrode is in N-type contact, namely under the action of a forward electrostatic field, electron accumulation promotes the fermi level of the tungsten diselenide channel material to be close to a valence band, reduces an electron potential barrier, increases a hole potential barrier, is beneficial to hole transmission and prevents electron transmission; when a negative voltage is applied to the top gate electrode, the source electrode is in P-type contact, namely under the action of a negative electrostatic field, the Fermi level of the tungsten diselenide channel material is driven to be close to a valence band by hole accumulation, a hole potential barrier is reduced, an electron potential barrier is increased, and the transmission of holes and electrons is prevented;
(5) FIG. 5 is a schematic diagram of the energy band of the device in contact with the tungsten diselenide channel material with the source-drain metal under positive and negative bias when a negative voltage is applied to the bottom gate electrode and a positive voltage is applied to the top gate electrode;
when negative voltage is applied to the bottom gate electrode, the drain electrode is in P-type contact, namely under the action of a negative electrostatic field, the hole accumulation promotes the fermi level of the tungsten diselenide channel material to be close to a valence band, the hole potential barrier is reduced, the electron potential barrier is increased, the transmission of holes is facilitated, and the transmission of electrons is hindered; when positive voltage is applied to the top gate electrode, the source electrode is in N-type contact, namely under the action of a forward electrostatic field, electron accumulation promotes the fermi level of the tungsten diselenide channel material to be close to a valence band, reduces an electron potential barrier, increases a hole potential barrier, is beneficial to hole transmission and prevents electron transmission.
(6) FIG. 6 is a graph of the output characteristics of the device under four combinations of positive, negative, positive-negative, negative-positive and positive voltages applied by the bottom gate electrode and the top gate electrode, showing four different switching characteristics;
according to the analysis of fig. 2-5, when positive voltages are applied to both the bottom gate electrode and the top gate electrode, the device is turned on by taking electrons as majority carriers under positive and negative bias, and the device is characterized by an N-type transistor switch characteristic; when negative voltage is applied to the bottom gate electrode and the top gate electrode, holes are used as majority carriers to conduct under the positive and negative voltages, and the switching characteristic of the P-type transistor is shown; when a positive voltage is applied to the bottom gate electrode and a negative voltage is applied to the top gate electrode, the device is non-conductive in the positive direction, and negative direction is conducted by taking holes as majority carriers, so that the switching characteristic of the reverse biased diode is shown; when a negative voltage is applied to the bottom gate electrode and a positive voltage is applied to the top gate electrode, the device is positively conducted by taking electrons as majority carriers, and is negatively non-conducted, and the device has positive bias diode switching characteristics.
The foregoing is merely a preferred embodiment of the present application, but the scope of the present application is not limited thereto, and any changes or substitutions easily conceivable by those skilled in the art within the technical scope of the present application should be covered in the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (9)
1. A two-dimensional reconfigurable transistor, comprising:
an insulating substrate (1), a source electrode (2), a bottom gate electrode (8), a bottom gate dielectric layer (7), a two-dimensional semiconductor layer (3), a top gate dielectric layer (4), a drain electrode (6) and a top gate electrode (5); wherein the source electrode (2) and the bottom gate electrode (8) are located above the insulating substrate (1), the bottom gate dielectric layer (7) covers the bottom gate electrode (8) and is not in contact with the source electrode (2), the two-dimensional semiconductor layer (3) is located above the bottom gate dielectric layer (7) and is in contact with the source electrode (2), the top gate dielectric layer (4) covers the two-dimensional semiconductor layer (3), the drain electrode (6) is in contact with the two-dimensional semiconductor layer (3), and the top gate electrode (5) is located above the top gate dielectric layer (4) and is not in contact with the drain electrode (6).
2. The two-dimensional reconfigurable transistor according to claim 1, characterized in that the two-dimensional semiconductor layer (3) is a two-dimensional layered material having bipolar field effect characteristics, the two-dimensional semiconductor layer (3) having a thickness of 2-10nm.
3. The two-dimensional reconfigurable transistor according to claim 1, characterized in that the insulating substrate (1) is a silicon wafer with an oxide layer, a flexible insulating PET or a sapphire substrate.
4. The two-dimensional reconfigurable transistor according to claim 1, wherein the materials of the source electrode (2), the bottom gate electrode (8), the drain electrode (6) and the top gate electrode (5) comprise a metal electrode material, a two-dimensional semi-metal material, and have a thickness of 20-50nm, and the materials of the bottom gate dielectric layer (7) and the top gate dielectric layer (4) adopt two-dimensional layered boron nitride, silicon oxide, aluminum oxide or hafnium oxide, and have a thickness of 20-40nm.
5. A method of fabricating a two-dimensional reconfigurable transistor, comprising:
depositing a source electrode (2) and a bottom gate electrode (8) on the basis of an insulating substrate (1);
depositing a bottom gate dielectric layer (7) on the bottom gate electrode (8) to complete the whole coverage;
-placing a two-dimensional semiconductor layer (3) over the bottom gate dielectric layer (7) and in direct contact with the source electrode (2);
depositing a top gate dielectric layer (4) over the two-dimensional semiconductor layer (3) for partial coverage;
and depositing a top gate electrode (5) above the top gate dielectric layer (4), and depositing a drain electrode (6) above the two-dimensional semiconductor layer (3) which is not covered by the top gate dielectric layer (4), thereby completing the preparation of the two-dimensional reconfigurable transistor regulated and controlled by the vertical double gate electrode.
6. The method of claim 5, wherein performing the deposition comprises:
patterning treatment is carried out by using an electron beam exposure process or an ultraviolet exposure process, and then deposition is completed by using a thermal evaporation process.
7. The method of manufacturing a two-dimensional reconfigurable transistor according to claim 5, wherein the total or partial coverage of the dielectric layer is performed based on an atomic deposition process.
8. The method of manufacturing a two-dimensional reconfigurable transistor according to claim 5, characterized in that a dry transfer process is used when the two-dimensional semiconductor layer (3) is placed over the bottom gate dielectric layer (7).
9. A method for controlling a two-dimensional reconfigurable transistor, applicable to the two-dimensional reconfigurable transistor according to any one of claims 1 to 4, comprising:
when the two-dimensional reconfigurable transistor operates, the drain electrode (6) provides bias voltage for the voltage application end, the source electrode (2) is grounded, and the combination mode of the gate electrode comprises the following steps: the bottom gate electrode (8) and the top gate electrode (5) apply positive voltages, the bottom gate electrode (8) and the top gate electrode (5) apply negative voltages, the bottom gate electrode (8) applies positive voltages and the top gate electrode (5) applies negative voltages, the bottom gate electrode (8) applies negative voltages and the top gate electrode (5) applies positive voltages;
when a positive voltage is applied to the drain electrode (6), electrons flow from the source electrode (2) to the drain electrode (6), and holes flow from the drain electrode (6) to the source electrode (2); when a negative voltage is applied to the source, electrons flow from the drain (6) to the source (2), and holes flow from the source (2) to the drain (6);
if positive voltage is applied to the bottom gate electrode (8), the drain electrode (6) is in N-type contact, so that hole transmission is blocked; if the bottom gate electrode (8) is applied with a negative voltage, the drain electrode (6) is in P-type contact, and electron transmission is blocked;
if the top gate electrode (5) is applied with a positive voltage, the source electrode (2) is in N-type contact; if the top gate electrode (5) is applied with a negative voltage, the source electrode (2) is represented as a P-type contact.
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| CN113299758A (en) * | 2021-05-24 | 2021-08-24 | 华东师范大学 | Source-drain double-doped reconfigurable field effect transistor |
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| CN103811559A (en) * | 2014-02-21 | 2014-05-21 | 苏州大学 | Thin film transistor with bipolar operating characteristics |
| CN113299758A (en) * | 2021-05-24 | 2021-08-24 | 华东师范大学 | Source-drain double-doped reconfigurable field effect transistor |
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