CN116225771A - System external monitoring reset circuit, chip, electronic equipment and related equipment - Google Patents
System external monitoring reset circuit, chip, electronic equipment and related equipment Download PDFInfo
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- CN116225771A CN116225771A CN202310512056.4A CN202310512056A CN116225771A CN 116225771 A CN116225771 A CN 116225771A CN 202310512056 A CN202310512056 A CN 202310512056A CN 116225771 A CN116225771 A CN 116225771A
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/302—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a software system
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- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The application discloses a system external monitoring reset circuit, a chip, electronic equipment and related equipment. The system external monitoring reset circuit is used for monitoring and resetting the operation of a chip with a plurality of chip domains, wherein the chip domains comprise a security domain and an application domain, and the circuit comprises: the device comprises a charging and discharging branch, a resetting branch, a first isolating switch and a second isolating switch. The charging and discharging branch circuit is connected with the monitoring output end of one or more chip domains, charges the charging and discharging capacity when the monitoring output end outputs high level, and opens a controllable switch between the charging and discharging branch circuit and the resetting branch circuit, so that the buffer capacitor of the resetting branch circuit discharges, and discharges the charging and discharging capacity when the output of the monitoring output end changes from high level to low level or no output. Therefore, when the system is powered on initially, the code burning stage or the monitoring output end of the chip domain does not have watchdog PWM output for a long time, the controllable switch is not conducted, the reset branch is not influenced, and the reset of a plurality of chip domains of the chip can be normally controlled through the reset branch.
Description
Technical Field
The application relates to the technical field of power electronics, in particular to a system external monitoring reset circuit, a chip, electronic equipment and related equipment.
Background
With the improvement of integration level of high-real-time industrial control equipment and the appearance of equipment such as intelligent cabins, the technical direction of running a single operating system on a single chip to run a plurality of operating systems on a single chip is rapidly developed. Therefore, the running states of a plurality of operating systems are required to be monitored simultaneously, and the phenomenon that the function of equipment cannot be recovered to be normal due to the fact that a certain system is blocked is avoided. At present, a scheme of performing watchdog reset when a system is abnormal is mainly adopted by a watchdog chip.
However, for a single-core single-operation system, a hardware watchdog chip is hung to reset the watchdog when the system is abnormal, and for a single-core multi-operation system, the running state of each operation system needs to be monitored, and any system abnormal needs to reset the hardware of the chip. In this regard, if an external hardware watchdog chip is configured for each operating system, the cost is multiplied. In addition, in the code burning stage, the system can not feed dogs normally, so that the system can be restarted continuously, and a complex peripheral circuit is also required to be added, so that the watchdog chip does not work in the code burning stage.
Disclosure of Invention
The embodiment of the application aims to provide a system external monitoring reset circuit, a chip, electronic equipment and related equipment.
According to a first aspect of the present application, there is provided a system external monitoring reset circuit for monitoring and resetting operation of a chip having a plurality of chip domains, the chip domains including a security domain and an application domain, the circuit comprising: the charging and discharging branch is connected with the monitoring output end of one or more chip domains, charges the charging and discharging capacity when the monitoring output end outputs PWM waves, and opens a controllable switch between the charging and discharging branch and the resetting branch to enable the buffer capacitor of the resetting branch to discharge, and discharges the charging and discharging capacity when the output of the monitoring output end changes from outputting PWM waves to outputting low level or no output; a reset branch circuit for charging the buffer capacitor when the output of the monitoring output terminal changes from outputting PWM waves to outputting low level or no output; the first isolating switch is used for isolating the influence of the charging and discharging branch on the reset branch, one end of the first isolating switch is connected with the reset branch, and the other end of the first isolating switch is connected with the reset signal input end of the chip domain; and the second isolating switch is used for isolating the influence of the reset branch on the charge and discharge branch, one end of the second isolating switch is connected with the charge and discharge branch, and the other end of the second isolating switch is connected with the reset signal input end of the chip domain.
According to an embodiment of the present application, the system external monitoring reset circuit further includes: and the push-pull circuit is connected with the monitoring output ends of the application domains of the chip and is used for synthesizing the monitoring output ends of the application domains into a path of monitoring output end signals.
According to an embodiment of the application, the system external monitoring reset circuit is used for monitoring and resetting the operation of a chip with two application domains; correspondingly, the push-pull circuit comprises: the control end of the first switching tube is connected with the monitoring output end of the first application domain of the chip, the input end of the first switching tube is connected with the ground end, and the output end of the first switching tube is connected with the input end of the charging and discharging branch circuit; the control end of the second switching tube is connected with the monitoring output end of the second application domain of the chip, the input end of the second switching tube is connected with the ground end, and the output end of the second switching tube is connected with the input end of the charging and discharging branch circuit; and one end of the pull-up resistor is connected with the second switching tube, and the other end of the pull-up resistor is connected with the power supply end.
According to an embodiment of the application, the first switching tube is an N-type MOS tube, and the second switching tube is a P-type MOS tube; correspondingly, the push-pull circuit further comprises: the first base resistor is connected between the control end of the first switching tube and the monitoring output end of the first application domain; and the second base resistor is connected between the control end of the second switching tube and the monitoring output end of the second application domain.
According to an embodiment of the present application, the charging and discharging branch includes: the charging switch is connected between the monitoring output end and the charging and discharging capacity, and charges the charging and discharging capacity when the monitoring output end outputs a high level; one end of the charging/discharging tube is connected with the charging switch, and the other end of the charging/discharging tube is grounded; a zener diode and a discharge resistor connected in parallel with the charge/discharge cell, the charge capacitor being capable of being discharged through the zener diode and the discharge resistor when the output of the monitor output terminal changes from a high level to a low level or no output; and the isolation capacitor is connected between the monitoring output end and the charge-discharge switch.
According to an embodiment of the present application, the reset branch includes: one end of the reset resistor is connected with the power supply end, and the other end of the reset resistor is connected with the buffer capacitor; one end of the buffer capacitor is connected with the reset resistor, and the other end of the buffer capacitor is grounded; correspondingly, the connection point of the first isolating switch and the reset branch is positioned between the reset resistor and the buffer capacitor.
According to a second aspect of the present application, there is also provided a chip including the above-described system external monitoring reset circuit.
According to a third aspect of the present application, there is also provided an electronic device, including the above chip.
According to a fourth aspect of the present application, there is also provided a vehicle comprising the above electronic device.
According to a fifth aspect of the present application, there is also provided a power protection device comprising the above-described electronic device.
In this application embodiment system external monitoring reset circuit, chip, electronic equipment and related equipment, system external monitoring reset circuit is used for monitoring and resetting the chip operation that has a plurality of chip fields, and the chip field includes safe domain and application domain, and this circuit is including filling the branch road, reset branch road, first isolator and second isolator. The charging and discharging branch circuit is connected with the monitoring output end of one or more chip domains, when the monitoring output end outputs a high level, the charging and discharging capacity is charged, and a controllable switch between the charging and discharging branch circuit and the resetting branch circuit is opened, so that the buffer capacitor of the resetting branch circuit discharges, and when the output of the monitoring output end is changed from the high level to the low level or no output, the charging and discharging capacity is discharged. And the reset branch circuit charges the buffer capacitor when the output of the monitoring output end is changed from high level to low level or no output is generated. The first isolating switch is used for detecting the reset voltage of the reset branch, one end of the first isolating switch is connected with the reset branch, the other end of the first isolating switch is connected with the reset signal input end of the chip domain, and when the reset voltage is larger than or equal to a first set voltage, a high level is input to the reset signal input end. The second isolating switch is used for detecting the charge-discharge voltage of the charge-discharge capacity, one end of the second isolating switch is connected with the charge-discharge branch, the other end of the second isolating switch is connected with the reset signal input end of the chip domain, and when the charge-discharge voltage is smaller than a second set voltage, a low level is input to the reset signal input end. Therefore, when the system is powered on initially, the code burning stage or the monitoring output end of the chip domain does not have watchdog PWM output for a long time, the controllable switch is not conducted, the reset branch is not influenced, and the reset of a plurality of chip domains of the chip can be normally controlled through the reset branch. The problem that the system is continuously reset due to the fact that the watchdog-free signal is adopted in the existing technical scheme of resetting by using the watchdog chip is effectively solved, and the chip system can work normally in the code burning stage, before the system is powered on initially and does not run successfully or in the period of the chip system without the watchdog-free signal such as the long-time watchdog-free signal.
It should be understood that the teachings of the present application are not required to achieve all of the above-described benefits, but rather that certain technical solutions may achieve certain technical effects, and that other embodiments of the present application may also achieve benefits not mentioned above.
Drawings
The above, as well as additional purposes, features, and advantages of exemplary embodiments of the present application will become readily apparent from the following detailed description when read in conjunction with the accompanying drawings. Several embodiments of the present application are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings, in which:
in the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.
FIG. 1 is a schematic diagram of an implementation principle of an external monitor reset circuit of a system according to an embodiment of the present application;
fig. 2 is a schematic diagram of an implementation principle of a specific application example of the external monitoring reset circuit of the system according to the embodiment of the application.
Detailed Description
The principles and spirit of the present application will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are presented merely to enable one skilled in the art to better understand and practice the present application and are not intended to limit the scope of the present application in any way. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The technical scheme of the present application is further elaborated below with reference to the drawings and specific embodiments.
Fig. 1 is a schematic diagram of an implementation principle of an external monitoring reset circuit of a system according to an embodiment of the application.
Referring to fig. 1, a system external monitor reset circuit of an embodiment of the present application is used to monitor and reset chip operation having a plurality of chip domains (shown in fig. 1 as a security domain 101 and an application domain 102), which may include the security domain 101 and the application domain 102. The external monitoring reset circuit of the system at least comprises a charging and discharging branch 103, a reset branch 104, a first isolating switch D1 and a second isolating switch D2.
The charge-discharge branch 103 is connected to a monitor output terminal of one or more chip domains, and charges the charge-discharge cell C3 when a PWM (Pulse Width Modulation ) wave is output from the monitor output terminal, and opens a controllable switch Q1 between the charge-discharge branch 103 and the reset branch 104, so that the buffer capacitor C1 of the reset branch 104 discharges, and discharges the charge-discharge cell C3 when the output of the monitor output terminal changes from outputting the PWM wave to outputting a low level or no output.
The charging and discharging branch 103 is here exemplified as being connected to the secure domain 101 of the chip. When the chip is just powered on or in the burning stage, the system running on the chip does not normally run, the monitoring output end does not output PWM waves, and if the monitoring output end is connected with the external watchdog chip in a traditional monitoring mode, a dog feeding signal cannot be normally output. For example: the clock period of the current watchdog chip is usually 1.6 seconds, but for larger systems such as a linux system or an android system running on the chip, initialization cannot be completed within 1.6 seconds. At this time, the isolation capacitor C2 can isolate the dc voltage, and thus, no matter the monitor output terminal is a constant output high or constant output low level, the charge-discharge branch 103 does not work, and the charge-discharge branch 103 cannot affect the reset signal input terminal of the chip through the second isolation switch D2. Only the reset branch 104 is now operating normally, the reset branch 104 realizing a reset of the RC (Resistor-Capacitance circuit, resistor-capacitor circuit) of the corresponding security domain 101 via the first isolating switch D1.
After the safety domain 101 works normally, the monitoring output end of the safety domain 101 outputs a PWM wave, and the PWM wave output can enable the charge-discharge branch 103 to start working, and the second isolating switch D2 keeps inputting a high level to the reset signal input end, so that the normal operation of the chip system is ensured.
Further, after the monitoring output end of the safety domain 101 works normally, a PWM wave is output, so that the charge/discharge cell C3 can be charged, and the controllable switch Q1 between the charge/discharge branch 103 and the reset branch 104 is turned on. At this time, the buffer capacitor C1 of the reset branch 104 is discharged, thereby disabling the reset circuit 104. And under the action of the first isolating switch D1, the high level of the charging and discharging branch 103 does not affect the reset branch 104.
If a system downtime or the like occurs, the monitoring output end of the safety domain 101 does not output PWM waves, and the charging and discharging branch 103 cannot maintain a high level and becomes output low level or no output. At this time, the charge/discharge cell C3 is rapidly discharged, and the reset signal input terminal is pulled down, thereby realizing the reset of the corresponding safety domain 101. Meanwhile, since the charging/discharging branch 103 no longer maintains the high level, the controllable switch Q1 is not turned on, and the power supply terminal VCC in the reset branch 104 can recharge the buffer capacitor C1 through the reset resistor R1. After the buffer capacitor C1 is charged, the reset signal input terminal is changed from low level to high level, and after the whole reset action is completed, the system running on the safety domain 101 will be operated again.
The first isolating switch D1 is configured to isolate the influence of the charging and discharging branch on the reset branch. One end of the first isolating switch D1 is connected with the reset branch 104, and the other end is connected with a reset signal input end of the chip domain.
In this embodiment of the present application, when the reset voltage of the reset branch 104 is greater than or equal to the first set voltage, the reset branch 104 inputs a high level to the reset signal input terminal.
For example, the voltage at point a in fig. 1 is defined as the reset voltage of the reset branch 104. When the security domain and the security operating system of the chip normally operate and output a PWM dog feeding signal (i.e., the PWM wave proposed in the present application), the PWM dog feeding signal is at a high level, and at this time, the charging/discharging capacity C3 is charged. The charge/discharge cell C3 receives a high level input to the reset signal input terminal via the second isolation switch D2, maintains the safety domain reset signal at the high level, and simultaneously turns on the controllable switch Q1 to discharge the electricity stored in the buffer capacitor C1.
The first set voltage and the second set voltage are set voltages determined by considering characteristics such as internal resistance and conduction voltage of components in the system external monitoring reset circuit, and the second set voltage can be set to enable the second isolation switch D2 to be turned on as long as the first set voltage is set to enable the first isolation switch D1 to be turned on. The present application is not particularly limited thereto.
The second isolating switch D2 is configured to isolate the influence of the reset branch 104 on the charge-discharge branch 103, where one end of the second isolating switch D2 is connected to the charge-discharge branch 103, and the other end is connected to the reset signal input end of the chip domain.
In this embodiment of the present application, the main function of the first isolation switch D1 and the second isolation switch D2 is to isolate the interaction between the charge-discharge circuit 103 and the reset circuit 104. For example: in the system power-on or burning stage, the reset circuit 104 sends a reset signal to the reset signal input end of the chip security domain 101 through the first isolating switch D1, so that the normal operation of the chip system is ensured. At this time, the charge/discharge circuit 103 does not operate, and the voltage of the reset circuit 104 cannot affect the charge/discharge circuit 103 by the second isolation switch D2.
In this embodiment of the present application, when the charge-discharge voltage of the charge-discharge circuit 103 is smaller than the second set voltage, a low level is input to the reset signal input terminal.
For example, the voltage at point b in fig. 1 is defined as the charge-discharge voltage of the charge-discharge vessel C3. If an abnormality occurs in the safety operation system disposed on the safety domain 101, the PWM dog feeding signal cannot be outputted, and the capacitance value of the charging/discharging capacitor C3 is small. At this time, the charge/discharge cell C3 may rapidly discharge through the discharge resistor R4 and the zener diode D5, and VCC charges the buffer capacitor C1 through the reset resistor R1, so that a low-level pulse is formed due to the discharge speed of the charge/discharge cell C3 being significantly lower than the charge speed of C1, and the reset signal is supplied to the security domain, so that the operating system operated by the chip security domain 101 is reset and restarted.
It should be noted that, the above only takes the system external monitoring reset circuit connected to the security domain 101 as an example, and a specific implementation manner of the system external monitoring reset circuit in the embodiment of the present application is described, and in an actual application process, the system external monitoring reset circuit may be configured according to a requirement.
In this embodiment of the present application, the system external monitor reset circuit of the security domain is different from the reset range of the system external monitor reset circuit of the application domain, and the system external monitor reset circuit of the security domain can reset all operating systems running, and the system external monitor reset circuit of the application domain only resets the operating systems running in the application domain. As such, the operating system running on the security domain may be responsible for critical functional operations of the device, such as: the most important protection execution part in the power protection device, the meter part of the vehicle, and the like. And if the security domain operating system is abnormal, operating the security domain reset signal to reset all the operating systems. Because of the problems in the highest security requirements of the device, it is often necessary to reset the entire operating system. When the operating system of the application domain is abnormal, the operating system of the application domain is reset, and the operating system of the security domain can continue to run.
The security domain runs a critical operation part, the probability of occurrence of a problem in the security domain is very low, but the operating system operated by the security domain is very critical, if the security domain has the problem, the meaning of keeping normal operation of the application domain is not great, therefore, the security domain can be configured with a separate system external monitoring reset circuit, and the system external monitoring reset circuit of the security domain can be configured to reset the security domain and all the application domains simultaneously.
In this embodiment of the present application, a common system external monitor reset circuit may be configured for multiple application domains of the chip, for resetting all application domains, and the application domains may independently run more than two non-secure operating systems. In an actual application scene, the application domain is a non-critical operation part for executing non-safety, and if any abnormality exists, the operation parts of the application domains can be reset, but the normal operation of the safety domain is not affected by the reset of the application domain.
However, in the practical application process, different security levels may be divided for a plurality of application domains according to requirements, for example: one or two of the plurality of application domains are configured to independently control their reset signals.
Illustrating: the power protection device is used for operating the real-time system in a safety domain, can monitor whether the state of the power grid system needs to be protected or not, and needs to be high in real-time performance and quick in response so as to avoid serious accidents such as fire disasters. But this security domain is not computationally demanding. The application domain runs non-secure operating systems that are computationally demanding, such as: the device state needs to be uploaded to a server or a camera is used for monitoring whether abnormal people enter, people face identification and other functions need to be android and the like. The application domain is not a safe operation part, the probability of the application domain to cause problems is relatively high, but the application domain crashes and does not influence the protection of the power grid, and the application domain is reset and restarted by itself, so that the protection of the security domain on the power grid system still continues to operate. Therefore, in this embodiment of the present application, both the security domain and the application domain may be reset when the security domain is reset.
In one embodiment of the present application, the charging/discharging branch 103 includes a charging switch D4, a charging/discharging capacity C3, a zener diode D5 and a discharging resistor R4 connected in parallel with the charging/discharging capacity C3, and an isolation capacitor C2.
The charging switch D4 is connected between the monitor output terminal and the charging/discharging tube C3, and charges the charging/discharging tube C3 when the monitor output terminal outputs a high level. One end of the charge/discharge vessel C3 is connected with the charge switch, and the other end is grounded. When the output of the monitor output terminal changes from high level to low level or no output, the charge/discharge cell C3 can be discharged through the zener diode D5 and the discharge resistor R4 connected in parallel with the charge/discharge cell C3. The isolation capacitor C2 is connected between the monitoring output end and the charge/discharge switch.
In an embodiment of the present application, the reset branch 104 includes a reset resistor R1 and a buffer capacitor C1. One end of the reset resistor R1 is connected with the power supply end, and the other end is connected with the buffer capacitor C1. One end of the buffer capacitor C1 is connected with the reset resistor R1, and the other end is grounded. Correspondingly, the connection point of the first isolating switch D1 and the reset branch 104 is located between the reset resistor R1 and the buffer capacitor C1.
Fig. 2 is a schematic diagram of an implementation principle of a specific application example of the external monitoring reset circuit of the system according to the embodiment of the application.
Referring to fig. 2, in this embodiment of the present application, the system external monitor reset circuit further includes a push-pull circuit (shown as Q3 and Q4 in fig. 2). The push-pull circuit is connected with the monitoring output ends of the application domains of the chip and is used for synthesizing the monitoring output ends of the application domains into a path of monitoring output end signal. The application domains of the chip are shown as the chip security domain, the application domain 1 and the application domain 2, and in practical application, the number of application domains of the chip is not limited.
Thus, the watchdog output signal 2 and the watchdog signal 3 are both output, and the two watchdog signal outputs are changed into one watchdog signal through the push-pull circuit. In the Linux operating system running on the application domain 1 and the android operating system running on the application domain 2, only one of the Linux operating system and the android operating system is halted, and the like, namely the chip application domains 1 and 2 are reset. Therefore, the simultaneous monitoring of a plurality of systems of the single chip can be realized, and the chip is reset as long as one of the systems runs, flies or crashes and the like. And the chip is prevented from being frequently reset when the system is not complete in power-on or in a burning stage.
In an embodiment of the present application, the first switching tube is an N-type MOS tube, and the second switching tube is a P-type MOS tube. Correspondingly, the push-pull circuit further comprises a first base resistor R10 and a second base resistor R9. The first base resistor is connected between the control end of the first switch tube and the monitoring output end of the first application domain. And the second base resistor R9 is connected between the control end of the second switching tube and the monitoring output end of the second application domain.
In one embodiment of the present application, the circuit is used to monitor and reset the operation of a chip having two application domains. Correspondingly, the push-pull circuit comprises a first switching tube Q3, a second switching tube Q4 and a pull-up resistor R11. The control end 1 of the first switching tube Q3 is connected to the monitoring output end of the first application domain (chip domain 1) of the chip, the input end 2 of the first switching tube is connected to the ground, and the output end 3 of the first switching tube is connected to the input end (the position where the left side of C5 in fig. 2 is connected to the first switching tube Q3 and the second switching tube Q4) of the charge-discharge branch 103. The control end of the second switching tube Q4 is connected with the monitoring output end of the second application domain of the chip, the input end of the second switching tube Q4 is connected with the ground, and the output end of the second switching tube Q4 is connected with the input end of the charging and discharging branch 103. One end of the pull-up resistor R11 is connected to the second switching transistor Q4, and the other end is connected to the power supply terminal VCC.
When the chip system is powered on initially, no watchdog PWM (pulse Width modulation) dog feeding signal is output by the chip, C3 and C6 are at low level, and at the moment, Q1 and Q2 are not conducted. R1 and C1 and R5 and C4 can reset the security domain and the application domain respectively according to the power-on time sequence required by the chip. When the chip works normally, the watchdog PWM feeding signal is not output, the reset circuit is not affected, and the chip can work normally in the code burning stage or when the watchdog PWM output is not provided for a long time. Therefore, the problem that the system is reset continuously because the dog cannot be fed before the system does not normally run in the code burning stage in the technical scheme of using the watchdog chip and the like at present is effectively solved.
Regardless of how long the time from powering up to outputting the watchdog signal, when the security domain and the secure operating system of the chip are operating normally and outputting the watchdog PWM watchdog signal, the PWM watchdog signal watchdog output 1 of the security domain is able to charge C3. C3 maintains the safety domain reset signal to be high level through D2, and simultaneously, Q1 is conducted to discharge electricity stored in C1. If an abnormality occurs in the oversafety operating system, so that the PWM watchdog signal output 1 of the security domain cannot be output, C3 is rapidly discharged through R4 and D5. Meanwhile, VCC charges C1 through R1, and because the discharging speed of C3 is obviously lower than the charging speed of C1, a low-level pulse is formed and is used as the input of a chip security domain reset signal, and the whole operating system running on the chip is reset and restarted.
When the application domain 1 or/and the application domain 2 of the chip normally operates, PWM dog feeding signals can be output at the same time. Q4 and Q3 form push-pull circuit (push-pull circuit), push-pull circuit will two paths PWM feed dog signals and synthesize a path PWM feed dog signal to charge C6 through C5, C6 charges to high level and keeps chip application domain reset signal to high level through D7, simultaneously with Q2 switch on and release electric charge in the electric capacity C4.
When the Linux operating system running in the application domain 1 or the android operating system running in the application domain 2 is abnormal, the watchdog PWM feed signal of the application domain cannot be output. At this time, C6 cannot be charged through C5. C6 discharges rapidly through R8 and D10, while Q2 is off, VCC charges C4 again through R5. Because the discharging speed of C6 is obviously slower than the charging speed of C4, a low-level pulse can be formed as the reset signal input of the application domain of the chip, and the reset and restart are carried out on the application domain part of the chip. At this time, if the security domain operating system operates normally, it continues to operate without any influence.
Other specific implementation details of the specific application example of the external monitoring reset circuit of the system in the embodiment of the present application shown in fig. 2 are similar to those of the external monitoring reset circuit of the system in the embodiment of the present application shown in fig. 1, and are not repeated here.
In this application embodiment system external monitoring reset circuit, chip, electronic equipment, vehicle and power protection equipment, system external monitoring reset circuit is arranged in monitoring and resetting the chip operation that has a plurality of chip fields, and the chip field includes safe domain and application domain, and this circuit is including filling branch road, branch road that resets, first isolator and second isolator. The charging and discharging branch circuit is connected with the monitoring output end of one or more chip domains, charges the charging and discharging capacity when the monitoring output end outputs high level, and opens a controllable switch between the charging and discharging branch circuit and the resetting branch circuit, so that the buffer capacitor of the resetting branch circuit discharges, and discharges the charging and discharging capacity when the output of the monitoring output end changes from high level to low level or no output. The reset branch charges the buffer capacitor when the output of the monitoring output terminal changes from high level to low level or no output. The first isolating switch is used for detecting the reset voltage of the reset branch, one end of the first isolating switch is connected with the reset branch, the other end of the first isolating switch is connected with the reset signal input end of the chip domain, and when the reset voltage is greater than or equal to a first set voltage, a high level is input to the reset signal input end. The second isolating switch is used for detecting the charge-discharge voltage of the charge-discharge capacity, one end of the second isolating switch is connected with the charge-discharge branch, the other end of the second isolating switch is connected with the reset signal input end of the chip domain, and when the charge-discharge voltage is smaller than the second set voltage, a low level is input to the reset signal input end. Therefore, when the system is powered on initially, the code burning stage or the monitoring output end of the chip domain does not have watchdog PWM output for a long time, the controllable switch is not conducted, the reset branch is not influenced, and the reset of a plurality of chip domains of the chip can be normally controlled through the reset branch. The problem that the system is continuously reset due to the fact that the watchdog-free signal is adopted in the existing technical scheme of resetting by using the watchdog chip is effectively solved, and the chip system can work normally in the code burning stage, before the system is powered on initially and does not run successfully or in the period of the chip system without the watchdog-free signal such as the long-time watchdog-free signal.
Similarly, based on the external monitoring reset circuit of the system, the application also provides a chip, and the chip comprises the external monitoring reset circuit of the system.
Further, based on the external monitoring reset circuit of the system, the application also provides electronic equipment, and the electronic equipment comprises the chip.
Further, based on the external monitoring reset circuit of the system, the application also provides a vehicle, and the vehicle comprises the electronic equipment.
Further, based on the external monitoring reset circuit of the system, the application also provides power protection equipment, and the power protection equipment comprises the electronic equipment.
It should be noted here that: the above description of the embodiments of the chip, the electronic device, the vehicle and the power protection device is similar to the description of the embodiment of the external monitoring reset circuit of the system shown in fig. 1 to 2, and has the similar beneficial effects as the embodiment of the external monitoring reset circuit of the system shown in fig. 1 to 2, so that the description is omitted. For technical details not disclosed in the embodiments of the chip, the electronic device, the vehicle and the power protection device of the present application, please refer to the description of the embodiment of the external monitoring reset circuit of the system shown in fig. 1 to 2, which is described in the foregoing application, for economy of description, and therefore, the description is not repeated.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of units is only one logical function division, and there may be other divisions in actual implementation, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units; can be located in one place or distributed to a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated in one unit; the integrated units may be implemented in hardware or in hardware plus software functional units.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, where the program, when executed, performs steps including the above method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read Only Memory (ROM), a magnetic disk or an optical disk, or the like, which can store program codes.
Alternatively, the integrated units described above may be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or partly contributing to the prior art, and the computer software product may be stored in a storage medium, and include several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the methods of the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a removable storage device, a ROM, a magnetic disk, or an optical disk.
The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes or substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (10)
1. A system external monitor reset circuit for monitoring and resetting operation of a chip having a plurality of chip domains, the chip domains including a security domain and an application domain, the circuit comprising:
the charging and discharging branch is connected with the monitoring output end of one or more chip domains, charges the charging and discharging capacity when the monitoring output end outputs PWM waves, and opens a controllable switch between the charging and discharging branch and the resetting branch to enable the buffer capacitor of the resetting branch to discharge, and discharges the charging and discharging capacity when the output of the monitoring output end changes from outputting PWM waves to outputting low level or no output;
a reset branch circuit for charging the buffer capacitor when the output of the monitoring output terminal changes from outputting PWM waves to outputting low level or no output;
the first isolating switch is used for isolating the influence of the charging and discharging branch on the reset branch, one end of the first isolating switch is connected with the reset branch, and the other end of the first isolating switch is connected with the reset signal input end of the chip domain;
and the second isolating switch is used for isolating the influence of the reset branch on the charge and discharge branch, one end of the second isolating switch is connected with the charge and discharge branch, and the other end of the second isolating switch is connected with the reset signal input end of the chip domain.
2. The system external monitor reset circuit of claim 1, further comprising:
and the push-pull circuit is connected with the monitoring output ends of the application domains of the chip and is used for synthesizing the monitoring output ends of the application domains into a path of monitoring output end signals.
3. The system external monitor reset circuit of claim 2, for monitoring and resetting chip operation with two application domains; in a corresponding manner,
the push-pull circuit includes:
the control end of the first switching tube is connected with the monitoring output end of the first application domain of the chip, the input end of the first switching tube is connected with the ground end, and the output end of the first switching tube is connected with the input end of the charging and discharging branch circuit;
the control end of the second switching tube is connected with the monitoring output end of the second application domain of the chip, the input end of the second switching tube is connected with the ground end, and the output end of the second switching tube is connected with the input end of the charging and discharging branch circuit;
and one end of the pull-up resistor is connected with the second switching tube, and the other end of the pull-up resistor is connected with the power supply end.
4. The system external monitoring reset circuit according to claim 3, wherein the first switching tube is an N-type MOS tube, and the second switching tube is a P-type MOS tube; in a corresponding manner,
the push-pull circuit further includes:
the first base resistor is connected between the control end of the first switching tube and the monitoring output end of the first application domain;
and the second base resistor is connected between the control end of the second switching tube and the monitoring output end of the second application domain.
5. The system external monitoring reset circuit of claim 1, the charge-discharge branch comprising:
the charging switch is connected between the monitoring output end and the charging and discharging capacity, and charges the charging and discharging capacity when the monitoring output end outputs a high level;
one end of the charging/discharging tube is connected with the charging switch, and the other end of the charging/discharging tube is grounded;
a zener diode and a discharge resistor connected in parallel with the charge/discharge cell, the charge/discharge cell being capable of being discharged through the zener diode and the discharge resistor when the output of the monitor output terminal changes from a high level to a low level or no output;
and the isolation capacitor is connected between the monitoring output end and the charging switch.
6. The system external monitoring reset circuit of claim 1, the reset leg comprising:
one end of the reset resistor is connected with the power supply end, and the other end of the reset resistor is connected with the buffer capacitor;
one end of the buffer capacitor is connected with the reset resistor, and the other end of the buffer capacitor is grounded; in a corresponding manner,
the connection point of the first isolating switch and the reset branch is positioned between the reset resistor and the buffer capacitor.
7. A chip comprising the system external monitor reset circuit of any one of claims 1-6.
8. An electronic device comprising the chip of claim 7.
9. A vehicle comprising the electronic device of claim 8.
10. A power protection device comprising the electronic device of claim 8.
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