CN116225147A - Current regulating circuit - Google Patents

Abstract

The invention discloses a current regulating circuit, a first control module is arranged between a grid electrode of a first PMOS and a grid electrode of a second PMOS, the first control module controls the grid electrode of the second PMOS to be connected with the grid electrode of the first PMOS when receiving a first closing instruction, the second PMOS is conducted, and the first PMOS and the second PMOS form a current mirror and output current; and when the first disconnection instruction is received, the second PMOS is controlled to be disconnected, and the second PMOS cannot output current. When the second PMOS is conducted, the current output by the drain electrode of the second PMOS directly flows into the output end of the current regulating circuit, so that the second PMOS is prevented from being influenced by conduction voltage drop, and therefore the second PMOS stably works in a saturation region, the working condition that the second PMOS is used as a current mirror to stably work is met, and the stability of the current regulating circuit is guaranteed.

Description

Current regulating circuit

Technical Field

The present invention relates to the field of integrated circuit design, and in particular, to a current regulating circuit.

Background

In integrated circuit designs, many circuits require current regulation circuitry to provide a stable current, and thus, the performance of the integrated circuit is directly affected by the quality of the current regulation circuitry design. The current regulation circuit typically uses a current mirror to regulate the output current of the current regulation circuit, the current mirror typically having 1 input to provide a reference current and having multiple outputs in parallel to output a total current based on the reference current. The input circuit of the current mirror comprises a reference MOS tube, each output of the current mirror comprises an output MOS tube which is in common gate and common source with the reference MOS tube, and a switch MOS tube which is connected with the drain electrode of the output MOS tube and used as a switch, the drain electrode of the switch MOS tube is used as the output of the circuit, and the drain electrodes of the switch MOS tubes in the multiplexing output are connected to output the final total current of the current mirror. However, as the switching MOS tube has a conduction voltage drop, the output MOS tube in the current mirror is influenced by the switching MOS tube, and cannot stably work in a saturation region, so that the working condition of the current mirror for stable work cannot be met, and the stability of the current regulating circuit is influenced.

Disclosure of Invention

The invention aims to provide a current regulating circuit which can prevent a second PMOS from being influenced by conduction voltage drop, so that the second PMOS stably works in a saturation region, meets the working condition that the second PMOS is used as a current mirror to stably work, and ensures the stability of the current regulating circuit.

In order to solve the technical problems, the invention provides a current regulating circuit, which comprises a reference current providing module, a first PMOS and N first output modules, wherein each first output module comprises a second PMOS and a first control module, and N is a positive integer;

the output end of the reference current providing module is connected with the drain electrode of the first PMOS and is used for providing the reference current flowing from the drain electrode of the first PMOS to the output end of the reference current providing module for the first PMOS;

the source electrode of the first PMOS and the first ends of the N first output modules are connected with a first power supply, the grid electrode of the first PMOS is respectively connected with the drain electrode of the first PMOS and the second ends of the N first output modules, and the common end connected with the third ends of the N first output modules is used as the output end of the current regulating circuit;

the first end of the first control module is used as the second end of the first output module, the source electrode of the second PMOS is used as the first end of the first output module, the second end of the first control module is connected with the grid electrode of the second PMOS, and the drain electrode of the second PMOS is used as the third end of the first output module;

the first control module is used for controlling the connection of the grid electrode of the second PMOS and the grid electrode of the first PMOS to control the connection of the second PMOS when a first closing instruction is received, and controlling the disconnection of the second PMOS when a first disconnecting instruction is received.

Preferably, the reference current providing module includes a first NMOS and a second NMOS;

the drain electrode of the first NMOS is used as the input end of the reference current providing module, the drain electrode of the first NMOS is respectively connected with the grid electrode of the first NMOS and the grid electrode of the second NMOS, the source electrode of the first NMOS is grounded and connected with the source electrode of the second NMOS, the drain electrode of the second NMOS is connected with the drain electrode of the first PMOS, and the drain electrode of the second NMOS is used for providing the reference current flowing from the drain electrode of the first PMOS to the output end of the reference current providing module for the first PMOS according to the reference current.

Preferably, the first control module includes a third PMOS and a fourth PMOS;

the source electrode of the third PMOS is used as the first end of the first control module, the source electrode of the fourth PMOS is connected with the first power supply, the drain electrode of the third PMOS is connected with the drain electrode of the fourth PMOS, the connected common end is used as the second end of the first control module, and the grid electrode of the third PMOS is used for being conducted when receiving a first low level and turned off when receiving a first high level; the grid electrode of the fourth PMOS is used for being turned off when receiving a second high level and turned on when receiving a second low level;

the first closing instruction includes the first low level and the second high level, and the first opening instruction includes the first high level and the second low level.

Preferably, the reference current supply module is further included, and an output end of the reference current supply module is connected with a drain electrode of the first NMOS and is used for supplying the reference current.

Preferably, the reference current providing module includes an operational amplifier, a fifth PMOS and a resistor, where an inverting input end of the operational amplifier is connected to the second power supply, a non-inverting input end of the operational amplifier is connected to a first end of the resistor, a common end connected to the non-inverting input end of the operational amplifier is connected to a drain electrode of the fifth PMOS, a second end of the resistor is grounded and is used as an output end of the reference current providing module, an output end of the operational amplifier is connected to a gate electrode of the fifth PMOS, and a source electrode of the fifth PMOS is connected to the third power supply.

Preferably, the aspect ratio of the first NMOS is the same as the aspect ratio of the second NMOS.

Preferably, the width-to-length ratio of the first PMOS is the same as the width-to-length ratio of the second PMOS.

Preferably, the system further comprises N second output modules, each of which comprises a third NMOS and a second control module;

the first ends of the N second output modules are grounded, the second ends of the N second output modules are connected with the grid electrode of the second NMOS, and the common end, which is connected with the third ends of the N first output modules and is used as the output end of the current regulating circuit, of the N second output modules;

the first end of the second control module is used as the second end of the second output module, the source electrode of the third NMOS is used as the first end of the second output module, the second end of the second control module is connected with the grid electrode of the third NMOS, and the drain electrode of the third NMOS is used as the third end of the second output module;

the second control module is used for controlling the connection of the grid electrode of the third NMOS and the grid electrode of the second NMOS to control the connection of the third NMOS when receiving a second closing instruction, and controlling the disconnection of the third NMOS when receiving a second opening instruction.

Preferably, the second control module includes a fourth NMOS and a fifth NMOS;

the source electrode of the fourth NMOS is used as the first end of the second control module, the source electrode of the fifth NMOS is grounded, the drain electrode of the fourth NMOS is connected with the drain electrode of the fifth NMOS, and the connected common end is used as the second end of the second control module, and the grid electrode of the fourth NMOS is used for being conducted when receiving a third high level and turned off when receiving a third low level; the grid electrode of the fifth NMOS is used for being turned off when receiving a fourth low level and turned on when receiving a fourth high level;

the second closing instruction includes the third high level and the fourth low level, and the second opening instruction includes the third low level and the fourth high level.

Preferably, the width-to-length ratio of the third NMOS is the same as the width-to-length ratio of the second NMOS.

The invention provides a current regulating circuit, a first control module is arranged between a grid electrode of a first PMOS and a grid electrode of a second PMOS, the first control module controls the grid electrode of the second PMOS to be connected with the grid electrode of the first PMOS when receiving a first closing instruction, the second PMOS is conducted, and the first PMOS and the second PMOS form a current mirror and output current; and when the first disconnection instruction is received, the second PMOS is controlled to be disconnected, and the second PMOS cannot output current. When the second PMOS is conducted, the current output by the drain electrode of the second PMOS directly flows into the output end of the current regulating circuit, so that the second PMOS is prevented from being influenced by conduction voltage drop, and therefore the second PMOS stably works in a saturation region, the working condition that the second PMOS is used as a current mirror to stably work is met, and the stability of the current regulating circuit is guaranteed.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required in the prior art and the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

Fig. 1 is a schematic diagram of a current adjusting circuit according to the present invention;

fig. 2 is a schematic diagram of another current adjusting circuit according to the present invention.

Detailed Description

The core of the invention is to provide a current regulating circuit, which can avoid the influence of the conduction voltage drop on the second PMOS, so that the second PMOS stably works in a saturation region, the working condition of the second PMOS as a current mirror for stable work is met, and the stability of the current regulating circuit is ensured.

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a current regulation circuit provided by the present invention, the current regulation circuit includes a reference current providing module 11, a first PMOS12 and N first output modules 13, each first output module 13 includes a second PMOS131 and a first control module 132, and N is a positive integer;

the output end of the reference current providing module 11 is connected with the drain electrode of the first PMOS12, and is used for providing the reference current flowing from the drain electrode of the first PMOS12 to the output end of the reference current providing module 11 for the first PMOS 12;

the source electrode of the first PMOS12 and the first ends of the N first output modules 13 are connected with a first power supply, the grid electrode of the first PMOS12 is respectively connected with the drain electrode of the first PMOS12 and the second ends of the N first output modules 13, and the third ends of the N first output modules 13 are connected and the connected common end is used as the output end of the current regulating circuit;

the first end of the first control module 132 is used as the second end of the first output module 13, the source electrode of the second PMOS131 is used as the first end of the first output module 13, the second end of the first control module 132 is connected with the gate electrode of the second PMOS131, and the drain electrode of the second PMOS131 is used as the third end of the first output module 13;

the first control module 132 is configured to control the gate of the second PMOS131 to be connected to the gate of the first PMOS12 to control the second PMOS131 to be turned on when receiving the first closing instruction, and control the second PMOS131 to be turned off when receiving the first opening instruction.

In the prior art, as the switching MOS tube has conduction voltage drop, the drain voltage of the output MOS tube in the current mirror is influenced by the conduction voltage drop of the switching MOS tube, and the drain voltage of the output MOS tube influences whether the output MOS tube can stably work in a saturation region or not, if the output MOS tube cannot stably work in the saturation region, the working condition of the stable work of the current mirror cannot be met, and further the stability of the current regulating circuit is influenced.

In order to solve the above technical problems, the present application provides a current adjusting circuit, which adopts a first PMOS12 and a second PMOS131 that are co-gated and co-sourced to form a current mirror, and a first control module 132 is disposed between the gate of the first PMOS12 and the gate of the second PMOS131 to control the second PMOS131 to be turned on or off, so that the purpose of adjusting the output current of the current adjusting circuit is achieved on the basis that the drain voltage of the second PMOS131 is not affected by the conduction voltage drop, that is, the second PMOS131 can stably work in a saturation region.

Specifically, the drain of the first PMOS12 is connected to the output terminal of the reference current providing module 11, the reference current providing module 11 provides the reference current for the first PMOS12, and when the first PMOS12 is turned on, the drain of the first PMOS12 outputs the reference current. Since the second PMOS131 and the first PMOS12 are in common gate and common source, after the first control module 132 receives the first closing instruction to control the gate of the second PMOS131 to be connected with the gate of the first PMOS12, the second PMOS131 is turned on, and the direction of the current output by the drain of the second PMOS131 is consistent with the direction of the current output by the drain of the first PMOS12, that is, the reference current, and the magnitude of the current is proportional to the ratio of the width-to-length ratio of the second PMOS131 to the width-to-length ratio of the first PMOS 12. The output current of the current adjusting circuit is the vector sum of the currents output from the drains of the second PMOS131 in the on state. If the width-to-length ratio of the first PMOS12 is the same as that of the second PMOS131, the output current of the current adjusting circuit is M times of the reference current, where M is the number of the second PMOS131 in the on state.

In summary, the present invention provides a current adjusting circuit, wherein a first control module 132 is disposed between a gate of a first PMOS12 and a gate of a second PMOS131, the first control module 132 controls the gate of the second PMOS131 to be connected to the gate of the first PMOS12 when receiving a first closing instruction, the second PMOS131 is turned on, and the first PMOS12 and the second PMOS131 form a current mirror and output current in a common gate and common source manner; when the first turn-off command is received, the second PMOS131 is controlled to turn off, and the second PMOS131 cannot output current. When the second PMOS131 is turned on, the current output by the drain of the second PMOS131 directly flows into the output end of the current adjusting circuit, so that the second PMOS131 is prevented from being affected by the conduction voltage drop, and thus the second PMOS131 stably works in a saturation region, the working condition that the second PMOS131 works as a current mirror stably is met, and the stability of the current adjusting circuit is ensured.

Based on the above embodiments:

as a preferred embodiment, the reference current supply module 11 includes a first NMOS and a second NMOS;

the drain electrode of the first NMOS is used as the input end of the reference current providing module 11, the drain electrode of the first NMOS is respectively connected with the gate electrode of the first NMOS and the gate electrode of the second NMOS, the source electrode of the first NMOS is grounded and connected with the source electrode of the second NMOS, and the drain electrode of the second NMOS is connected with the drain electrode of the first PMOS12 and is used for providing the reference current flowing from the drain electrode of the first PMOS12 to the output end of the reference current providing module 11 for the first PMOS12 according to the reference current.

In this embodiment, the reference current providing module 11 is formed by a first NMOS and a second NMOS, the source of the first NMOS and the source of the second NMOS are both grounded, the gate of the first NMOS is connected to the gate of the second NMOS, and the connected common terminal is connected to the drain of the first NMOS, so that the connection mode satisfies the conduction conditions of the first NMOS and the second NMOS, and the first NMOS and the second NMOS form a common-gate and common-source current mirror. The drain electrode of the first NMOS is used as the input end of the reference current providing module 11 to input the reference current, the drain electrode of the second NMOS is connected with the drain electrode of the first PMOS12 to provide the reference current flowing from the drain electrode of the first PMOS12 to the output end of the reference current providing module 11 for the first PMOS12 according to the reference current, wherein, the direction of the reference current is consistent with the direction of the reference current, and the magnitude is proportional to the ratio of the aspect ratio of the first NMOS to the aspect ratio of the second NMOS because the first NMOS and the second NMOS form a current mirror of a common gate common source. If the width-to-length ratio of the first NMOS is the same as that of the second NMOS, the magnitude and direction of the reference current are the same as those of the reference current. In addition, the reference current supply module 11 in the present embodiment has the advantage of simple structure and easy implementation.

As a preferred embodiment, the first control module 132 includes a third PMOS and a fourth PMOS;

the source electrode of the third PMOS is used as the first end of the first control module 132, the source electrode of the fourth PMOS is connected with the first power supply, the drain electrode of the third PMOS is connected with the drain electrode of the fourth PMOS, and the connected common end is used as the second end of the first control module 132, the gate electrode of the third PMOS is used for being turned on when receiving the first low level and turned off when receiving the first high level; the grid electrode of the fourth PMOS is used for being turned off when receiving the second high level and turned on when receiving the second low level;

the first closing command comprises a first low level and a second high level, and the first opening command comprises a first high level and a second low level.

In the present embodiment, the first control module 132 is composed of a third PMOS and a fourth PMOS. Specifically, when the first control module 132 is to control the second PMOS131 to be turned on: since the source of the third PMOS is connected to the gate of the first PMOS12 as the first end of the first control module 132, when the gate of the third PMOS receives the first low level, the on condition of the first PMOS12 is satisfied, so that the first PMOS12 is turned on, and further, the gate of the second PMOS131 is connected to the gate of the first PMOS12, so that the second PMOS131 is turned on and outputs current as a current mirror co-gate-co-source with the first PMOS12, so as to achieve the purpose of adjusting the output current of the current adjusting circuit.

When the first control module 132 is to control the second PMOS131 to turn off: the gate of the third PMOS receives the first high level, and does not meet the conduction condition of the third PMOS, so the third PMOS is turned off, and further the connection between the gate of the second PMOS131 and the first PMOS12 is disconnected, but because the gate impedance of the MOS transistor is very high, even if the connection between the gate of the second PMOS131 and the first PMOS12 is disconnected, the gate of the second PMOS131 still maintains the potential when being turned on, so that the drain of the second PMOS131 still outputs the current, and for the above reasons, the present application sets a fourth PMOS, which is turned on when receiving the second low level, so that the gate of the second PMOS131 is connected with the power supply, so that the potential of the gate of the second PMOS131 is equal to the potential of the source and equal to the power supply voltage, so the second PMOS131 no longer meets the conduction condition, and the second PMOS131 is turned off and no longer outputs the current.

In summary, in the present embodiment, the first control module 132 is formed by the third PMOS and the fourth PMOS, which has a simple structure and reliable operation.

As a preferred embodiment, the reference current providing module further comprises a reference current providing module, wherein an output end of the reference current providing module is connected with the drain electrode of the first NMOS, and is used for providing the reference current.

In this embodiment, the drain electrode of the first NMOS is connected to the reference current providing module, so that the current adjusting circuit itself can adjust the output current of the current adjusting circuit based on the reference current, without connecting an external device.

As a preferred embodiment, the reference current providing module includes an operational amplifier, a fifth PMOS and a resistor, the inverting input terminal of the operational amplifier is connected to the second power supply, the non-inverting input terminal of the operational amplifier is connected to the first terminal of the resistor, the connected common terminal is connected to the drain electrode of the fifth PMOS, the second terminal of the resistor is grounded and serves as the output terminal of the reference current providing module, the output terminal of the operational amplifier is connected to the gate electrode of the fifth PMOS, and the source electrode of the fifth PMOS is connected to the third power supply.

The embodiment provides a specific structure of a reference current providing module, wherein the reference current provided by the reference current providing module is equal to the voltage value of the second power supply and the resistance value of the upper resistor, and the direction of the reference current is from the output end of the reference current providing module to the drain electrode of the first NMOS.

As a preferred embodiment, the aspect ratio of the first NMOS is the same as the aspect ratio of the second NMOS.

The current after the MOS tube is conducted is (V) _GS -V _TH ) ² (W/L) where V _GS Is the starting voltage of the MOS tube, V _TH The threshold voltage of the MOS tube is given, and W/L is the width-to-length ratio of the MOS tube. If V of each MOS tube _GS V (V) _TH And if the current is the same, the ratio of the currents after the conduction of the MOS tubes is equal to the ratio between the width-to-length ratios of the MOS tubes. Based on the above principle, in this embodiment, the first NMOS and the second NMOS with the same width-to-length ratio are selected, and then the current after the second NMOS is turned on is equal to the current after the first NMOS is turned on, so that the output current of the current adjusting circuit is relatively intuitive and simple when the output current is adjusted, and the circuit structure is simple and easy to implement.

As a preferred embodiment, the aspect ratio of the first PMOS12 is the same as the aspect ratio of the second PMOS 131.

The current after the MOS tube is conducted is (V) _GS -V _TH ) ² (W/L) where V _GS Is the starting voltage of the MOS tube, V _TH The threshold voltage of the MOS tube is given, and W/L is the width-to-length ratio of the MOS tube. If V of each MOS tube _GS V (V) _TH The ratio of the currents after the conduction of each MOS tube is equal to that of each MOS tubeRatio between the aspect ratio of (c) and (d). Based on the above principle, in this embodiment, the first PMOS12 and the second PMOS131 with the same width-to-length ratio are selected, and then the current after the second PMOS131 is turned on is equal to the current after the first PMOS12 is turned on, so that the output current of the current adjusting circuit is relatively intuitive and simple when the output current is adjusted, and the circuit structure is simple and easy to implement.

As a preferred embodiment, N second output modules 21 are further included, each second output module 21 including a third NMOS213 and a second control module 212;

the first ends of the N second output modules 21 are grounded, the second ends of the N second output modules 21 are connected with the grid electrode of the second NMOS, and the common end, which is connected with the third ends of the N first output modules 13, of the third ends of the N second output modules 21 is used as the output end of the current regulating circuit;

the first end of the second control module 212 is used as the second end of the second output module 21, the source electrode of the third NMOS213 is used as the first end of the second output module 21, the second end of the second control module 212 is connected with the gate electrode of the third NMOS213, and the drain electrode of the third NMOS213 is used as the third end of the second output module 21;

the second control module 212 is configured to control connection of the gate of the third NMOS213 and the gate of the second NMOS to control the third NMOS213 to be turned on when receiving the second close command, and control the third NMOS213 to be turned off when receiving the second open command.

In this embodiment, the third NMOS213 and the second NMOS that are co-gated and co-sourced form a current mirror, and the second control module 212 is disposed between the gate of the third NMOS213 and the gate of the second NMOS to control the on or off of the third NMOS213, so that the purpose of adjusting the output current of the current adjusting circuit is achieved on the basis that the drain voltage of the third NMOS213 is not affected by the on-voltage drop, that is, the third NMOS213 can stably operate in the saturation region.

Specifically, since the third NMOS213 is co-gated with the second NMOS, after the second control module 212 receives the second close command to control the gate of the third NMOS213 to be connected to the gate of the second NMOS, the third NMOS213 is turned on, and the direction of the current output by the drain of the third NMOS213 is consistent with the direction of the current output by the drain of the second NMOS, that is, the reference current, and the magnitude is proportional to the ratio of the aspect ratio of the second NMOS to the aspect ratio of the third NMOS 213. The output current of the current adjusting circuit is the vector sum of the current output by the drain of the second PMOS131 in the on state and the current output by the drain of the third NMOS213 in the on state. If the width-to-length ratio of the first PMOS12 is the same as the width-to-length ratio of the second PMOS131 and the width-to-length ratio of the second NMOS is the same as the width-to-length ratio of the third NMOS213, the output current of the current adjusting circuit is X times the reference current, where X is the number of the second PMOS131 in the on state plus the number of the third NMOS213 in the on state.

As a preferred embodiment, the second control module 212 includes a fourth NMOS and a fifth NMOS;

the source electrode of the fourth NMOS is used as the first end of the second control module 212, the source electrode of the fifth NMOS is grounded, the drain electrode of the fourth NMOS is connected with the drain electrode of the fifth NMOS, and the connected common end is used as the second end of the second control module 212, and the gate electrode of the fourth NMOS is used for being turned on when receiving the third high level and turned off when receiving the third low level; the grid electrode of the fifth NMOS is used for being turned off when receiving a fourth low level and turned on when receiving a fourth high level;

the second closing command comprises a third high level and a fourth low level, and the second opening command comprises a third low level and a fourth high level.

Fig. 2 is a schematic diagram of another current adjusting circuit according to the present invention.

In the present embodiment, the second control module 212 is constituted by a fourth NMOS and a fifth NMOS. Specifically, when the second control module 212 is to control the third NMOS213 to be turned on: since the source of the fourth NMOS is connected to the gate of the second NMOS as the first end of the second control module 212, when the gate of the fourth NMOS receives the third high level, the conduction condition of the fourth NMOS is satisfied, so that the fourth NMOS is turned on, and further, the gate of the second NMOS is connected to the gate of the third NMOS213, so that the third NMOS213 is turned on and outputs current as a current mirror co-gate-co-source with the second NMOS, so as to achieve the purpose of adjusting the output current of the current adjusting circuit.

When the second control module 212 is to control the third NMOS213 to be turned off: the gate of the fourth NMOS receives the third low level, and does not meet the on condition of the fourth NMOS, so the fourth NMOS is turned off, and the gate of the third NMOS213 is further disconnected from the gate of the second NMOS, but because the gate impedance of the MOS transistor is very high, even if the gate of the third NMOS213 is disconnected from the gate of the second NMOS, the gate of the third NMOS213 still maintains the potential when being turned on, so that the drain of the third NMOS213 still outputs the current.

In summary, in the present embodiment, the first control module 132 is formed by the fourth NMOS and the fifth NMOS, which has a simple structure and reliable operation.

As a preferred embodiment, the width-to-length ratio of the third NMOS213 is the same as the width-to-length ratio of the second NMOS.

In this embodiment, the third NMOS213 and the second NMOS with the same width-to-length ratio are selected, and the current after the third NMOS213 is turned on is equal to the current after the second NMOS is turned on, so that the output current of the current adjusting circuit is relatively intuitive and simple when the output current is adjusted, and the circuit structure is simple and easy to implement.

It should be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (10)

1. The current regulating circuit is characterized by comprising a reference current providing module, a first PMOS and N first output modules, wherein each first output module comprises a second PMOS and a first control module, and N is a positive integer;

the output end of the reference current providing module is connected with the drain electrode of the first PMOS and is used for providing the reference current flowing from the drain electrode of the first PMOS to the output end of the reference current providing module for the first PMOS;

the source electrode of the first PMOS and the first ends of the N first output modules are connected with a first power supply, the grid electrode of the first PMOS is respectively connected with the drain electrode of the first PMOS and the second ends of the N first output modules, and the common end connected with the third ends of the N first output modules is used as the output end of the current regulating circuit;

the first end of the first control module is used as the second end of the first output module, the source electrode of the second PMOS is used as the first end of the first output module, the second end of the first control module is connected with the grid electrode of the second PMOS, and the drain electrode of the second PMOS is used as the third end of the first output module;

the first control module is used for controlling the connection of the grid electrode of the second PMOS and the grid electrode of the first PMOS to control the connection of the second PMOS when a first closing instruction is received, and controlling the disconnection of the second PMOS when a first disconnecting instruction is received.

2. The current regulation circuit of claim 1 wherein the reference current supply module comprises a first NMOS and a second NMOS;

the drain electrode of the first NMOS is used as the input end of the reference current providing module, the drain electrode of the first NMOS is respectively connected with the grid electrode of the first NMOS and the grid electrode of the second NMOS, the source electrode of the first NMOS is grounded and connected with the source electrode of the second NMOS, the drain electrode of the second NMOS is connected with the drain electrode of the first PMOS, and the drain electrode of the second NMOS is used for providing the reference current flowing from the drain electrode of the first PMOS to the output end of the reference current providing module for the first PMOS according to the reference current.

3. The current regulation circuit of claim 2, wherein the first control module includes a third PMOS and a fourth PMOS;

the source electrode of the third PMOS is used as the first end of the first control module, the source electrode of the fourth PMOS is connected with the first power supply, the drain electrode of the third PMOS is connected with the drain electrode of the fourth PMOS, the connected common end is used as the second end of the first control module, and the grid electrode of the third PMOS is used for being conducted when receiving a first low level and turned off when receiving a first high level; the grid electrode of the fourth PMOS is used for being turned off when receiving a second high level and turned on when receiving a second low level;

the first closing instruction includes the first low level and the second high level, and the first opening instruction includes the first high level and the second low level.

4. The current regulation circuit of claim 2 further comprising a reference current supply module, an output of the reference current supply module being connected to a drain of the first NMOS for providing the reference current.

5. The current regulation circuit of claim 4 wherein the reference current supply module comprises an operational amplifier, a fifth PMOS and a resistor, the inverting input of the operational amplifier is connected to a second power supply, the non-inverting input of the operational amplifier is connected to the first end of the resistor and the common terminal of the connection is connected to the drain of the fifth PMOS, the second end of the resistor is grounded and serves as the output of the reference current supply module, the output of the operational amplifier is connected to the gate of the fifth PMOS, and the source of the fifth PMOS is connected to a third power supply.

6. The current regulation circuit of claim 2 wherein the first NMOS has a same aspect ratio as the second NMOS.

7. The current regulation circuit of claim 6 wherein the first PMOS has a same aspect ratio as the second PMOS.

8. The current regulation circuit of any one of claims 2 to 7, further comprising N second output modules, each second output module comprising a third NMOS and a second control module;

the first ends of the N second output modules are grounded, the second ends of the N second output modules are connected with the grid electrode of the second NMOS, and the common end, which is connected with the third ends of the N first output modules and is used as the output end of the current regulating circuit, of the N second output modules;

the first end of the second control module is used as the second end of the second output module, the source electrode of the third NMOS is used as the first end of the second output module, the second end of the second control module is connected with the grid electrode of the third NMOS, and the drain electrode of the third NMOS is used as the third end of the second output module;

the second control module is used for controlling the connection of the grid electrode of the third NMOS and the grid electrode of the second NMOS to control the connection of the third NMOS when receiving a second closing instruction, and controlling the disconnection of the third NMOS when receiving a second opening instruction.

9. The current regulation circuit of claim 8 wherein the second control module includes a fourth NMOS and a fifth NMOS;

the source electrode of the fourth NMOS is used as the first end of the second control module, the source electrode of the fifth NMOS is grounded, the drain electrode of the fourth NMOS is connected with the drain electrode of the fifth NMOS, and the connected common end is used as the second end of the second control module, and the grid electrode of the fourth NMOS is used for being conducted when receiving a third high level and turned off when receiving a third low level; the grid electrode of the fifth NMOS is used for being turned off when receiving a fourth low level and turned on when receiving a fourth high level;

the second closing instruction includes the third high level and the fourth low level, and the second opening instruction includes the third low level and the fourth high level.

10. The current regulation circuit of claim 8 wherein the third NMOS has a same aspect ratio as the second NMOS.

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