CN116224296A

CN116224296A - Phased array radar and information acquisition method, storage medium and electronic equipment

Info

Publication number: CN116224296A
Application number: CN202310336643.2A
Authority: CN
Inventors: 邓庆文; 渠慎奇; 钱程
Original assignee: Zhejiang Lab
Current assignee: Zhejiang Lab
Priority date: 2023-03-28
Filing date: 2023-03-28
Publication date: 2023-06-06
Anticipated expiration: 2043-03-28
Also published as: CN116224296B

Abstract

The specification discloses a phased array radar and information acquisition method, a storage medium and electronic equipment. The phased array radar includes: wafer, signal processing unit, a plurality of power supply chip group and a plurality of receiving chip group, wherein, every power supply chip group corresponds at least one receiving chip group, a plurality of power supply chip groups evenly set up around the inside of wafer, signal processing unit sets up the inside central authorities of wafer, to every receiving chip group, this receiving chip group includes: the radio frequency chip unit is arranged in the wafer, the antenna unit is arranged on the upper surface of the wafer right above the radio frequency chip unit, a rewiring layer is arranged above the radio frequency chip unit, and the radio frequency chip unit is connected with the antenna unit arranged on the upper surface of the wafer through the rewiring layer.

Description

Phased array radar and information acquisition method, storage medium and electronic equipment

Technical Field

The present disclosure relates to the field of radars, and in particular, to a phased array radar, an information acquisition method, a storage medium, and an electronic device.

Background

The phased array radar is a radar adopting a phased array antenna, the phased array antenna is developed from an array antenna adopted by the early radar, a directional antenna is formed by arranging a plurality of radio frequency units (array elements), and the electronic control phase shifter is utilized to change the phase distribution of the array elements of the antenna so as to realize the rotation or scanning of beam pointing in space.

However, the radio frequency receiving unit of the current phased array radar is usually mounted on a printed circuit board (Printed Circuit Board, PCB), and the radio frequency receiving unit is connected with an antenna through a long microstrip line or a radio frequency cable, which results in a large signal power loss. Moreover, as all chips are integrated on the PCB, the PCB is required to provide a larger deployment area, so that the power supply system has larger loss during transmission, the power supply use efficiency is lower, and the phased array radar has larger volume.

Therefore, how to reduce the volume of the phased array radar, reduce the power loss of signals in the transmission process, and improve the use efficiency of the power supply is a problem to be solved urgently.

Disclosure of Invention

The present specification provides a phased array radar and information acquisition method, a storage medium, and an electronic device, to partially solve the above-mentioned problems existing in the prior art.

The technical scheme adopted in the specification is as follows:

the present specification provides a phased array radar comprising: the phased array radar includes: the system comprises a wafer, a signal processing unit, a plurality of power supply chip sets and a plurality of receiving chip sets, wherein each power supply chip set corresponds to at least one receiving chip set;

the power supply chip sets are uniformly arranged around the inside of the wafer, the signal processing unit is arranged in the center of the inside of the wafer, and the receiving chip sets comprise, for each receiving chip set: the radio frequency chip unit is arranged in the wafer, the antenna unit is arranged on the upper surface of the wafer right above the radio frequency chip unit, a rewiring layer is arranged above the radio frequency chip unit, and the radio frequency chip unit is connected with the antenna unit arranged on the upper surface of the wafer through the rewiring layer;

for each power supply chipset, the power supply chipset is used for supplying power to a receiving chipset corresponding to the power supply chipset;

the antenna unit is used for receiving electromagnetic wave signals and transmitting the electromagnetic wave signals to the radio frequency chip unit;

the radio frequency chip unit is used for converting the electromagnetic wave signals to obtain converted signals and sending the converted signals to the signal processing unit;

the signal processing unit is used for receiving power supply of at least two power supply chip sets, and processing the converted signals to obtain processed signals so as to obtain information carried by the electromagnetic wave signals according to the processed signals.

Optionally, the redistribution layer is prepared on the upper surface of the wafer.

Optionally, the rerouting layer includes: a silicon dioxide layer, a metal layer and a hafnium oxide layer.

Optionally, for each power chipset, the power chipset includes: at least one of the DC-DC converter DC-DC unit and the LDO unit.

Optionally, the phased array radar includes at least four power supply chip sets, and the signal processing unit is powered by two of the power supply chip sets.

Optionally, the number of corresponding receiving chipsets for each power chipset is the same.

Optionally, for each power chipset, the power chipset is configured to supply power to a radio frequency chip unit in a receiving chipset corresponding to the power chipset.

Optionally, the plurality of receiving chip sets are disposed inside the wafer according to a uniform planar array, where the number of rows and columns of the uniform planar array are equal.

Optionally, a low noise amplifier, a quadrature mixer, a power amplifier, a filter and an analog-to-digital converter ADC are arranged in the radio frequency chip unit;

the radio frequency chip unit is used for performing preliminary processing on the electromagnetic wave signal through the low noise amplifier, the quadrature mixer, the power amplifier and the filter, and inputting the signal after preliminary processing into the ADC to obtain the converted signal.

Optionally, the antenna unit is connected with a low noise amplifier in the radio frequency chip unit;

the antenna unit is used for transmitting the received electromagnetic wave signal to the low noise amplifier.

Optionally, the ports of the quadrature mixer include a radio frequency input port, a local oscillator input port, a first quadrature output port, and a second quadrature output port;

the radio frequency input port is used for receiving the signal output by the low noise amplifier;

the first orthogonal output port is used for outputting a first orthogonal signal, and the second orthogonal output port is used for outputting a second orthogonal signal, wherein the first orthogonal signal and the second orthogonal signal are in an orthogonal relationship;

the local oscillation input port is used for receiving the local oscillation signal.

Optionally, the phased array radar further comprises: a local oscillator and at least two power dividers;

the local oscillator input port is used for receiving the output of the local oscillator signal generated by the local oscillator after being processed by each power divider.

Optionally, the local oscillator input ports in each radio frequency chip unit have the same frequency and the same phase.

Optionally, the quadrature mixer is configured to receive the signal output by the low noise amplifier and the local oscillation signal, and generate and output the first quadrature signal and the second quadrature signal according to the signal output by the low noise amplifier and the local oscillation signal.

Optionally, the signal processing unit is further configured to control at least one of the receiving chipset and the power chipset according to the processed signal.

Optionally, the antenna unit is disposed on the hafnium oxide layer.

Optionally, the antenna unit includes: a patch antenna.

The specification provides an information acquisition method which is applied to the phased array radar, and comprises the following steps:

receiving electromagnetic wave signals through the phased array radar, and converting the electromagnetic wave signals to obtain converted signals;

processing the converted signal to obtain a processed signal;

and acquiring information carried by the electromagnetic wave signal according to the processed signal.

The present specification provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements the above-described information acquisition method.

The above-mentioned at least one technical scheme that this specification adopted can reach following beneficial effect:

the phased array radar in this specification includes: wafer, signal processing unit, a plurality of power supply chip group and a plurality of receiving chip group, wherein, every power supply chip group corresponds at least one receiving chip group, a plurality of power supply chip groups evenly set up around the inside of wafer, signal processing unit sets up the inside central authorities of wafer, to every receiving chip group, this receiving chip group includes: the radio frequency chip unit is arranged in the wafer, the antenna unit is arranged on the upper surface of the wafer right above the radio frequency chip unit, a rewiring layer is arranged above the radio frequency chip unit, and the radio frequency chip unit is connected with the antenna unit arranged on the upper surface of the wafer through the rewiring layer.

According to the phased array radar, the power supply chip set, the receiving chip set and the signal processing units of the phased array radar are integrated inside the wafer, the antenna units are arranged outside the wafer, each radio frequency unit and the corresponding antenna unit are not connected through a microstrip line or a radio frequency cable, so that the power loss in the signal transmission process is greatly reduced, and compared with the existing packaging method through a PCB, the phased array radar has the advantages that the same number of chips can be arranged in the wafer with a smaller area, the integration level of the phased array radar is greatly improved, the volume of the phased array radar is reduced, and the use efficiency of a power supply is further improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the specification, illustrate and explain the exemplary embodiments of the present specification and their description, are not intended to limit the specification unduly. In the drawings:

FIG. 1a is a schematic diagram of a phased array radar provided in the present specification;

FIG. 1b is a schematic diagram of a phased array radar provided in the present specification;

fig. 2 is a schematic circuit diagram of a phased array radar provided in the present specification;

FIG. 3 is a schematic diagram of a power supply circuit of a power chip set provided in the present specification;

fig. 4 is a schematic flow chart of an information acquisition method provided in the present specification;

fig. 5 is a schematic view of an electronic device corresponding to fig. 4 provided in the present specification.

Detailed Description

For the purposes of making the objects, technical solutions and advantages of the present specification more apparent, the technical solutions of the present specification will be clearly and completely described below with reference to specific embodiments of the present specification and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present specification. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.

The following describes in detail the technical solutions provided by the embodiments of the present specification with reference to the accompanying drawings.

Fig. 1a and 1b are schematic views of a phased array radar provided in the present specification, wherein fig. 1a and 1b are a view of the phased array radar in a direction of a top surface of a wafer and a view of the phased array radar at a side surface of the wafer, respectively.

The phased array radar includes: wafer, several power supply chip sets, several receiving chip sets, signal processing units and a rewiring layer (not shown in fig. 1 a).

Each receiving chip group comprises a radio frequency chip unit and an antenna unit, the radio frequency chip units can be prepared inside a wafer through a standard complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) active device process and are distributed according to a uniform plane array with equal row numbers and column numbers, and the antenna units in each receiving chip group are positioned on the upper surface of the wafer right above the radio frequency units in the receiving antenna group, so that the radio frequency chip units in each receiving chip group and one antenna unit right above a rewiring layer form a unique connection relationship.

The re-wiring layer can be prepared on the upper surface of the wafer by micro-nano manufacturing technology, and comprises a silicon dioxide layer, a metal layer and a hafnium dioxide layer, and is used for packaging chips in the wafer.

The antenna unit is arranged on the hafnium oxide layer in the rewiring layer, and can be a patch antenna for receiving electromagnetic wave signals and transmitting the electromagnetic wave signals to the radio frequency chip unit, and the radio frequency chip unit converts the electromagnetic wave signals after receiving the electromagnetic wave signals and sends the converted signals to the signal processing unit.

Specifically, each radio frequency chip unit includes a low noise amplifier, a quadrature mixer, a power amplifier, a filter and an analog-to-digital converter (Analog to Digital Converter, ADC), and the radio frequency chip unit is configured to perform preliminary processing on electromagnetic wave signals through the low noise amplifier, the quadrature mixer, the power amplifier and the filter, and input the preliminarily processed signals into the ADC to obtain digital signals sampled and converted by the ADC. For ease of understanding, the present disclosure provides a schematic circuit structure of a phased array radar, as shown in fig. 2.

Fig. 2 is a schematic circuit diagram of a phased array radar provided in the present specification.

The low noise amplifier is connected with the antenna unit, after the antenna unit receives the electromagnetic wave signal, the electromagnetic wave signal can be transmitted to the low noise amplifier In the radio frequency chip unit, the low noise amplifier outputs the signal to the Quadrature mixer, and after the Quadrature mixer receives the signal output by the low noise amplifier and the self-oscillation signal, the signal output by the low noise amplifier and the self-oscillation signal can be obtained and subjected to In-phase/Quadrature (I/Q) modulation, so that a first Quadrature signal (I-path signal) and a second Quadrature signal (Q-path signal) which are In Quadrature relation with each other are generated and output.

It should be noted that, since a plurality of receiving chipsets are provided in the present specification, when the number of receiving chipsets is n, the number of radio frequency chip units and antenna units is also n, each receiving chipset is arranged according to a (n×n) uniform planar array, only four receiving chipsets, R (1, 1), R (1, n), R (n, n), are shown in fig. 2, and other chipsets between the four receiving chipsets are connected based on the same manner, which is not shown in fig. 2.

In this specification, the quadrature mixer may be provided with four ports, which are a radio frequency input port (RF), a local oscillator input port (LO), a first quadrature output port (I-path port), and a second quadrature output port (Q-path port), respectively, where the radio frequency input port is used to obtain a signal output by the low noise amplifier, the first quadrature output port is used to output a first quadrature signal, the second quadrature output port is used to output a second quadrature signal, and the local oscillator input port is used to receive the local oscillator signal.

Furthermore, the phased array radar in the specification is further provided with a plurality of power dividers and a local oscillator, wherein the local oscillator is used for outputting local oscillation signals, and the local oscillation signals are processed by the multi-stage power dividers and then are input into quadrature mixers in each radio frequency chip set through local oscillation input ports. It should be noted that, the local oscillation input ports in each radio frequency chip unit have the same corresponding input frequency and the same phase.

For each signal output by the quadrature mixer, the signal is input to a corresponding ADC after preliminary processing by a power amplifier and a filter, sampled by the ADC, and converted into a digital signal (converted signal) and input to a signal processing unit.

The signal processing unit can be prepared at the middle position inside the wafer through a standard CMOS active device process, signals sampled by the ADC (processed signals) are output to the signal processing unit for processing, and the signal processing unit can perform fast Fourier transform (Fast Fourier transform, FFT), convolution, digital filtering, amplitude-phase weighting operation and the like on the processed signals, so that the processed signals are obtained.

Thus, information (such as distance, angle, speed, size, shape, etc. of the target object) carried in the received electromagnetic wave signal can be obtained according to the processed signal.

In this specification, the signal processing unit may parse the processed signal to obtain information carried in the electromagnetic wave signal, or of course, the processed signal may also be sent to a terminal device or a server connected to the phased array radar, so that the terminal device or the server parses the processed signal to obtain information carried in the electromagnetic wave signal.

In addition, the signal processing unit can also output a clock signal and a logic signal, so that the control of the radio frequency chip unit and the power supply chip set in each receiving chip set is realized according to the clock signal and the logic signal. For example, the signal processing unit may control when the power chipset starts or shuts down power, and when the ADC in the radio frequency chip unit starts or shuts down sampling and sampling frequency.

As shown in fig. 1a, the phased array radar in this specification may be provided with four power supply chipsets, namely a first power supply chipset, a second power supply chipset, a third power supply chipset, and a fourth power supply chipset.

The power supply chip sets are uniformly arranged around the wafer and are used for supplying power to the corresponding receiving chip sets and the signal processing units, and it is required to be noted that each power supply chip set in the specification corresponds to at least one receiving chip set and ensures that the number of the receiving chip sets is an integer multiple of the number of the power supply chip sets.

In this specification, the number of receiving chipsets corresponding to each power supply chipset may be the same, where each power supply chipset may be fabricated inside a wafer by a CMOS active device process and disposed on average in four directions of up, down, left, and right inside the wafer.

Each power chipset may include a DC-DC converter (DC-DC) unit and a low dropout linear regulator (Low Dropout Regulator, LDO) unit to provide a more stable power supply. Of course, it is also possible in this specification to supply power only through the DC-DC unit or only through the LDO unit. For ease of understanding, the present disclosure also provides a schematic power supply circuit of a power chipset, as shown in fig. 3.

Fig. 3 is a schematic diagram of a power supply circuit of a power chip set provided in the present specification.

The receiving chip set is an n×n uniform plane array, each radio frequency chip unit is an array element, the first row of radio frequency chip units are sequentially R (1, 1), R (1, 2), … …, R (1, n-1) and R (1, n), the second row of radio frequency chip units are sequentially R (2, 1), R (2, 2), … …, R (2, n-1) and R (2, n), and correspondingly, the n-1 row of radio frequency chip units are sequentially R (n-1, 1), R (n-1, 2), … …, R (n-1 ) and R (n-1, n), and the n-th row of radio frequency chip units are sequentially R (n, 1), R (n, 2), … …, R (n, n-1) and R (n, n).

Similarly, the patch antenna group is also an n×n uniform planar array, each antenna element is an array element, the first row of antenna elements are sequentially a (1, 1), a (1, 2), … …, a (1, n-1), a (1, n), the second row of antenna elements are sequentially a (2, 1), a (2, 2), … …, a (2, n-1), a (2, n), and correspondingly, the n-1 row of antenna elements are sequentially a (n-1, 1), a (n-1, 2), … …, a (n-1 ), a (n-1, n), and the n-th row of antenna elements are sequentially a (n, 1), a (n, 2), … …, a (n, n-1), a (n, n).

The connection relationship between the radio frequency chip unit and the antenna unit is that R (1, 1) is connected with A (1, 1), R (1, 2) is connected with A (1, 2), … …, R (1, n) is connected with A (1, n), similarly, R (n, 1) is connected with A (n, 1), R (n, 2) is connected with A (n, 2), … …, R (n, n) is connected with A (n, n), so that each radio frequency chip unit and the corresponding antenna unit form a unique connection relationship. It should be noted that n is a positive integer and is an even number, and the antenna unit is prepared on the hafnium oxide layer by a micro-nano process.

In this specification, each power chip group supplies power to its corresponding radio frequency chip unit, where the radio frequency chip unit corresponding to the first power chip group may include: r (1, 2) to R (1, n-1) and R (2, 2) to R (2, n-1), the radio frequency chip unit corresponding to the second power chip set may include: r (n-1, 2) to R (n-1 ) and R (n, 2) to R (n, n-1).

The radio frequency chip unit corresponding to the third power chip set may include: r (1, 1) to R (n, 1) and R (3, 2) to R (n-3, 2) so that the n/2 th column of radio frequency chip units R (3, n/2) to R (n-3, n/2) are all powered.

The radio frequency chip unit corresponding to the fourth power chip set may include: r (3, n-1) to R (n-3, n-1) and R (1, n) to R (n, n) are such that the n/2+1-th row of radio frequency chip units R (3, n/2+1) to R (n-3, n/2+1) are powered.

In practical applications, the signal processing unit may be additionally powered by two or more power supply chipsets, and in this specification, the signal processing unit may be powered by the first unit chipset and the second power supply chipset.

In addition, in the process of preparing the phased array radar in the specification, a 65nm standard CMOS active device process can be selected, based on process design toolkit (Process Design Kit, PDK) data, according to the connection relation of the radio frequency chip units shown in fig. 2, the functional modules such as a low noise amplifier, a quadrature mixer, a low pass filter, an ADC and the like are set, the radio frequency working frequency is in a Ku wave band, tools such as Cadence, synopsys, mentor and the like are comprehensively utilized, a circuit diagram is designed, then a layout is designed, and the simulation is optimized, and after the setting of the functional modules, the radio frequency chip units are subjected to imposition simulation, and the imposition diagram is stored as a module cell_RF. The method comprises the steps of synchronously carrying out 12V-5V, 5V-1.5V, 5V-1.2V setting and 1.5V-1.2V LDO setting on a DC/DC module, carrying out signal processing unit peripheral circuit design, and respectively storing the layouts of the DC/DC module, the LDO module and the control and signal processing unit module as a module cell_DC, a cell_LDO and a cell_CDSP.

And then, according to fig. 3, the different modules are spliced, wherein the spacing of the cell_rf is 9mm, the two-dimensional area array is arranged on an 8-inch wafer to form a 16×16 array, the cell_dc and the cell_ldo are distributed around the array, 8 cell_rf are provided with power according to each cell_dc and cell_ldo, and the periphery of the array is required to be supplied with power by 32 groups of cell_dc and cell_ldos which are 16×16 arrays. The arrangement modes of all cells are symmetrical, and the central area cell_CDSP is connected through 256 groups of SPI lines.

And then, the arranged layout can be manufactured into a mask, and the manufacturing of the active area of the whole wafer is completed by adopting the processing means of semiconductor active devices through the processes of photoetching, overlay, etching, passivation, oxidation, film plating, metal deposition, ion implantation, implantation doping, diffusion, annealing, electroplating and the like and using a global exposure mode.

Based on the wafer manufactured, a 2um silicon dioxide layer, a metal GND grid layer, a grid coverage rate of 50%, a grid line width of 20um and a thickness of 2um can be prepared layer by layer on the front surface by using a subsequent Damascus process, then a hafnium dioxide layer (with a relative dielectric constant of 22) is deposited, the thickness of 2um is 2um, then a via hole is manufactured, the via hole is filled with metal, and the lower end of the via hole is connected with a low-noise input port of a cell_RF according to the design and manufacture of 50 ohm impedance. And finally, depositing a layer of metal with the thickness of 2um, wherein the metal pattern is a butterfly dipole antenna, which is bilaterally symmetrical, and an excitation port of the antenna is connected with the upper end of the via hole, so that the phased array radar is prepared.

The foregoing describes a phased array radar structure provided in the present specification, and for convenience of understanding, the present specification further provides a flow chart of an information acquisition method based on the phased array radar, as shown in fig. 4.

Fig. 4 is a schematic flow chart of an information acquisition method provided in the present specification, where the method is applied to the phased array radar, and includes the following steps:

s401: and receiving electromagnetic wave signals through the phased array radar, and converting the electromagnetic wave signals to obtain converted signals.

S402: and processing the converted signal to obtain a processed signal.

S403: and acquiring information carried by the electromagnetic wave signal according to the processed signal.

In the present specification, the execution subject for implementing the information acquisition method may be a terminal device corresponding to the phased array radar, and may be a server connected to the phased array radar. For convenience of description, the present specification will explain one information acquisition method provided in the present specification, taking a terminal device as an execution subject only as an example.

The terminal equipment can receive electromagnetic wave signals through the antenna unit and transmit the electromagnetic wave signals to the low-noise amplifier in the radio frequency chip unit, the low-noise amplifier outputs signals to the quadrature mixer, and the quadrature mixer can acquire the signals output by the low-noise amplifier and the self-oscillation signals and perform I/Q modulation after receiving the signals output by the low-noise amplifier and the self-oscillation signals, so that a first quadrature signal (I-path signal) and a second quadrature signal (Q-path signal) which are in quadrature relation with each other are generated and output.

The signals sampled by the ADC (processed signals) are all output to the signal processing unit for processing, and the signal processing unit may perform FFT, convolution, digital filtering, amplitude-phase weighting operation, etc. on the processed signals, so as to obtain the processed signals.

Thus, the terminal device can obtain the information (such as the distance, angle, speed, size, shape, etc.) carried in the received electromagnetic wave signal according to the processed signal.

Of course, in practical application, the phased array radar itself may acquire information carried in the received electromagnetic wave signal according to the processed signal.

The comparison of the phased array radar prepared based on the PCB process and the semiconductor process and having similar performances (only containing a 16×16 uniform area array) with the traditional phased array radar can be seen from the table 1, the phased array radar in the scheme has the advantages of remarkably improved volume, power consumption, weight, reliability, power efficiency and the like, and greatly reduced throughput in terms of cost.

TABLE 1

Therefore, the phased array radar in the specification can solve the problems of large size, high power consumption, excessively complex radio frequency circuits and control circuits, poor system stability and the like of the traditional phased array radar based on the PCB and the integrated circuit, and can also utilize the batch production capacity of the semiconductor technology to greatly reduce the cost.

The present specification also provides a computer-readable storage medium storing a computer program operable to perform an information acquisition method as provided in fig. 4 above.

The present specification also provides a schematic structural diagram of an electronic device corresponding to fig. 4 shown in fig. 5. At the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile storage, as illustrated in fig. 5, although other hardware required by other services may be included. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs to implement the information acquisition method described above with respect to fig. 4. Of course, other implementations, such as logic devices or combinations of hardware and software, are not excluded from the present description, that is, the execution subject of the following processing flows is not limited to each logic unit, but may be hardware or logic devices.

Improvements to one technology can clearly distinguish between improvements in hardware (e.g., improvements to circuit structures such as diodes, transistors, switches, etc.) and software (improvements to the process flow). However, with the development of technology, many improvements of the current method flows can be regarded as direct improvements of hardware circuit structures. Designers almost always obtain corresponding hardware circuit structures by programming improved method flows into hardware circuits. Therefore, an improvement of a method flow cannot be said to be realized by a hardware entity module. For example, a programmable logic device (Programmable Logic Device, PLD) (e.g., field programmable gate array (Field Programmable Gate Array, FPGA)) is an integrated circuit whose logic function is determined by the programming of the device by a user. A designer programs to "integrate" a digital system onto a PLD without requiring the chip manufacturer to design and fabricate application-specific integrated circuit chips. Moreover, nowadays, instead of manually manufacturing integrated circuit chips, such programming is mostly implemented by using "logic compiler" software, which is similar to the software compiler used in program development and writing, and the original code before the compiling is also written in a specific programming language, which is called hardware description language (Hardware Description Language, HDL), but not just one of the hdds, but a plurality of kinds, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), lava, lola, myHDL, PALASM, RHDL (Ruby Hardware Description Language), etc., VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog are currently most commonly used. It will also be apparent to those skilled in the art that a hardware circuit implementing the logic method flow can be readily obtained by merely slightly programming the method flow into an integrated circuit using several of the hardware description languages described above.

The controller may be implemented in any suitable manner, for example, the controller may take the form of, for example, a microprocessor or processor and a computer readable medium storing computer readable program code (e.g., software or firmware) executable by the (micro) processor, logic gates, switches, application specific integrated circuits (Application Specific Integrated Circuit, ASIC), programmable logic controllers, and embedded microcontrollers, examples of which include, but are not limited to, the following microcontrollers: ARC 625D, atmel AT91SAM, microchip PIC18F26K20, and Silicone Labs C8051F320, the memory controller may also be implemented as part of the control logic of the memory. Those skilled in the art will also appreciate that, in addition to implementing the controller in a pure computer readable program code, it is well possible to implement the same functionality by logically programming the method steps such that the controller is in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Such a controller may thus be regarded as a kind of hardware component, and means for performing various functions included therein may also be regarded as structures within the hardware component. Or even means for achieving the various functions may be regarded as either software modules implementing the methods or structures within hardware components.

The system, apparatus, module or unit set forth in the above embodiments may be implemented in particular by a computer chip or entity, or by a product having a certain function. One typical implementation is a computer. In particular, the computer may be, for example, a personal computer, a laptop computer, a cellular telephone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

For convenience of description, the above devices are described as being functionally divided into various units, respectively. Of course, the functions of each element may be implemented in one or more software and/or hardware elements when implemented in the present specification.

It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The present description is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the specification. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

The memory may include volatile memory in a computer-readable medium, random Access Memory (RAM) and/or nonvolatile memory, such as Read Only Memory (ROM) or flash memory (flash RAM). Memory is an example of computer-readable media.

Computer readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of storage media for a computer include, but are not limited to, phase change memory (PRAM), static Random Access Memory (SRAM), dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), read Only Memory (ROM), electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium, which can be used to store information that can be accessed by a computing device. Computer-readable media, as defined herein, does not include transitory computer-readable media (transmission media), such as modulated data signals and carrier waves.

It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.

It will be appreciated by those skilled in the art that embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, the present specification may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present description can take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.

In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for system embodiments, since they are substantially similar to method embodiments, the description is relatively simple, as relevant to see a section of the description of method embodiments.

The foregoing is merely exemplary of the present disclosure and is not intended to limit the disclosure. Various modifications and alterations to this specification will become apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, or the like, which are within the spirit and principles of the present description, are intended to be included within the scope of the claims of the present description.

Claims

1. A phased array radar, the phased array radar comprising: the system comprises a wafer, a signal processing unit, a plurality of power supply chip sets and a plurality of receiving chip sets, wherein each power supply chip set corresponds to at least one receiving chip set;

2. The phased array radar of claim 1, wherein the redistribution layer is fabricated on a top surface of the wafer.

3. The phased array radar of claim 2, wherein the rewiring layer comprises: a silicon dioxide layer, a metal layer and a hafnium oxide layer.

4. The phased array radar of claim 1, wherein for each power chipset, the power chipset comprises: at least one of the DC-DC converter DC-DC unit and the LDO unit.

5. The phased array radar of claim 1, wherein at least four power supply chip sets are included in the phased array radar and power is supplied to the signal processing unit by two of the power supply chip sets.

6. The phased array radar of claim 1, wherein the number of corresponding receive chipsets for each power chipset is the same.

7. The phased array radar of claim 1, wherein for each power chipset, the power chipset is configured to power radio frequency chip units in a receiving chipset to which the power chipset corresponds.

8. The phased array radar of claim 1, wherein the plurality of receive chip sets are disposed within the wafer in a uniform planar array having equal numbers of rows and columns.

9. The phased array radar of claim 1, wherein a low noise amplifier, a quadrature mixer, a power amplifier, a filter, and an analog-to-digital converter ADC are provided in the radio frequency chip unit;

10. The phased array radar of claim 9, wherein the antenna unit is connected to a low noise amplifier in the radio frequency chip unit;

11. The phased array radar of claim 9, wherein the ports of the quadrature mixer comprise a radio frequency input port, a local oscillator input port, a first quadrature output port, and a second quadrature output port;

12. The phased array radar of claim 11, further comprising: a local oscillator and at least two power dividers;

13. The phased array radar of claim 11, wherein the local oscillator input ports in each radio frequency chip unit are of the same frequency and of the same phase for corresponding inputs.

14. The phased array radar of claim 12, wherein the quadrature mixer is configured to receive the signal output by the low noise amplifier and the local oscillation signal, and to generate and output the first quadrature signal and the second quadrature signal based on the signal output by the low noise amplifier and the local oscillation signal.

15. The phased array radar of claim 1, wherein the signal processing unit is further configured to control at least one of the receive chipset and the power chipset based on the processed signal.

16. The phased array radar of claim 3, wherein the antenna elements are disposed on the hafnium oxide layer.

17. The phased array radar of claim 1, wherein the antenna unit comprises: a patch antenna.

18. A method of information acquisition, characterized in that it is applied to the phased array radar of any one of claims 1 to 17, the method comprising:

processing the converted signal to obtain a processed signal;

19. A computer readable storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the method of claim 18.