CN116224296A - Phased array radar and information acquisition method, storage medium and electronic equipment - Google Patents

Abstract

The specification discloses a phased array radar and information acquisition method, a storage medium and electronic equipment. The phased array radar includes: wafer, signal processing unit, a plurality of power supply chip group and a plurality of receiving chip group, wherein, every power supply chip group corresponds at least one receiving chip group, a plurality of power supply chip groups evenly set up around the inside of wafer, signal processing unit sets up the inside central authorities of wafer, to every receiving chip group, this receiving chip group includes: the radio frequency chip unit is arranged in the wafer, the antenna unit is arranged on the upper surface of the wafer right above the radio frequency chip unit, a rewiring layer is arranged above the radio frequency chip unit, and the radio frequency chip unit is connected with the antenna unit arranged on the upper surface of the wafer through the rewiring layer.

Description

A phased array radar and information acquisition method, storage medium and electronic equipment

technical field

This specification relates to the field of radar, in particular to a phased array radar, an information acquisition method, a storage medium and electronic equipment.

Background technique

Phased array radar is a radar that uses a phased array antenna. The phased array antenna is developed from the array antenna used in the initial radar. The directional antenna is composed of many radio frequency units (array elements). The phase distribution of the antenna elements is used to realize the rotation or scanning of the beam pointing in space.

However, the RF receiving unit of the current phased array radar is usually mounted on the Printed Circuit Board (PCB), and the RF receiving unit is connected to the antenna through a long microstrip line or RF cable, resulting in signal power loss larger. Moreover, since all the chips are integrated on the PCB board, the PCB board needs to provide a large deployment area, which makes the power system lose a lot during transmission, and the power usage efficiency is low, which further leads to a larger volume of the phased array radar.

Therefore, how to reduce the size of the phased array radar, reduce the power loss of the signal during transmission, and improve the efficiency of the power supply is an urgent problem to be solved.

Contents of the invention

This specification provides a phased array radar, information acquisition method, storage medium and electronic equipment, so as to partially solve the above-mentioned problems existing in the prior art.

This manual adopts the following technical solutions:

This specification provides a phased array radar, the phased array radar includes: the phased array radar includes: a wafer, a signal processing unit, several power chipsets and several receiving chipsets, wherein each power chip The group corresponds to at least one receiving chipset;

The plurality of power chipsets are evenly arranged around the inside of the wafer, the signal processing unit is arranged in the center of the inside of the wafer, and for each receiving chipset, the receiving chipset includes: a radio frequency chip unit and the An antenna unit corresponding to the radio frequency chip unit, the radio frequency chip unit is arranged inside the wafer, the antenna unit is arranged on the upper surface of the wafer directly above the radio frequency chip unit, and a heavy weight is arranged above the radio frequency chip unit a wiring layer, the radio frequency chip unit is connected to the antenna unit arranged on the upper surface of the wafer through the rewiring layer;

For each power chipset, the power chipset is used to supply power to the receiving chipset corresponding to the power chipset;

The antenna unit is used to receive electromagnetic wave signals and transmit the electromagnetic wave signals to the radio frequency chip unit;

The radio frequency chip unit is used to convert the electromagnetic wave signal to obtain a converted signal, and send the converted signal to the signal processing unit;

The signal processing unit is configured to receive power from at least two power chipsets, and process the converted signal to obtain a processed signal, so as to obtain information carried by the electromagnetic wave signal according to the processed signal .

Optionally, the redistribution layer is prepared on the upper surface of the wafer.

Optionally, the redistribution layer includes: a silicon dioxide layer, a metal layer and a hafnium dioxide layer.

Optionally, for each power chipset, the power chipset includes: at least one of a DC-DC converter DC-DC unit and a low-dropout linear regulator LDO unit.

Optionally, the phased array radar includes at least four power chipsets, and two of the power chipsets are used to supply power to the signal processing unit.

Optionally, each power supply chipset corresponds to the same number of receiving chipsets.

Optionally, for each power chip set, the power chip set is used to supply power to the radio frequency chip unit in the receiving chip set corresponding to the power chip set.

Optionally, the plurality of receiving chip groups are arranged inside the wafer according to a uniform planar array, and the number of rows and columns of the uniform planar array are equal.

Optionally, the radio frequency chip unit is provided with a low noise amplifier, a quadrature mixer, a power amplifier, a filter, and an analog-to-digital converter ADC;

The radio frequency chip unit is used to perform preliminary processing on the electromagnetic wave signal through the low noise amplifier, the quadrature mixer, the power amplifier and the filter, and input the preliminary processed signal into the The ADC is used to obtain the converted signal.

Optionally, the antenna unit is connected to a low noise amplifier in the radio frequency chip unit;

The antenna unit is used to transmit the received electromagnetic wave signal to the low noise amplifier.

Optionally, the ports of the quadrature mixer include a radio frequency input port, a local oscillator input port, a first quadrature output port, and a second quadrature output port;

The radio frequency input port is used to receive the signal output by the low noise amplifier;

The first quadrature output port is used to output a first quadrature signal, and the second quadrature output port is used to output a second quadrature signal, wherein the first quadrature signal and the second quadrature signal The signals are in an orthogonal relationship;

The local oscillator input port is used to receive a local oscillator signal.

Optionally, the phased array radar further includes: a local oscillator and at least two power dividers;

The local oscillator input port is used to receive the output of the local oscillator signal generated by the local oscillator after being processed by each power divider.

Optionally, the local oscillator input ports in each radio frequency chip unit have the same input frequency and the same phase.

Optionally, the quadrature mixer is configured to receive the signal output by the low noise amplifier and the local oscillation signal, and generate and output the the first quadrature signal and the second quadrature signal.

Optionally, the signal processing unit is further configured to control at least one of the receiving chipset and the power chip set according to the processed signal.

Optionally, the antenna unit is disposed on the hafnium dioxide layer.

Optionally, the antenna unit includes: a patch antenna.

This specification provides an information acquisition method, the method is applied to the above-mentioned phased array radar, and the method includes:

receiving an electromagnetic wave signal through the phased array radar, and converting the electromagnetic wave signal to obtain a converted signal;

Processing the converted signal to obtain a processed signal;

The information carried by the electromagnetic wave signal is obtained according to the processed signal.

This specification provides a computer-readable storage medium, the storage medium stores a computer program, and when the computer program is executed by a processor, the above information acquisition method is implemented.

The above-mentioned at least one technical solution adopted in this specification can achieve the following beneficial effects:

The phased array radar in this specification includes: a wafer, a signal processing unit, several power chip groups and several receiving chip groups, wherein each power chip group corresponds to at least one receiving chip group, and the several power chip groups are evenly arranged on Around the inside of the wafer, the signal processing unit is arranged in the center of the wafer, and for each receiving chip set, the receiving chip set includes: a radio frequency chip unit and an antenna unit corresponding to the radio frequency chip unit, The radio frequency chip unit is disposed inside the wafer, the antenna unit is disposed on the upper surface of the wafer directly above the radio frequency chip unit, a rewiring layer is disposed above the radio frequency chip unit, and the radio frequency chip unit passes through The redistribution layer is connected to the antenna unit disposed on the upper surface of the wafer.

It can be seen from the phased array radar above that the power chip set, receiving chip set and signal processing unit of the phased array radar in this solution are all integrated inside the wafer, the antenna unit is set outside the wafer, and each radio frequency unit is connected to the Corresponding antenna units do not need to be connected through microstrip lines or radio frequency cables, which greatly reduces the power loss in the signal transmission process, and compared with the current packaging method through PCB, this solution can be used in a smaller area The same number of chips are set in the wafer, which greatly improves the integration of phased array radar, reduces the volume of phased array radar, and further improves the efficiency of power supply.

Description of drawings

The drawings described here are used to provide a further understanding of this specification and constitute a part of this specification. The schematic embodiments and descriptions of this specification are used to explain this specification and do not constitute an improper limitation of this specification. In the attached picture:

Figure 1a is a schematic diagram of a phased array radar provided in this specification;

Figure 1b is a schematic diagram of a phased array radar provided in this specification;

Figure 2 is a schematic diagram of the circuit structure of a phased array radar provided in this specification;

Fig. 3 is a schematic diagram of a power supply circuit of a power chipset provided in this specification;

FIG. 4 is a schematic flow chart of an information acquisition method provided in this specification;

FIG. 5 is a schematic diagram of an electronic device corresponding to FIG. 4 provided in this specification.

Detailed ways

In order to make the purpose, technical solution and advantages of this specification clearer, the technical solution of this specification will be clearly and completely described below in conjunction with specific embodiments of this specification and corresponding drawings. Apparently, the described embodiments are only some of the embodiments in this specification, not all of them. Based on the embodiments in this specification, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of this specification.

The technical solutions provided by each embodiment of this specification will be described in detail below in conjunction with the accompanying drawings.

Figure 1a and Figure 1b are schematic diagrams of a phased array radar provided in this specification, wherein Figure 1a and Figure 1b are views of the phased array radar on the upper surface of the wafer and views on the side of the wafer respectively.

The phased array radar includes: a wafer, several power chipsets, several receiving chipsets, a signal processing unit and a redistribution layer (not shown in FIG. 1a ).

Each receiving chipset contains a radio frequency chip unit and an antenna unit. The radio frequency chip unit can be prepared inside the wafer by a standard complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) active device process, and the number of rows and columns The number of equal uniform planar arrays is arranged, and the antenna unit in each receiving chip group is located on the upper surface of the wafer directly above the radio frequency unit in the receiving antenna group, so that the radio frequency chip unit in each receiving chip group and its rewiring An antenna element directly above the layer constitutes the only connection relationship.

The rewiring layer can be prepared on the upper surface of the wafer by micro-nano manufacturing technology, including a silicon dioxide layer, a metal layer and a hafnium dioxide layer, and is used to package chips in the wafer.

The antenna unit is arranged on the hafnium dioxide layer in the redistribution layer. The antenna unit can be a patch antenna for receiving electromagnetic wave signals and transmitting the electromagnetic wave signals to the radio frequency chip unit. The conversion is performed and the converted signal is sent to the signal processing unit.

Specifically, each radio frequency chip unit includes a low noise amplifier, a quadrature mixer, a power amplifier, a filter, and an analog to digital converter (Analog to Digital Converter, ADC), and the radio frequency chip unit is used to pass the low noise amplifier, The quadrature mixer, power amplifier and filter conduct preliminary processing on the electromagnetic wave signal, and input the preliminary processed signal into the ADC to obtain a digital signal sampled and converted by the ADC. For ease of understanding, this specification provides a schematic diagram of the circuit structure of a phased array radar, as shown in Figure 2 .

FIG. 2 is a schematic diagram of a circuit structure of a phased array radar provided in this specification.

Among them, the low noise amplifier is connected with the antenna unit. When the antenna unit receives the electromagnetic wave signal, it can transmit the electromagnetic wave signal to the low noise amplifier in the radio frequency chip unit, and the low noise amplifier will output the signal to the quadrature mixer. After receiving the signal output by the low noise amplifier and the local oscillating signal, the cross-mixer can obtain the signal output by the low noise amplifier and the local oscillating signal and perform in-phase/quadrature (I/Q) modulation, Thus, a first quadrature signal (signal I) and a second quadrature signal (signal Q) which are orthogonal to each other are generated and output.

It should be noted that since there are multiple receiving chipsets in this specification, when the number of receiving chipsets is n, the number of radio frequency chip units and antenna units is also n, and each receiving chipset is arranged according to a uniform plane of (n×n) The array is arranged, and only the four receiving chipsets R(1,1), R(1,n), R(n,1), and R(n,n) are shown in Figure 2. For these four receiving chipsets Other chipsets between chipsets are connected in the same manner, which are not shown one by one in FIG. 2 .

In this specification, the quadrature mixer can be provided with four ports, which are respectively a radio frequency input port (RF), a local oscillator input port (LO), a first quadrature output port (I port) and a second quadrature output port. Output port (Q port), the RF input port is used to obtain the signal output by the low noise amplifier, the first quadrature output port is used to output the first quadrature signal, and the second quadrature output port is used to output the second quadrature signal , the local oscillator input port is used to receive the local oscillator signal.

Further, the phased array radar in this specification is also provided with multiple power dividers and local oscillators, and the local oscillators are used to output local oscillation signals. After the local oscillation signals are processed by multi-stage power dividers, The input port is input to a quadrature mixer in each radio frequency chipset. It should be noted that the local oscillator input port in each radio frequency chip unit corresponds to the same input frequency and phase.

For each signal output by the quadrature mixer, the signal is input to the corresponding ADC after preliminary processing by the power amplifier and the filter, and is sampled by the ADC and converted into a digital signal (converted signal) and input to the signal processing unit.

The signal processing unit can be prepared in the middle of the wafer through the standard CMOS active device process, and the signal (processed signal) sampled by the ADC is output to the signal processing unit for processing, and the signal processing unit can quickly process the processed signal Fast Fourier transform (FFT), convolution, digital filtering, amplitude-phase weighting operation, etc., to obtain the processed signal.

In this way, the information carried in the received electromagnetic wave signal (such as the distance, angle, speed, size and shape of the target object, etc.) can be obtained according to the processed signal.

In this specification, the signal processing unit can analyze the processed signal to obtain the information carried in the electromagnetic wave signal. Of course, the processed signal can also be sent to a terminal device or server connected to the phased array radar, so that The processed signal is analyzed by the terminal device or the server to obtain the information carried by the electromagnetic wave signal.

In addition, the signal processing unit can also output a clock signal and a logic signal, so as to control the radio frequency chip unit and the power chip set in each receiving chipset according to the clock signal and the logic signal. For example, the signal processing unit can control when the power chipset starts or stops power supply, and controls when the ADC in the radio frequency chip unit starts or stops sampling and the sampling frequency.

As shown in Figure 1a, the phased array radar in this specification can be provided with four power chipsets, which are the first power chipset, the second power chipset, the third power chipset and the fourth power chipset.

Each power supply chipset is evenly arranged around the inside of the wafer, and is used to supply power to their corresponding receiving chipsets and signal processing units. It should be noted that each power supply chipset in this specification corresponds to at least one receiving chipset , and ensure that the number of receiving chipsets is an integer multiple of the number of power chipsets.

In this specification, the number of receiving chipsets corresponding to each power supply chipset can be the same, wherein each power supply chipset can be prepared inside the wafer through a CMOS active device process, and are evenly arranged on the upper and lower sides of the wafer. , left and right directions.

Each power chipset may include a DC-DC converter (DC-DC) unit and a low dropout regulator (Low Dropout Regulator, LDO) unit, thereby providing a more stable power supply. Of course, in this specification, it is also possible to supply power only through the DC-DC unit or only through the LDO unit. For ease of understanding, this specification also provides a schematic diagram of a power supply circuit of a power chipset, as shown in FIG. 3 .

FIG. 3 is a schematic diagram of a power supply circuit of a power chipset provided in this specification.

Among them, the receiving chipset is an n×n uniform planar array, each radio frequency chip unit is an array element, and the radio frequency chip units in the first row are R(1,1), R(1,2),...,R( 1, n-1), R(1, n), the RF chip units in the second row are R(2, 1), R(2, 2), ..., R(2, n-1), R( 2, n), correspondingly, the radio frequency chip units in row n-1 are R(n-1, 1), R(n-1, 2), ..., R(n-1, n-1), R(n-1, n), the radio frequency chip units in the nth row are R(n, 1), R(n, 2), ..., R(n, n-1), R(n, n).

Similarly, the patch antenna group is also an n×n uniform planar array, each antenna element is an array element, and the antenna elements in the first row are A(1,1), A(1,2),...,A (1, n-1), A(1, n), the antenna elements in the second row are A(2, 1), A(2, 2), ..., A(2, n-1), A( 2, n), correspondingly, the antenna elements in the n-1th row are A(n-1, 1), A(n-1, 2), ..., A(n-1, n-1), A (n-1, n), the antenna elements in the nth row are A(n, 1), A(n, 2), . . . , A(n, n-1), A(n, n).

Among them, the connection relationship between the radio frequency chip unit and the antenna unit is that R(1,1) is connected with A(1,1), R(1,2) is connected with A(1,2), ..., R(1,n ) is connected to A(1, n), similarly, R(n, 1) is connected to A(n, 1), R(n, 2) is connected to A(n, 2), ..., R(n, n) is connected to A(n, n), so that each radio frequency chip unit and its corresponding antenna unit form a unique connection relationship. It should be noted that n is a positive integer and is an even number, and the antenna unit is prepared on the hafnium dioxide layer by a micro-nano process.

In this specification, each power supply chipset supplies power to its corresponding radio frequency chip unit, wherein the radio frequency chip unit corresponding to the first power supply chipset may include: R(1, 2) to R(1, n-1 ) and R(2,2) to R(2,n-1), the radio frequency chip unit corresponding to the second power chip set may include: R(n-1,2) to R(n-1,n-1) and R(n, 2) to R(n, n-1).

The radio frequency chip unit corresponding to the third power chipset may include: R(1,1) to R(n,1) and R(3,2) to R(n-3,2), so that the n/2th column radio frequency Chip units R(3, n/2) to R(n−3, n/2) are all powered.

The radio frequency chip unit corresponding to the fourth power chipset may include: R(3,n-1) to R(n-3,n-1) and R(1,n) to R(n,n), so that the nth The radio frequency chip units R(3, n/2+1) to R(n-3, n/2+1) of the /2+1 columns are all powered.

In practical applications, the signal processing unit may be powered by two or more power chip sets. In this specification, the signal processing unit may be powered by the first unit chip set and the second power chip set.

In addition, in the process of preparing the phased array radar in this manual, the 65nm standard CMOS active device process can be selected, based on the Process Design Kit (PDK) data, according to the RF chip unit shown in Figure 2 The connection relationship of the low-noise amplifier, quadrature mixer, low-pass filter, ADC and other functional modules are set, the RF operating frequency is Ku-band, and the circuit diagram is first designed by using Cadence, Synopsys, Mentor and other tools, and then Design the layout and optimize the simulation. After completing the function module setting, make the RF chip unit imposition and simulation, and save the layout as a module cell_RF. Simultaneously carry out the DC/DC module 12V to 5V, 5V to 1.5V, 5V to 1.2V settings, and 1.5V to 1.2V LDO settings, carry out the peripheral circuit design of the signal processing unit, and integrate the DC/DC module, LDO module and control with the The layout of the signal processing unit modules are respectively stored as modules cell_DC, cell_LDO, and cell_CDSP.

Then splicing different modules according to Figure 3, where the pitch of cell_RF is 9mm, arranged in a two-dimensional array, and arranged in a 16×16 array on an 8-inch wafer, cell_DC and cell_LDO are distributed around the array, according to each cell_DC And cell_LDO provides power for 8 cell_RFs, and 32 groups of cell_DC and cell_LDO are required to supply power for the 16×16 array cell_RF in the periphery. All cells are arranged symmetrically, and the central area cell_CDSP is connected by 256 sets of SPI lines.

Afterwards, the arranged layout can be made into a mask, and the semiconductor active layer can be processed by photolithography, overlay, etching, passivation, oxidation, coating, metal deposition, ion implantation, implant doping, diffusion, annealing, electroplating, etc. The device processing method uses the global exposure method to complete the production of the active area of the entire wafer.

Based on the finished wafer, the back damascene process can be used to prepare a 2um silicon dioxide layer and a metal GND grid layer layer by layer on the front side. The grid coverage is 50%, the grid line width is 20um, and the thickness is 2um. Then deposit a layer of hafnium dioxide (relative dielectric constant 22) with a thickness of 2um, and then make vias, fill the vias with metal, and design and manufacture according to the impedance of 50 ohms, the lower end of the vias and the low noise of cell_RF Connect to the input port. Finally, deposit a layer of metal with a thickness of 2um. The metal pattern is a butterfly dipole antenna, which is symmetrical to the left and right. The excitation port of the antenna is connected to the upper end of the via hole to complete the preparation of the phased array radar.

The above is a description of the structure of a phased array radar provided in this specification. For ease of understanding, this specification also provides a schematic flowchart of an information acquisition method based on the above phased array radar, as shown in FIG. 4 .

FIG. 4 is a schematic flow chart of an information acquisition method provided in this specification. The method is applied to the above-mentioned phased array radar and includes the following steps:

S401: Receive an electromagnetic wave signal through the phased array radar, and convert the electromagnetic wave signal to obtain a converted signal.

S402: Process the converted signal to obtain a processed signal.

S403: Obtain information carried by the electromagnetic wave signal according to the processed signal.

In this specification, the executor used to implement the information acquisition method may be a terminal device corresponding to the phased array radar, and of course, may also be a server connected to the phased array radar. For ease of description, this specification only uses a terminal device as an execution subject as an example to describe a method for obtaining information provided in this specification.

The terminal device can receive the electromagnetic wave signal through the antenna unit, and transmit the electromagnetic wave signal to the low noise amplifier in the radio frequency chip unit. The low noise amplifier will output the signal to the quadrature mixer, and the quadrature mixer receives the output of the low noise amplifier. After the signal and the local oscillating signal, the signal output by the low-noise amplifier and the local oscillating signal can be obtained and I/Q modulation is performed, thereby generating and outputting the first quadrature signal (I signal) and the second quadrature signal which are orthogonal to each other. Quadrature signal (Q signal).

For each signal output by the quadrature mixer, the signal is input to the corresponding ADC after preliminary processing by the power amplifier and the filter, and is sampled by the ADC and converted into a digital signal (converted signal) and input to the signal processing unit.

The signal (processed signal) sampled by the ADC is output to the signal processing unit for processing. The signal processing unit can perform FFT, convolution, digital filtering, amplitude-phase weighting operation and other processing on the processed signal to obtain the processed signal.

In this way, the terminal device can obtain the information carried in the received electromagnetic wave signal (such as the distance, angle, speed, size and shape of the target object, etc.) according to the processed signal.

Of course, in practical applications, the information carried in the received electromagnetic wave signal can also be obtained by the phased array radar itself according to the processed signal.

It can be seen from the phased array radar above that the power chip set, receiving chip set and signal processing unit of the phased array radar in this solution are all integrated inside the wafer, the antenna unit is set outside the wafer, and each radio frequency unit is connected to the Corresponding antenna units do not need to be connected through microstrip lines or radio frequency cables, which greatly reduces the power loss in the signal transmission process, and compared with the current packaging method through PCB, this solution can be used in a smaller area The same number of chips are set in the wafer, which greatly improves the integration of phased array radar, reduces the volume of phased array radar, and further improves the efficiency of power supply.

Based on the evaluation of relevant parameters of the Ku-band digital phased array radar (only 16×16 uniform area array) with similar performance prepared by PCB technology and semiconductor technology, the phased array radar in this scheme is compared with the traditional phased array radar You can refer to Table 1. It can be seen from Table 1 that the phased array radar in this solution has been significantly improved in terms of volume, power consumption, weight, reliability, and power efficiency. In terms of cost, it can be achieved through mass production. The magnitude is reduced.

Table 1

It can be seen that the phased array radar in this manual can not only solve the problem of traditional phased array radars based on PCB circuit boards and integrated circuits, but also have large volume, high power consumption, complex radio frequency lines and control lines, and poor system stability. And other issues, but also use the mass production capacity of the semiconductor process to greatly reduce costs.

This specification also provides a computer-readable storage medium, the storage medium stores a computer program, and the computer program can be used to execute an information acquisition method provided in FIG. 4 above.

This specification also provides a schematic structural diagram of an electronic device shown in FIG. 5 corresponding to FIG. 4 . As shown in FIG. 5 , at the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory, and of course may also include hardware required by other services. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it, so as to realize the information acquisition method described in FIG. 4 above. Of course, in addition to the software implementation, this specification does not exclude other implementations, such as logic devices or the combination of software and hardware, etc., that is to say, the execution subject of the following processing flow is not limited to each logic unit, but can also be hardware or logic device.

For a technical improvement, it can be clearly distinguished whether it is an improvement on hardware (for example, an improvement on circuit structures such as diodes, transistors, switches, etc.) or an improvement on software (improvement on a method flow). However, with the development of technology, the improvement of many current method flows can be regarded as the direct improvement of the hardware circuit structure. Designers almost always get the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that the improvement of a method flow cannot be realized by hardware physical modules. For example, a Programmable Logic Device (Programmable Logic Device, PLD) (such as a Field Programmable Gate Array (Field Programmable Gate Array, FPGA)) is such an integrated circuit, and its logic function is determined by programming the device by a user. It is programmed by the designer to "integrate" a digital system on a PLD, instead of asking a chip manufacturer to design and make a dedicated integrated circuit chip. Moreover, nowadays, instead of making integrated circuit chips by hand, this kind of programming is mostly realized by "logic compiler (logic compiler)" software, which is similar to the software compiler used in program development and writing. The original code must also be written in a specific programming language, which is called a hardware description language (Hardware Description Language, HDL), and there is not only one kind of HDL, but many kinds, such as ABEL (Advanced Boolean Expression Language), AHDL ( Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc., currently the most commonly used is VHDL (Very -High-Speed Integrated Circuit Hardware Description Language) and Verilog. It should also be clear to those skilled in the art that only a little logical programming of the method flow in the above-mentioned hardware description languages and programming into an integrated circuit can easily obtain a hardware circuit for realizing the logic method flow.

The controller may be implemented in any suitable way, for example the controller may take the form of a microprocessor or processor and a computer readable medium storing computer readable program code (such as software or firmware) executable by the (micro)processor , logic gates, switches, Application Specific Integrated Circuit (ASIC), programmable logic controllers, and embedded microcontrollers, examples of controllers include but are not limited to the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20 and Silicone Labs C8051F320, the memory controller can also be implemented as part of the memory's control logic. Those skilled in the art also know that, in addition to realizing the controller in a purely computer-readable program code mode, it is entirely possible to make the controller use logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded The same function can be realized in the form of a microcontroller or the like. Therefore, such a controller can be regarded as a hardware component, and the devices included in it for realizing various functions can also be regarded as structures within the hardware component. Or even, means for realizing various functions can be regarded as a structure within both a software module realizing a method and a hardware component.

The systems, devices, modules, or units described in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementing device is a computer. Specifically, the computer may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or Combinations of any of these devices.

For the convenience of description, when describing the above devices, functions are divided into various units and described separately. Of course, when implementing this specification, the functions of each unit can be implemented in one or more pieces of software and/or hardware.

Those skilled in the art should understand that the embodiments of this specification may be provided as methods, systems, or computer program products. Accordingly, this description may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present description may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The specification is described with reference to flowcharts and/or block diagrams of methods, devices (systems), and computer program products according to embodiments of the specification. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing apparatus to operate in a specific manner, such that the instructions stored in the computer-readable memory produce an article of manufacture comprising instruction means, the instructions The device realizes the function specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

These computer program instructions can also be loaded onto a computer or other programmable data processing device, causing a series of operational steps to be performed on the computer or other programmable device to produce a computer-implemented process, thereby The instructions provide steps for implementing the functions specified in the flow chart or blocks of the flowchart and/or the block or blocks of the block diagrams.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

Memory may include non-permanent storage in computer readable media, in the form of random access memory (RAM) and/or nonvolatile memory such as read only memory (ROM) or flash RAM. Memory is an example of computer readable media.

Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can be implemented by any method or technology for storage of information. Information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash memory or other memory technology, Compact Disc Read-Only Memory (CD-ROM), Digital Versatile Disc (DVD) or other optical storage, Magnetic tape cartridge, tape magnetic disk storage or other magnetic storage device or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, computer-readable media excludes transitory computer-readable media, such as modulated data signals and carrier waves.

It should also be noted that the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes Other elements not expressly listed, or elements inherent in the process, method, commodity, or apparatus are also included. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

Those skilled in the art should understand that the embodiments of this specification may be provided as methods, systems or computer program products. Accordingly, this description may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present description may take the form of a computer program product embodied on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.

The specification may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The present description may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including storage devices.

Each embodiment in this specification is described in a progressive manner, the same and similar parts of each embodiment can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for relevant parts, refer to part of the description of the method embodiment.

The above descriptions are only examples of this specification, and are not intended to limit this specification. For those skilled in the art, various modifications and changes may occur in this description. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this specification shall be included within the scope of the claims of this specification.

Claims (19)

1. A phased array radar, the phased array radar comprising: the system comprises a wafer, a signal processing unit, a plurality of power supply chip sets and a plurality of receiving chip sets, wherein each power supply chip set corresponds to at least one receiving chip set;

the power supply chip sets are uniformly arranged around the inside of the wafer, the signal processing unit is arranged in the center of the inside of the wafer, and the receiving chip sets comprise, for each receiving chip set: the radio frequency chip unit is arranged in the wafer, the antenna unit is arranged on the upper surface of the wafer right above the radio frequency chip unit, a rewiring layer is arranged above the radio frequency chip unit, and the radio frequency chip unit is connected with the antenna unit arranged on the upper surface of the wafer through the rewiring layer;

for each power supply chipset, the power supply chipset is used for supplying power to a receiving chipset corresponding to the power supply chipset;

the antenna unit is used for receiving electromagnetic wave signals and transmitting the electromagnetic wave signals to the radio frequency chip unit;

the radio frequency chip unit is used for converting the electromagnetic wave signals to obtain converted signals and sending the converted signals to the signal processing unit;

the signal processing unit is used for receiving power supply of at least two power supply chip sets, and processing the converted signals to obtain processed signals so as to obtain information carried by the electromagnetic wave signals according to the processed signals.

2. The phased array radar of claim 1, wherein the redistribution layer is fabricated on a top surface of the wafer.

3. The phased array radar of claim 2, wherein the rewiring layer comprises: a silicon dioxide layer, a metal layer and a hafnium oxide layer.

4. The phased array radar of claim 1, wherein for each power chipset, the power chipset comprises: at least one of the DC-DC converter DC-DC unit and the LDO unit.

5. The phased array radar of claim 1, wherein at least four power supply chip sets are included in the phased array radar and power is supplied to the signal processing unit by two of the power supply chip sets.

6. The phased array radar of claim 1, wherein the number of corresponding receive chipsets for each power chipset is the same.

7. The phased array radar of claim 1, wherein for each power chipset, the power chipset is configured to power radio frequency chip units in a receiving chipset to which the power chipset corresponds.

8. The phased array radar of claim 1, wherein the plurality of receive chip sets are disposed within the wafer in a uniform planar array having equal numbers of rows and columns.

9. The phased array radar of claim 1, wherein a low noise amplifier, a quadrature mixer, a power amplifier, a filter, and an analog-to-digital converter ADC are provided in the radio frequency chip unit;

the radio frequency chip unit is used for performing preliminary processing on the electromagnetic wave signal through the low noise amplifier, the quadrature mixer, the power amplifier and the filter, and inputting the signal after preliminary processing into the ADC to obtain the converted signal.

10. The phased array radar of claim 9, wherein the antenna unit is connected to a low noise amplifier in the radio frequency chip unit;

the antenna unit is used for transmitting the received electromagnetic wave signal to the low noise amplifier.

11. The phased array radar of claim 9, wherein the ports of the quadrature mixer comprise a radio frequency input port, a local oscillator input port, a first quadrature output port, and a second quadrature output port;

the radio frequency input port is used for receiving the signal output by the low noise amplifier;

the first orthogonal output port is used for outputting a first orthogonal signal, and the second orthogonal output port is used for outputting a second orthogonal signal, wherein the first orthogonal signal and the second orthogonal signal are in an orthogonal relationship;

the local oscillation input port is used for receiving the local oscillation signal.

12. The phased array radar of claim 11, further comprising: a local oscillator and at least two power dividers;

the local oscillator input port is used for receiving the output of the local oscillator signal generated by the local oscillator after being processed by each power divider.

13. The phased array radar of claim 11, wherein the local oscillator input ports in each radio frequency chip unit are of the same frequency and of the same phase for corresponding inputs.

14. The phased array radar of claim 12, wherein the quadrature mixer is configured to receive the signal output by the low noise amplifier and the local oscillation signal, and to generate and output the first quadrature signal and the second quadrature signal based on the signal output by the low noise amplifier and the local oscillation signal.

15. The phased array radar of claim 1, wherein the signal processing unit is further configured to control at least one of the receive chipset and the power chipset based on the processed signal.

16. The phased array radar of claim 3, wherein the antenna elements are disposed on the hafnium oxide layer.

17. The phased array radar of claim 1, wherein the antenna unit comprises: a patch antenna.

18. A method of information acquisition, characterized in that it is applied to the phased array radar of any one of claims 1 to 17, the method comprising:

receiving electromagnetic wave signals through the phased array radar, and converting the electromagnetic wave signals to obtain converted signals;

processing the converted signal to obtain a processed signal;

and acquiring information carried by the electromagnetic wave signal according to the processed signal.

19. A computer readable storage medium, characterized in that the storage medium stores a computer program which, when executed by a processor, implements the method of claim 18.

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