CN112463718A - Signal recognition processing device - Google Patents
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- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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Abstract
The invention provides a signal identification processing device, which comprises a heterogeneous system on chip (SoC) chip, an embedded Graphic Processor (GPU) chip array formed by stacking embedded GPU chips, an Ethernet exchange chip and a PCIe exchange chip.
Description
Technical Field
The invention relates to the technical field of high-performance signal identification applied to communication and radar reconnaissance equipment, in particular to a signal identification processing device.
Background
In the design of military and civil communication and radar signal reconnaissance equipment, the characteristics of huge calculation amount, limited equipment calculation capacity and huge equipment volume exist, and the characteristics are contradictory to the urgent requirements of high real-time performance, low time delay and good mobility in practical application.
In the prior art, data is often transmitted to a general high-performance operation server for processing, or a huge processor array is formed by stacking an FPGA and a DSP for processing, so that the power consumption and the volume of equipment are large. These solutions have the following disadvantages:
1) if special operation equipment such as an operation server and a data center is adopted for processing, the requirements on the reliability and the real-time performance of a scene needing to be moved by the reconnaissance equipment cannot be effectively met;
2) the method for forming a huge processor array by stacking the FPGA and the DSP has the problems of high equipment power consumption, large volume, difficult development and the like;
3) often, the calculation requirements of the traditional signal identification method and the intelligent identification method cannot be met at the same time.
In view of the above disadvantages of the existing solutions, it is necessary to provide a signal identification processing apparatus with small device size, high integration level, easy implementation, good flexibility and strong expansibility, so as to meet the requirements of signal identification and electronic reconnaissance of communication and radar.
Disclosure of Invention
The technical problem to be solved by the invention is to provide a signal identification processing device, which improves the integration level, designability, flexibility and expansibility of signal identification processing equipment. Therefore, the invention adopts the following technical scheme:
a signal identification processing device is characterized by comprising the following four components:
1-a) a heterogeneous system on chip (SoC) chip, which is used for the functions of system control, data reception, signal preprocessing and data distribution and providing an external application interface;
the heterogeneous system-on-chip internally comprises an ARM multi-core processor and a programmable logic real-time signal processing circuit; tasks configured by the programmable logic real-time signal processing circuit comprise an internal interface connected with an ARM processor in a chip, a high-speed PCIe interface connected with PCIe exchange and signal preprocessing calculation;
the system control function receives an instruction from an external application interface, converts the instruction into a control command in the device, controls the programmable logic real-time signal processing circuit to work through an SoC internal interface in one part, and sends the control command to an embedded Graphic Processor (GPU) chip array through an Ethernet exchange chip in the other part through gigabit Ethernet to control each GPU chip to work;
the data receiving function is used for receiving the original signal to be identified from an external memory and a signal collector through a high-speed optical interface or a high-speed serial data interface;
the signal preprocessing function realizes the sampling rate conversion, frequency point conversion, time domain feature extraction, frequency domain feature extraction and time frequency feature extraction of signals;
the data distribution function is used for sending the original signals to be identified or the preprocessed signals to each embedded GPU chip in the embedded GPU chip array through a PCIe interface and a PCIe exchange chip;
the provided external application interface provides a group of hardware and software interfaces for users to realize management commands and output of the information obtained by identification.
1-b) a plurality of embedded Graphics Processing Unit (GPU) chips for distributed signal recognition algorithm processing;
the multiple embedded Graphic Processor (GPU) chips form parallel computation by stacking to obtain stronger computing capability and better support the realization of an intelligent signal recognition algorithm.
1-c) an Ethernet exchange chip respectively connected to a heterogeneous system on chip (SoC) chip and a plurality of embedded Graphic Processor (GPU) chips for controlling command distribution and signal identification information output;
1-d) one PCIe exchange chip respectively connected to a heterogeneous system-on-chip (SoC) chip and a plurality of embedded Graphic Processor (GPU) chips for distributing signal data to be identified;
the signal identification processing device is characterized in that the heterogeneous system-on-chip and the embedded Graphics Processing Unit (GPU) chip array form a high-integration device capable of simultaneously supporting complex control command processing, hierarchical real-time signal preprocessing, high-speed data channels and deep learning algorithm mass computation.
2-a) the complex control command is processed and runs in an ARM multi-core processor, so that the advantages of the ARM multi-core processor in complex flow control, convenient programming, rich interfaces and the like can be exerted, and the flexible configuration of signal preprocessing and signal identification algorithms is realized;
2-b) the hierarchical real-time signal preprocessing is realized by combining a heterogeneous system-on-chip (SoC) chip and an embedded Graphics Processing Unit (GPU) chip array, and high real-time calculation such as signal sampling frequency, frequency point transformation, time frequency feature extraction and the like is distributed to a programmable logic real-time signal processing circuit for calculation, so that the highest-level real-time processing is realized; the method comprises the following steps of distributing calculation such as parameter configuration, resource scheduling and the like to an ARM multi-core processor to realize real-time processing of a control flow; running a deep learning algorithm for mass calculation on an embedded Graphics Processing Unit (GPU) chip array to realize complex intelligent signal identification algorithm calculation; the real-time processing of the control flow does not directly perform calculation on the original mass data, but needs to meet the real-time requirement of completing a specific task at a certain time node in a certain stage.
2-c) the high-speed data channel is realized by connecting PCIe interfaces of a heterogeneous system-on-chip and a plurality of embedded Graphic Processor (GPU) chips to a PCIe exchange chip, so that real-time data exchange up to hundreds of Gbps can be realized;
2-d) the massive computing power of the deep learning algorithm is provided by a stacked Graphics Processing Unit (GPU) chip array, and distributed signal recognition algorithm operation can be provided.
The scheme can simultaneously meet the requirements of signal real-time preprocessing, high-level real-time calculation and massive deep learning algorithms, and can simultaneously support the traditional signal sorting method based on signal characteristic and template matching and the latest artificial intelligence method. In the scheme, the heterogeneous system on chip (SoC) chip, the embedded Graphics Processing Unit (GPU) chip array and the two-stage high-speed data exchange channel form a heterogeneous signal processing device which is expandable, easy to implement and good in flexibility. Further, the apparatus integrates various processors in a heterogeneous manner, has an extremely high integration level, and makes it possible to miniaturize devices and to reduce power consumption; the introduction of an embedded Graphics Processing Unit (GPU) chip array provides flexible organization and expandability of mass processing capacity; the device supports real-time data exchange at different levels, real-time operation at different levels and massive calculation of future large-scale intelligent recognition algorithm; the method and the device have the advantages that the processes and algorithms of different types of calculation are distributed to different processors to be realized, the respective processing advantages of the heterogeneous processors are exerted, and the development difficulty is reduced.
The invention can simultaneously meet the requirements of signal real-time preprocessing, high-level real-time calculation and massive deep learning algorithms through the integrated design of the heterogeneous processor, and can simultaneously support the traditional signal sorting method based on signal characteristics and template matching and the latest artificial intelligence method.
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Fig. 1 is a block diagram of a signal identification apparatus according to the present invention.
Detailed Description
In order to fully understand the technical content of the present invention, specific embodiments are given below, and the technical solution of the present invention is described and explained in more detail with reference to the accompanying drawings.
Fig. 1 is a block diagram of a signal recognition apparatus according to the present invention, and the hardware components of the signal recognition apparatus include a heterogeneous system on chip (SoC) chip 11, an embedded Graphics Processing Unit (GPU) chip array 12 formed by a plurality of embedded GPU chips 1-n, an ethernet switch chip 13, and a PCIe switch chip 14. Wherein n is a natural number greater than 2.
The heterogeneous system on chip (SoC) chip 11 is used for system control, data reception, signal preprocessing, and data distribution, and provides an external application interface; the heterogeneous system-on-chip 11 internally comprises an ARM multi-core processor 111 and a programmable logic real-time signal processing circuit 112; the tasks that the programmable logic real-time signal processing circuit 112 is configured to include internal interfaces to connect to an on-chip ARM processor, high-speed PCIe interfaces to connect to the PCIe switch chip 14, and signal pre-processing computations.
1-a) the system control function receives an instruction from an external application interface, converts the instruction into a control command in the device, controls the programmable logic real-time signal processing circuit 112 to work through an SoC internal interface in one part, and sends the other part to an embedded Graphics Processing Unit (GPU) chip array 12 through a gigabit ethernet exchange chip 13 to control each GPU chip to work;
1-b) the data receiving function, which is used for receiving the original signal to be identified from an external memory and a signal collector through a high-speed optical interface or a high-speed serial data interface;
1-c) the signal preprocessing function, which realizes the sampling rate conversion, frequency point conversion, time domain feature extraction, frequency domain feature extraction and time frequency feature extraction of signals;
1-d) the data distribution function, which is to realize that the original signal to be identified or the preprocessed signal is sent to each embedded Graphic Processing Unit (GPU) chip in the GPU chip array 12 through a PCIe interface and a PCIe exchange chip 14;
1-e) providing an external application interface, and providing a group of hardware and software interfaces for users to realize management commands and output of the identified information.
The embedded Graphics Processor (GPU) chip array 12 is composed of a plurality of embedded GPU chips for distributed signal recognition algorithm processing. The multiple embedded Graphic Processor (GPU) chips form parallel computation by stacking to obtain stronger computing capability and better support the realization of an intelligent signal recognition algorithm.
The ethernet switching chip 13 implements an ethernet switching function, and is connected to the heterogeneous system on a chip (SoC) chip 11 and the plurality of embedded Graphics Processing Units (GPU) chips, respectively, for control command distribution and signal identification information output.
The PCIe switch chip 14 is connected to a heterogeneous system on chip (SoC) chip 11 and a plurality of embedded Graphics Processing Units (GPU) chips, respectively, and is used for signal data distribution to be identified.
The signal identification processing device is characterized in that the heterogeneous system on chip (SoC) chip 11 and the embedded Graphics Processing Unit (GPU) chip array 12 form a high-integration device capable of simultaneously supporting complex control command processing, hierarchical real-time signal preprocessing, high-speed data channels and deep learning algorithm mass computation.
2-a) the complex control command is processed, and the ARM multi-core processor 111 running in the heterogeneous system on a chip (SoC) 11 can exert the advantages of the ARM multi-core processor in complex flow control, convenient programming, rich interfaces and the like, and realize flexible configuration of signal preprocessing and signal identification algorithms;
2-b) the hierarchical real-time signal preprocessing is realized by combining a heterogeneous system-on-chip (SoC) chip 11 and an embedded Graphics Processing Unit (GPU) chip array 12, and high real-time calculation such as signal sampling frequency, frequency point transformation, time frequency feature extraction and the like is distributed to a programmable logic real-time signal processing circuit 112 for calculation, so that the highest-level real-time processing is realized; parameter configuration and resource scheduling calculation are distributed to the ARM multi-core processor 111, and real-time processing of a control flow is achieved; running a deep learning algorithm for mass calculation on an embedded Graphics Processing Unit (GPU) chip array 12 to realize complex intelligent signal identification algorithm calculation;
2-c) the high-speed data channel is realized by connecting a heterogeneous system on chip (SoC) chip 11 and PCIe interfaces of a plurality of embedded Graphics Processing Unit (GPU) chips to a PCIe switch chip 14, which can realize real-time data exchange up to several hundred Gbps;
2-d) the massive computing power of the deep learning algorithm is provided by a stacked Graphics Processing Unit (GPU) chip array 12, capable of providing distributed signal recognition algorithm operations.
In the above scheme, a heterogeneous system on chip (SoC) chip 11, an embedded Graphics Processing Unit (GPU) chip array 12, and two-stage high-speed data exchange channels 13 and 14 form a heterogeneous signal processing apparatus that is extensible, easy to implement, and highly flexible.
The invention can simultaneously meet the requirements of signal real-time preprocessing, high-level real-time calculation and massive deep learning algorithms through the integrated design of the heterogeneous processor, and can simultaneously support the traditional signal sorting method based on signal characteristics and template matching and the latest artificial intelligence method. In the scheme, the heterogeneous system on chip (SoC) chip, the embedded Graphics Processing Unit (GPU) chip array and the two-stage high-speed data exchange channel form a heterogeneous signal processing device which is expandable, easy to implement and good in flexibility. Further, the apparatus integrates various processors in a heterogeneous manner, has an extremely high integration level, and makes it possible to miniaturize devices and to reduce power consumption; the introduction of an embedded Graphics Processing Unit (GPU) chip array provides flexible organization and expandability of mass processing capacity; the device supports real-time data exchange at different levels, real-time operation at different levels and massive calculation of future large-scale intelligent recognition algorithm; the method and the device have the advantages that the processes and algorithms of different types of calculation are distributed to different processors to be realized, the respective processing advantages of the heterogeneous processors are exerted, and the development difficulty is reduced.
It should be understood that the technical contents of the present invention are further disclosed from the perspective of specific embodiments, which aim to make the contents of the present invention easier to understand, but do not represent embodiments of the present invention and the rights are not limited thereto. The scope of the invention is set forth in the appended claims and all obvious modifications which are within the spirit of the invention are intended to be embraced therein.
Claims (2)
1. A signal identification processing device is characterized by comprising the following four components:
1-a) a heterogeneous system on chip (SoC) chip, which is used for the functions of system control, data reception, signal preprocessing and data distribution and providing an external application interface;
the heterogeneous system-on-chip internally comprises an ARM multi-core processor and a programmable logic real-time signal processing circuit; tasks configured by the programmable logic real-time signal processing circuit comprise an internal interface connected with an ARM processor in a chip, a high-speed PCIe interface connected with a PCIe exchange chip and signal preprocessing calculation;
the system control function receives an instruction from an external application interface, converts the instruction into a control command in the device, controls the programmable logic real-time signal processing circuit to work through an SoC internal interface in one part, and sends the control command to an embedded Graphic Processor (GPU) chip array through an Ethernet exchange chip in the other part through gigabit Ethernet to control each GPU chip to work;
the data receiving function is used for receiving the original signal to be identified from an external memory and a signal collector through a high-speed optical interface or a high-speed serial data interface;
the signal preprocessing function realizes the sampling rate conversion, frequency point conversion, time domain feature extraction, frequency domain feature extraction and time frequency feature extraction of signals;
the data distribution function is used for sending the original signals to be identified or the preprocessed signals to each embedded Graphic Processing Unit (GPU) chip in the GPU chip array through a PCIe interface and a PCIe exchange chip;
the provided external application interface provides a group of hardware and software interfaces for a user to realize management commands and output of information obtained by identification;
1-b) a plurality of embedded Graphics Processing Unit (GPU) chips for distributed signal recognition algorithm processing;
the multiple embedded Graphic Processor (GPU) chips form parallel computation by stacking to obtain stronger computing capability and better support the realization of an intelligent signal identification algorithm;
1-c) an Ethernet exchange chip respectively connected to a heterogeneous system on chip (SoC) chip and a plurality of embedded Graphic Processor (GPU) chips for controlling command distribution and signal identification information output;
1-d) one PCIe exchange chip respectively connected to a heterogeneous system-on-chip (SoC) chip and a plurality of embedded Graphic Processor (GPU) chips for signal data distribution to be identified.
2. The signal recognition processing device of claim 1, wherein the heterogeneous system-on-a-chip and the embedded Graphics Processing Unit (GPU) chip array form a highly integrated device capable of simultaneously supporting complex control command processing, hierarchical real-time signal preprocessing, high-speed data channels, and deep learning algorithm mass computation;
2-a) the complex control command is processed and runs in an ARM multi-core processor, so that the advantages of the ARM multi-core processor in complex flow control, convenient programming and rich interfaces can be exerted, and the flexible configuration of signal preprocessing and signal identification algorithms is realized;
2-b) the hierarchical real-time signal preprocessing is realized by combining a heterogeneous system-on-chip (SoC) chip and an embedded Graphics Processing Unit (GPU) chip array, high real-time calculation is distributed in a programmable logic real-time signal processing circuit for calculation, and the highest-level real-time processing is realized; parameter configuration and resource scheduling calculation are distributed to an ARM multi-core processor, and real-time processing of a control flow is achieved; running a deep learning algorithm for mass calculation on an embedded Graphics Processing Unit (GPU) chip array to realize complex intelligent signal identification algorithm calculation; the high real-time calculation comprises signal sampling frequency, frequency point transformation and time-frequency feature extraction;
2-c) the high-speed data channel is realized by connecting PCIe interfaces of a heterogeneous system on chip (SoC) chip and a plurality of embedded Graphic Processor (GPU) chips to one PCIe exchange chip, so that real-time data exchange of hundreds of Gbps can be realized;
2-d) the massive computing power of the deep learning algorithm is provided by a stacked Graphics Processing Unit (GPU) chip array, and distributed signal recognition algorithm operation can be provided.
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