CN116209256A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

Embodiments of the present disclosure provide a semiconductor device and a method of manufacturing the same, the method of manufacturing including: forming a contact hole in a semiconductor substrate; depositing a first contact material on the side wall and the bottom of the contact hole to form a first contact layer; performing an ion implantation process on the first contact layer; the ion implantation process comprises multiple ion implantation steps, wherein in each ion implantation step, an ion beam and a perpendicular line of a plane where the semiconductor substrate is located form a first preset angle, and the semiconductor substrate is rotated around the perpendicular line by a second preset angle after each ion implantation step; depositing a second contact material filling the contact hole on the surface of the first contact layer to form a second contact layer; and carrying out heat treatment on the semiconductor substrate to repair the first contact layer and the second contact layer.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The present disclosure relates to the field of semiconductor technology, and in particular, to a semiconductor device and a method of manufacturing the same.

Background

The dynamic random access memory (Dynamic Random Access Memory, abbreviated as DRAM) is a common memory device, which has the characteristics of high integration level, high read-write speed, low price and the like, and is widely applied to various consumer electronic products such as computers, mobile phones, set top boxes and the like. In the DRAM, a metal line, a capacitor, and the like are connected to an active region through a contact plug. With the shrinking integrated circuits and increasing market demands on DRAM performance, there is a need for contact plugs with better electrical performance, and thus fewer defects in the contact plug are structurally required, which presents new challenges to the existing contact plug process.

Disclosure of Invention

According to a first aspect of the present disclosure, there is provided a method of manufacturing a semiconductor device, comprising:

forming a contact hole in a semiconductor substrate;

depositing a first contact material on the side wall and the bottom of the contact hole to form a first contact layer; the method comprises the steps of carrying out a first treatment on the surface of the

Performing an ion implantation process on the first contact layer; the ion implantation process comprises multiple ion implantation steps, wherein in each ion implantation step, an ion beam and a perpendicular line of a plane where the semiconductor substrate is located form a first preset angle, and the semiconductor substrate is rotated around the perpendicular line by a second preset angle after each ion implantation step;

depositing a second contact material filling the contact hole on the surface of the first contact layer to form a second contact layer;

and carrying out heat treatment on the semiconductor substrate to repair the first contact layer and the second contact layer.

In some embodiments, the first preset angle is 30 ° to 60 °; the second preset angle is 20 °, 30 °, 45 °, 60 °, 90 ° or 180 °.

In some embodiments, the performing an ion implantation process on the first contact layer includes:

carrying out ion implantation on the first contact layer for N times, wherein N is a positive integer; the second preset angle is gamma, and the product of N and gamma is 360 degrees.

In some embodiments, the number of contact holes is a plurality; the performing an ion implantation process on the first contact layer further includes:

and in each ion implantation, moving the semiconductor substrate along a preset direction until the first contact layers in the contact holes are implanted with ions, wherein the preset direction is parallel to the plane of the semiconductor substrate.

In some embodiments, the implanted ions comprise at least one of germanium, arsenic, and indium.

In some embodiments, the material of the first contact layer comprises silicon or germanium;

the material of the second contact layer comprises doped silicon or doped germanium.

In some embodiments, a second contact material is filled in the contact hole, and in the step of forming a second contact layer, a gap is formed in the second contact layer;

after the heat treatment step, the gap is filled with the repaired first contact layer and the repaired second contact layer.

In some embodiments, the forming a contact hole in a semiconductor body substrate includes:

providing a substrate; the substrate comprises a plurality of active areas which are isolated from each other and are arranged in an array, wherein the active areas comprise a source electrode area and a drain electrode area;

forming a dielectric layer and a mask layer which are sequentially stacked on the substrate;

the contact hole penetrating the mask layer and the dielectric layer and extending into the source region or the drain region is formed.

In some embodiments, the method of manufacturing further comprises:

etching the repaired first contact layer and the repaired second contact layer back until the top surfaces of the repaired first contact layer and the repaired second contact layer are flush with the top surface of the dielectric layer;

removing the mask layer;

forming a bit line material layer covering the dielectric layer, the repaired first contact layer and the repaired second contact layer;

etching the bit line material layer to form a bit line extending along a first direction, and etching the repaired first contact layer and second contact layer to form a contact plug; wherein the first direction is parallel to the plane of the semiconductor substrate.

According to a second aspect of the present disclosure, there is provided a semiconductor device comprising:

a semiconductor substrate;

the contact plug extends into the semiconductor substrate and comprises a first contact part and a second contact part, the first contact part covers the side wall and the bottom of the second contact part, and the second contact part contains doping ions.

The manufacturing method of the semiconductor device is used for eliminating gaps existing in the existing contact plugs. The manufacturing method provided by the embodiment of the disclosure comprises the steps of firstly carrying out ion implantation on the first contact layer and then forming the second contact layer. The process sequence can improve the distribution depth of the implanted ions in the contact hole, can enable the depth of the implanted ions in the contact hole to be larger than the depth of the gap, and is easy to repair the gap near the bottom of the contact hole. In the ion implantation process of the embodiment, ion implantation is performed on the first contact layer for a plurality of times, and in each ion implantation, the perpendicular line of the plane where the ion beam and the semiconductor substrate are located forms a first preset angle, so that the contact area between the ion beam and the side wall of the first contact layer in the contact hole can be increased, and the implantation area and the implantation depth of the ion beam on the side wall of the first contact layer are improved; after each ion implantation, the semiconductor substrate is rotated around the vertical line by a second preset angle, so that the implanted ions in the first contact layer in the contact hole can be distributed more uniformly. By the ion implantation process, the uniformity and implantation depth of the distribution of the implanted ions on the side wall and the bottom of the first contact layer in the contact hole can be improved, so that the ion implantation area of the first contact layer is recrystallized after heat treatment, the ion implantation area and the first contact layer and the second contact layer nearby the ion implantation area are repaired to fill gaps, the density of the contact plug is improved, and the electrical performance of the contact plug is improved.

Drawings

Fig. 1a to 1f are schematic structural views of a semiconductor device in a manufacturing process according to an embodiment of the present disclosure;

fig. 2 shows the range of germanium ions as a function of the energy of the implanted ions;

fig. 3 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the disclosure;

fig. 4a to 4g are schematic structural views of yet another semiconductor device provided in an embodiment of the present disclosure during a fabrication process;

fig. 5 is a schematic cross-sectional view of a contact hole along an X direction according to an embodiment of the disclosure;

fig. 6 is a schematic structural diagram of an ion implantation apparatus according to an embodiment of the present disclosure;

fig. 7 is a schematic diagram of ion implantation of a semiconductor substrate using the ion implantation apparatus shown in fig. 6 according to an embodiment of the present disclosure;

FIG. 8 is a schematic diagram of ion implantation of a semiconductor substrate using the ion implantation apparatus of FIG. 6, in accordance with an embodiment of the present disclosure;

fig. 9 is a schematic diagram of a semiconductor substrate placement manner according to an embodiment of the disclosure;

fig. 10 is a schematic diagram of an ion beam implantation process according to an embodiment of the present disclosure;

FIG. 11 is a schematic diagram of a rotation of a semiconductor substrate according to an embodiment of the disclosure;

fig. 12a to 12d are schematic views sequentially showing the distribution of implanted ions in the first contact layer in the hole in the case of performing ion implantation on the first contact layer 1 time, 4 times, 8 times and more than 8 times in the ion implantation process;

fig. 13 is a schematic flow chart of an ion implantation process according to an embodiment of the disclosure;

fig. 14a is a schematic top view of a semiconductor device according to an embodiment of the disclosure;

fig. 14B is a schematic cross-sectional view of the semiconductor device shown in fig. 14a along line B-B.

Detailed Description

The following describes the technical scheme of the present disclosure in detail with reference to the drawings and specific embodiments.

In the description of the present disclosure, it should be understood that the terms "length," "width," "depth," "upper," "lower," "outer," and the like indicate an orientation or a positional relationship based on that shown in the drawings, and are merely for convenience in describing the present disclosure and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present disclosure.

Fig. 1a to 1f are schematic structural diagrams of a semiconductor device according to an embodiment of the present disclosure in a manufacturing process. Fig. 1a is a schematic top view of a substrate, and fig. 1b to 1e are schematic cross-sectional views of the semiconductor device along line A-A (i.e., along the Y direction). As shown in fig. 1a, the substrate 100 includes a plurality of active regions 110 isolated from each other and arranged in an array, and a shallow trench isolation structure 120 is disposed between adjacent active regions 110. The active regions 110 are used to form transistors, and each active region 110 may include one or two transistors. In some embodiments, as shown in fig. 1a, each active region 110 includes two transistors arranged in parallel, two word lines 130 extending in the X direction extend through one active region 110 in parallel, the portion of the active region 110 between the two word lines 130 is the drain region 111 (or the source region 112) of the two transistors for connection to a bit line, and the portion of the active region 110 outside of each word line 130 is the source region 112 (or the drain region 111) of each transistor for connection to a capacitor. The DRAM may be configured as a 1T1C memory cell with one transistor and one capacitor, and the voltage signal on the word line can control the transistor to be turned on or off, thereby reading data in the capacitor through the bit line, or writing data into the capacitor through the bit line.

In the DRAM, the bit line may be drawn out through a bit line contact plug. The bottom of the bit line contact plug is connected to the drain region 111 (or the source region 112), and the top of the bit line contact plug is provided with a bit line extending in the Y direction. Fig. 1b to 1f illustrate a process of forming a bit line contact plug.

As shown in fig. 1b, a dielectric layer 200 and a mask layer 400 are sequentially stacked on a substrate 100; wherein the dielectric layer 200 is used to isolate the bit lines from the substrate 100. Illustratively, dielectric layer 200 includes a first sub-dielectric layer 210 and a second sub-dielectric layer 220 that are sequentially stacked from bottom to top. The mask layer 400 includes a first sub-mask layer 410 and a second sub-mask layer 420 stacked in order from bottom to top. In addition, a word line isolation layer 140 is further disposed on top of the word line 130, and the word line isolation layer 140 is located between the word line 130 and the dielectric layer 200.

With continued reference to fig. 1b, a plurality of contact holes 500 are formed through the mask layer 400 and the dielectric layer 200 and extending to the drain region 111 (or the source region 112). The contact hole 500 is used to form a bit line contact plug in a subsequent process.

Next, a first contact material is deposited on the sidewalls and bottom of the contact hole 500, forming a first contact layer 610. It should be appreciated that the first contact layer 610 would also cover the top of the mask layer 400.

Referring to fig. 1c, the deposition of the second contact material continues within the contact hole 500, forming a second contact layer 620.

Referring to fig. 1d, the first contact layer 610 and the second contact layer 620 are etched back until the tops of the first contact layer 610 and the second contact layer 620 are flush with the top of the first sub-mask layer 410.

In some embodiments, when the first contact material and the second contact material are grown in a Low pressure chemical vapor deposition furnace using a Low pressure chemical vapor deposition process (Low-pressure CVD), the second contact material cannot completely fill the remaining space of the contact hole 500, such that a gap 520 as shown in fig. 1c appears in the second contact layer 620 and/or between the first contact layer 610 and the second contact layer 620. As shown in fig. 1d, the gap 520 remains after the etching back, resulting in a decrease in the conductivity of the finally formed bit line contact plug.

One approach is to implant ions into the first contact layer 610 and the second contact layer 620 after the etch back in fig. 1e, as shown in fig. 1e and 1 f. In fig. 1e, the arrow above the first contact layer 610 represents the ion beam, and the direction indicated by the arrow represents the direction in which the ion beam is implanted into the semiconductor substrate. In the ion implantation process shown in fig. 1e, the ion beam is perpendicular to the plane of the semiconductor substrate.

As shown in fig. 1f, the device is annealed and the gap is repaired by annealing.

In the conventional ion implantation process, the ion implantation energy is generally 7.5KeV to 8.5KeV, and the dosage is 3.5E15ions/cm ² To 4.5E15ions/cm ² . The range of the implanted ions within the first contact layer 610 and the second contact layer 620 is about 10nm. The range is understood to be the distance that the implanted ions travel within the target (i.e., within the first contact layer 610 and the second contact layer 620). The range is related to the energy of the implanted ions. Fig. 2 shows the relationship between the range of germanium ions and the energy of the implanted ions, and generally the larger the energy of the implanted ions, the larger the range of ions.

With continued reference to FIG. 1e, the depth H of the bit line contact plug ₁ About 30nm to 35nm, and the range of the implanted ions in the first contact layer 610 and the second contact layer 620 is about 10nm, which is smaller than the depth of the bit line contact plug, so that as shown in fig. 1f, the implanted ions can repair the gap 520 in a certain depth of the surface layer of the bit line contact plug, and cannot repair the gap 520 near the bottom. However, if the ion implantation energy or dose is increased, the electrical performance of the bit line contact plug is affected. The ion implantation is performed on the first contact layer 610 of the memory array region, but at the same time, the active region of the peripheral region is not provided with a barrier layer before the ion implantation, that is, when the ion implantation is performed on the first contact layer 610 of the memory array region, the active region of the peripheral region is also implanted with ions. If the ion implantation dose is increased, the electrical performance of the transistor formed by the active region of the peripheral region is abnormal.

Based on this, the embodiment of the disclosure provides a manufacturing method of a semiconductor device. Fig. 3 is a schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the disclosure. As shown in fig. 3, the manufacturing method of the semiconductor device includes:

s100: forming a contact hole in a semiconductor substrate;

s200: depositing a first contact material on the side wall and the bottom of the contact hole to form a first contact layer;

s300: performing an ion implantation process on the first contact material layer; the ion implantation process comprises multiple ion implantation steps, wherein in each ion implantation step, an ion beam forms a first preset angle with a vertical line of a plane where the semiconductor substrate is located, and the semiconductor substrate is rotated around the vertical line by a second preset angle after each ion implantation step;

s400: depositing a second contact material filling the contact hole on the surface of the first contact layer to form a second contact layer;

s500: and performing heat treatment on the semiconductor substrate to repair the first contact layer and the second contact layer.

Fig. 4a to 4g are schematic structural views of yet another semiconductor device according to an embodiment of the present disclosure during a fabrication process. A method of manufacturing a semiconductor device provided in an embodiment of the present disclosure will be described below with reference to fig. 4a to 4 g.

Referring to fig. 4a, step S100 is performed to form a contact hole 500 in a semiconductor substrate.

For example, the semiconductor substrate is similar to the semiconductor substrate shown in fig. 1b, the semiconductor substrate comprises a substrate 100, the substrate 100 comprises active regions which are isolated from each other and are arranged in an array, the word lines 130 extend along the X direction and pass through the active regions, and the portions of the active regions located at two sides of each word line 130 are respectively a drain region 111 and a source region.

Next, a dielectric layer 200 and a mask layer 400 are sequentially stacked from bottom to top on the substrate 100. Illustratively, the dielectric layer 200 may include a plurality of layer structures. In this embodiment, the dielectric layer 200 includes a first sub-dielectric layer 210 and a second sub-dielectric layer 220 sequentially stacked from bottom to top. The material of the first sub-dielectric layer may comprise silicon oxide and the material of the second sub-dielectric layer may comprise silicon nitride. Illustratively, the mask layer 400 may include a plurality of layer structures. In this embodiment, the mask layer 400 includes a first sub-mask layer 410 and a second sub-mask layer 420 sequentially stacked from bottom to top. The material of the first sub-mask layer 410 may include polysilicon and the material of the second sub-mask layer 420 may include silicon oxide.

Illustratively, the contact hole 500 extends through the mask layer 400 and the dielectric layer 200 and into the drain region 111 (or source region).

Referring to fig. 4b, step S200 is performed to deposit a first contact material on the sidewalls and bottom of the contact hole, forming a first contact layer 610.

Since the contact hole extends through the dielectric layer 200 and into the substrate 100, there are multiple materials on the sidewall of the contact hole, such as three materials of silicon (substrate 100), silicon oxide (first sub-dielectric layer 210) and silicon nitride (second sub-dielectric layer 220) on the sidewall of the contact hole 500 in fig. 4 a. If the second contact material (e.g., doped silicon) is deposited directly on the sidewalls of the contact hole, the second contact material grows at a different rate on the surfaces of the three materials, which results in early sealing where the growth rate is faster, resulting in larger gaps in the contact plugs, and a reduction in electrical performance. Thus, in some embodiments, the material of the first contact layer 610 includes undoped silicon or undoped germanium, such as undoped polysilicon. Undoped silicon (or undoped germanium) can be deposited on the side wall and the bottom of the contact hole more uniformly, so that the side wall of the contact hole is modified, the deposition of the second contact material is facilitated, and the reduction of gaps in the contact plug is facilitated.

In some embodiments, the first contact material may be grown using a low pressure chemical vapor deposition process. For example, a first contact material may be prepared by supplying silane (SiH 4) gas into a low pressure chemical vapor deposition furnace tube as a raw material.

In some embodiments, the thickness of the first contact layer 610 ranges from 5nm to 6.5nm. And the contact hole 500 has a top width W in a cross-sectional view along the Y-direction (as shown in fig. 4 a) ₁ About 30nm to 40nm, bottom width W ₂ About 25nm to 35nm. Fig. 5 shows a schematic cross-sectional view of the contact hole 500 in the X-direction. Top width W of contact hole 500 in cross-section along X-direction ₃ About 45nm to 55nm, bottom width W ₄ About 35nm to 45nm. It can be seen that after the first contact layer 610 is formed, the contact hole 500 is not filled, and the aperture 510 is also present in the contact hole 500.

Referring to fig. 4c, step S300 is performed to perform an ion implantation process on the first contact layer 610 within the aperture 510. The ion implantation process comprises multiple ion implantation steps, wherein in each ion implantation step, a first preset angle theta is formed between an ion beam and a perpendicular L of a plane of the semiconductor substrate, and the semiconductor substrate is rotated around the perpendicular L by a second preset angle gamma after each ion implantation step.

Here, in fig. 4c, an arrow above the first contact layer 610 represents an ion beam, and a direction indicated by the arrow represents a direction in which the ion beam is implanted into the semiconductor substrate. The ion beam in both directions in fig. 4c represents the direction of the ion beam during the two ion implantations, and after the first ion implantation, the semiconductor substrate is rotated 180 ° and then the second ion implantation is performed.

Fig. 6 is a schematic structural diagram of an ion implantation apparatus according to an embodiment of the present disclosure. As shown in fig. 6, the ion implantation apparatus comprises an ion source (not shown), an accelerator (not shown), and a scanning system 710. The ion beam 720 generated by the ion source is passed through an accelerator to gain sufficient energy and then enters the scanning system 710. The scanning system 710 includes two scanning electrodes 711 disposed opposite to each other, and the deflection angle of the ion beam 720 is continuously changed by continuously adjusting the voltage of the scanning electrode 710 when the ion beam 720 passes between the two scanning electrodes 711, thereby scanning the surface of the semiconductor substrate 10 along the scanning direction D1 (e.g., horizontal direction).

Fig. 7 is a schematic view of ion implantation using the ion implantation apparatus shown in fig. 6. In order to achieve the first preset angle θ between the ion beam 720 and the perpendicular L of the plane of the semiconductor substrate 10, in some embodiments, as shown in fig. 7, the semiconductor substrate 10 may be inclined to be disposed at a first preset angle θ away from the vertical (Z direction) in the plane of the semiconductor substrate 10, where the angle between the perpendicular L of the plane of the semiconductor substrate 10 and the horizontal direction is equal to the first preset angle θ. The ion beam 720 is implanted into the semiconductor substrate 10 in a manner parallel to the horizontal direction, so that the ion beam 720 can form a first preset angle θ with the perpendicular L to the plane of the semiconductor substrate 10.

Here, it should be noted that the first preset angle θ between the ion beam 720 and the perpendicular L of the plane of the semiconductor substrate 10 includes two modes, that is, the plane of the semiconductor substrate 10 is deviated from the vertical direction by the first preset angle θ clockwise as shown in fig. 7, and in other embodiments, the plane of the semiconductor substrate 10 may be deviated from the vertical direction by the first preset angle θ counterclockwise as shown in fig. 8.

Here, as shown in fig. 9, the plane of the semiconductor substrate 10 may be deviated from the vertical direction clockwise, which means that the angle between the plane of the semiconductor substrate 10 and the vertical direction is negative θ (- θ). The plane of the semiconductor substrate 10 is deviated from the vertical direction in the anticlockwise direction, and the included angle between the plane of the semiconductor substrate 10 and the vertical direction is represented as positive θ (+θ). That is, during ion implantation, the plane of the semiconductor substrate 10 may deviate from the vertical direction by positive θ or negative θ, so that the ion beam 720 forms positive θ or negative θ with the perpendicular L to the plane of the semiconductor substrate 10.

Fig. 10 is a schematic diagram of yet another ion beam implantation process provided by an embodiment of the present disclosure. In other embodiments, as shown in fig. 10, during the ion implantation process, the semiconductor substrate 10 may be placed such that the plane of the semiconductor substrate 10 is parallel to the vertical direction, and the perpendicular L of the plane of the semiconductor substrate 10 is along the horizontal direction. The ion beam 720 is incident on the semiconductor substrate 10 at a first predetermined angle θ inclined from the horizontal, so that the ion beam 720 forms a first predetermined angle θ with respect to a perpendicular L to the plane of the semiconductor substrate 10.

The ion beam is injected into the aperture 510 in a plane perpendicular to the semiconductor substrate. In this embodiment, the ion implantation is performed at the first preset angle θ formed by the perpendicular to the plane of the semiconductor substrate and the ion beam, so that the contact area between the ion beam and the sidewall of the aperture 510 can be increased, thereby increasing the implantation area and implantation depth of the ion beam in the sidewall of the aperture 510, and improving the uniformity of the distribution of the implanted ions on the sidewall and bottom of the aperture 510.

In some embodiments, the first preset angle θ ranges from 30 ° to 60 °, i.e., greater than or equal to 30 °, and less than or equal to 60 °. This results in a more uniform distribution of implanted ions on the sidewalls and bottom of the aperture 510.

In some embodiments, to make the distribution of the implanted ions within the aperture more uniform along the circumferential first contact layer of the aperture, step S300 may specifically include:

carrying out ion implantation on the first contact layer for N times, wherein N is a positive integer; the second preset angle is gamma, and the product of N and gamma is 360 degrees.

In some embodiments, N may be 2, 4, 6, 8, 12, 18, …, meaning that the ion implantation process may include 2, 4, 6, 8, 12, 18 or more ion implantations, each time followed by 180 °, 90 °, 60 °, 45 °, 30 °, 20 ° … of the rotation angle of the semiconductor substrate (i.e., the second predetermined angle γ).

Taking N as 4 as an example, in the ion implantation process, the first contact layer 610 is implanted 4 times, and the semiconductor substrate is rotated 90 ° around the vertical line L after each implantation is completed. The semiconductor substrate is not rotated every time the ion implantation is performed, but is rotated after the ion implantation is completed.

In some embodiments, the perpendicular L passes through the center of the semiconductor substrate. Illustratively, the semiconductor substrate is a wafer, and the perpendicular line L passes through the center of the wafer.

Fig. 11 is a schematic view showing the semiconductor substrate rotated along the vertical line L. Fig. 12a to 12d sequentially show distribution representations of implanted ions in the first contact layer 610 in the aperture 510 in the case of performing ion implantation on the first contact layer 1, 4, 8, and more than 8 times in the ion implantation process. Referring to fig. 12a, for one aperture, as the ion beam moves along its scan direction D1 and is injected into aperture 510, the sidewall regions within aperture 510 perpendicular to scan direction D1 are implanted with a greater concentration of ions, while the sidewall regions parallel to scan direction D1 are implanted with a lesser concentration of ions. The concentration of implanted ions is also smaller in the middle region of the aperture 510 due to the greater depth. In addition, as shown in fig. 4c, since the ion beam forms a first preset angle θ with the perpendicular to the plane of the semiconductor substrate, a shadow effect is likely to exist, so that the ion concentration of the side wall of the aperture 510 toward the ion beam is high, and the ion concentration of the shadow region is low. So that if ion implantation is performed only once, the distribution of implanted ions within the first contact layer along the circumference of the aperture 510 is non-uniform.

Referring to fig. 11 and 12b, after the semiconductor substrate is rotated 3 times along the vertical line L to perform ion implantation on the first contact layer 4 times, each region of the sidewall of the aperture 510 may have an opportunity to face the ion beam, each region may have an opportunity to be perpendicular to the scanning direction D1, so that the distribution of the implanted ions in the aperture 510 may be more uniform than one implantation. Referring to fig. 12c and 12d, as the number of ion implantations increases, the distribution of implanted ions within the first contact layer 610 along the circumference of the aperture within the aperture 510 is more uniform.

In this embodiment, in the ion implantation process, the first contact layer 610 in the aperture 510 is ion implanted in a plurality of times, and the semiconductor substrate is rotated around the vertical line by the second preset angle γ after each ion implantation, so that the distribution of the implanted ions in the first contact layer 610 along the aperture circumference in the aperture 510 is more uniform.

It should be appreciated that the product of N and γ may also be a positive integer multiple of 360 °, for example 720 °.

In some implementations, a semiconductor substrate (e.g., a wafer) is used to fabricate a plurality of semiconductor devices, and each region of the semiconductor substrate used to form the semiconductor devices may include a plurality of active regions that are independent of each other and are arranged in an array. Correspondingly, the number of the contact holes is a plurality of. In order to implant ions into the first contact layer in each contact hole on the semiconductor substrate, the step S300 may specifically include:

in each ion implantation, the semiconductor substrate is moved along a preset direction until the first contact layer in the contact holes is implanted with ions, wherein the preset direction is parallel to the plane of the semiconductor substrate.

For example, the moving direction (i.e., the preset direction) of the semiconductor substrate 10 may be moved up and down in parallel to the plane thereof, as in the D2 direction in fig. 6. The direction of movement D2 of the semiconductor substrate may be perpendicular to the scanning direction D1 of the ion beam 720.

In some embodiments, the scanning operation of the ion beam along the scanning direction D1 and the movement of the semiconductor substrate along the predetermined direction D2 are not performed simultaneously, i.e. the ion beam moves once along the predetermined direction D2 after completing one scan along the scanning direction D1, until the entire surface of the semiconductor substrate is scanned, and then one ion implantation is completed.

Fig. 13 is a schematic flow chart of an ion implantation process according to an embodiment of the disclosure. The following describes the process of the ion implantation process provided in the embodiments of the present disclosure in conjunction with the flowchart. The ion implantation process shown in the flowchart includes performing ion implantation 4 times on the first contact layer 610. As shown in fig. 13, step S310 is performed first, and the first contact layer 610 in the aperture 510 is subjected to a first ion implantation; the ion beam 720 forms a first predetermined angle θ with a perpendicular L to the plane of the semiconductor substrate. The ion beam 720 is moved along the scan direction D1 and the semiconductor substrate is moved along the preset direction D2 until the entire surface of the semiconductor substrate is scanned.

Next, step S320 is performed to rotate the semiconductor substrate by a second preset angle γ around the vertical line L.

Next, step S330 is performed to perform a second ion implantation on the first contact layer 610 in the aperture 510; the second ion implantation is the same as the first ion implantation, and the ion beam 720 forms a first predetermined angle θ with respect to a perpendicular L to the plane of the semiconductor substrate. The ion beam 720 is moved along the scan direction D1 and the semiconductor substrate is moved along the preset direction D2 until the entire surface of the semiconductor substrate is scanned.

Then, step S340 is performed to rotate the semiconductor substrate around the vertical line L by a second preset angle γ in the same rotation direction.

Then, step S350 is performed to perform a third ion implantation on the first contact layer 610 in the aperture 510; the third ion implantation is the same as the first ion implantation, and thus will not be described in detail.

Step S360 is performed to rotate the semiconductor substrate around the vertical line L by a second predetermined angle γ in the same rotation direction.

Finally, step S370 is performed to perform a fourth ion implantation on the first contact layer 610 in the aperture 510; the fourth ion implantation is the same as the first ion implantation, and thus will not be described in detail.

After the step S370 is performed, the ion implantation process is completed, and the first contact layer 610 in the aperture 510 is uniformly implanted with ions. It should be appreciated that during the ion implantation process, the first contact layer 610 on top of the mask layer 400 is also implanted with ions.

In some embodiments, the ion implantation energy is in the range of 7.5 to 8.5KeV and the implantation dose is in the range of 3.8E15ions/cm ² To 4.2E15ions/cm ² It is ensured that the range and concentration of the implanted ions in the first contact layer 610 are satisfactory.

In some embodiments, the relative atomic mass of the implanted ions is greater than or equal to 70. For example, the implanted ions include at least one of germanium (Ge), arsenic (As), and indium (In).

Next, referring to fig. 4d, step S400 is performed to fill the second contact material in the pores 510, thereby forming a second contact layer 620.

In some embodiments, the material of the second contact layer 620 includes doped silicon or doped germanium. For example doped polysilicon. The main function of the second contact layer 620 is to conduct the bit line and the drain region (or the source region), and the second contact layer 620 is doped silicon or doped germanium, so that the conductivity of the second contact layer 620 can be ensured to meet the requirement.

In some embodiments, the second contact material may be grown using a low pressure chemical vapor deposition process. For example, a second contact material may be prepared by supplying silane (SiH 4) gas and dopant source gas into a low pressure chemical vapor deposition furnace tube.

As shown in fig. 4c and 4d, due to the larger aspect ratio of the aperture 510, the opening of the aperture 510 is smaller, and when the second contact material is deposited, the second contact material may seal in advance at the opening of the aperture 510, resulting in a gap 520 in the contact hole after the second contact material is formed. The gap 520 is generated because the second contact material does not completely fill the aperture 510, so the gap 520 may be located in the second contact layer 620, or may be located between the first contact layer 610 and the second contact layer 620, or partially located in the second contact layer 620, or partially located between the first contact layer 610 and the second contact layer 620.

Next, referring to fig. 4e, step S400 is performed to thermally treat the semiconductor substrate, repair the first and second contact layers 620, and form repaired first and second contact layers 611 and 621.

In fig. 4c, after implanting ions into the first contact layer 610, the implanted ions may damage the original structure of the first contact material. Taking the example of ion implantation of germanium, the relative atomic mass of germanium is large and the atomic radius is also large, and germanium will destroy the crystal structure of silicon after being implanted into silicon. When the semiconductor substrate is heat-treated, the ion-implanted region of the surface of the first contact layer 610 is recrystallized, and the recrystallization process restores the structure of the ion-implanted region and the first contact layer 610 and the second contact layer 620 in the vicinity thereof, thereby eliminating the gaps 520 in the vicinity of the ion-implanted region. Since the surface of the first contact layer 610 within the aperture 510 is implanted with ions substantially everywhere, after the heat treatment, both the gap 520 near the opening of the contact hole 500 and the gap 520 near the bottom of the contact hole 500 can be repaired.

As shown in fig. 4d and 4e, after the heat treatment, the repaired first contact layer 611 and second contact layer 621 fill the slit 520 such that the slit 520 disappears.

In fig. 4d and 4e, after the semiconductor substrate is heat-treated, the area where the first contact layer 610 is not recrystallized is the repaired first contact layer 611, and the area where the first contact layer 610 and the second contact layer 620 are repaired is the repaired second contact layer 621. There may be a second contact layer 620 in the semiconductor structure where no recrystallization has occurred.

In some embodiments, the heat treatment comprises an annealing treatment or a rapid heat treatment (Rapid Thermal Processing, RTP). The temperature of the annealing treatment is in the range of 750 ° to 850 °, for example. The rapid thermal processing temperature ranges from 750 ° to 850 °.

In the method, the original process sequence of forming the second contact layer and then ion implantation is modified into the process sequence of firstly ion implantation of the first contact layer in the pore and then forming the second contact layer, so that the process sequence is set to improve the distribution depth of implanted ions in the contact hole, the depth of the implanted ions in the contact hole is larger than the depth of the gap, and the gap near the bottom of the contact hole is easy to repair. In the ion implantation process of the embodiment, ion implantation is performed on the first contact layer for a plurality of times, and in each ion implantation, the perpendicular line of the plane of the ion beam and the semiconductor substrate is at a first preset angle, so that the contact area between the ion beam and the side wall of the hole can be increased, and the implantation area and the implantation depth of the ion beam on the side wall of the hole are improved; after each ion implantation, the semiconductor substrate is rotated around the vertical line by a second preset angle, so that the implanted ions in the first contact layer along the circumferential direction of the hole in the hole can be distributed more uniformly. By the ion implantation process, uniformity of ion implantation distribution on the side wall and the bottom of the hole can be improved, so that the ion implantation area of the first contact layer is recrystallized after heat treatment, the whole gap in the contact plug is repaired, and electric performance of the contact plug is provided.

In the embodiment of the disclosure, by changing the sequence and the mode of ion implantation in the forming process of the contact plug, the gap of the contact plug layer can be eliminated without changing the ion implantation energy and the ion implantation dosage. And the electric performance of the transistor in the peripheral area is not affected because the ion implantation energy and the dosage are not changed.

In some embodiments, referring to fig. 4e, 4f and 4g, the method of manufacturing further comprises:

etching back the repaired first contact layer 611 and the second contact layer 621 until the top surfaces of the repaired first contact layer 611 and the second contact layer 621 are flush with the top surface of the dielectric layer 200;

removing the mask layer 400;

forming a bit line material layer 300 covering the dielectric layer 200, the repaired first contact layer 611 and the repaired second contact layer 621;

the bit line material layer 300 is etched to form bit lines extending in the first direction, and the repaired first contact layer 611 and second contact layer 621 are etched to form contact plugs. Wherein the remaining repaired first contact layer 611 constitutes a first contact portion of the contact plug and the remaining repaired second contact layer 621 constitutes a second contact portion of the contact plug.

Wherein the first direction is parallel to the plane of the semiconductor substrate. The first direction is, for example, the Y direction.

Illustratively, the bit line material layer 300 includes a metal nitride layer and a metal layer sequentially stacked from bottom to top. The material of the metal nitride layer may be titanium nitride, tungsten nitride, etc., and the material of the metal layer may be tungsten, copper, gold, cobalt, etc.

It should be noted that, the manufacturing method provided by the embodiment of the disclosure is not only applicable to the bit line contact plug, but also applicable to the preparation of other contact plugs with gaps, such as the capacitor contact plug, the source contact plug and the drain contact plug of the peripheral area, and the like. The manufacturing method is not only suitable for the DRAM, but also suitable for the manufacture of other semiconductor devices, such as NAND memories, SRAM memories and the like.

The embodiments of the present disclosure further provide a semiconductor device, fig. 14a is a schematic top view of the semiconductor device provided in the embodiments of the present disclosure, and fig. 14B is a schematic cross-sectional view of fig. 14a along line B-B, as shown in fig. 14a and 14B, the semiconductor device includes:

a semiconductor substrate;

the contact plug 810 extends into the semiconductor substrate, the contact plug 810 includes a first contact portion 811 and a second contact portion 812, the first contact portion 811 covers a sidewall and a bottom of the second contact portion 812, and the second contact portion 812 contains doping ions.

In some embodiments, the dopant ions include at least one of germanium, arsenic, and indium.

In some embodiments, there is no gap within contact plug 810.

In some embodiments, as shown in fig. 14a, the semiconductor base includes a substrate 100, the substrate 100 includes a plurality of active regions 110 isolated from each other and arranged in an array, a word line extending in the X direction passes through the active regions 110, and portions of the active regions 110 located at both sides of the word line are a source region 112 and a drain region 111, respectively.

The semiconductor substrate further comprises a dielectric layer 200, the dielectric layer 200 covers the surface of the substrate 100, and the contact plug 810 penetrates through the dielectric layer 200 and extends into the drain region 111; the bit line 820 is located on top of the contact plug 810 and the dielectric layer 200, and the bit line 820 is connected to the contact plug 810 and extends in the Y direction.

In the semiconductor device provided in the embodiments of the present disclosure, the second contact portion 812 contains a doping ion, and the doping ion is used to recrystallize the second contact portion 812 during the preparation process of the contact plug 810, so as to ensure no gap in the contact plug 810.

The above embodiments are merely illustrative of the principles of the present disclosure and its efficacy, and are not intended to limit the disclosure. Modifications and variations may be made to the above-described embodiments by those of ordinary skill in the art without departing from the spirit and scope of the present disclosure. Accordingly, it is intended that all equivalent modifications and variations which a person having ordinary skill in the art would accomplish without departing from the spirit and technical spirit of the present disclosure be covered by the claims of the present disclosure.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:

forming a contact hole in a semiconductor substrate;

depositing a first contact material on the side wall and the bottom of the contact hole to form a first contact layer;

performing an ion implantation process on the first contact layer; the ion implantation process comprises multiple ion implantation steps, wherein in each ion implantation step, an ion beam and a perpendicular line of a plane where the semiconductor substrate is located form a first preset angle, and the semiconductor substrate is rotated around the perpendicular line by a second preset angle after each ion implantation step;

depositing a second contact material filling the contact hole on the surface of the first contact layer to form a second contact layer;

and carrying out heat treatment on the semiconductor substrate to repair the first contact layer and the second contact layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the first preset angle is 30 ° to 60 °; the second preset angle is 20 °, 30 °, 45 °, 60 °, 90 ° or 180 °.

3. The method of manufacturing a semiconductor device according to claim 1, wherein the performing an ion implantation process on the first contact layer comprises:

carrying out ion implantation on the first contact layer for N times, wherein N is a positive integer; the second preset angle is gamma, and the product of N and gamma is 360 degrees.

4. The method for manufacturing a semiconductor device according to claim 1, wherein the number of the contact holes is plural; the performing an ion implantation process on the first contact layer further includes:

and in each ion implantation, moving the semiconductor substrate along a preset direction until the first contact layers in the contact holes are implanted with ions, wherein the preset direction is parallel to the plane of the semiconductor substrate.

5. The method of manufacturing a semiconductor device according to claim 1, wherein the implanted ions include at least one of germanium, arsenic, and indium.

6. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the first contact layer includes silicon or germanium;

the material of the second contact layer comprises doped silicon or doped germanium.

7. The method of manufacturing a semiconductor device according to claim 1, wherein in the step of forming a second contact layer by filling a second contact material in the contact hole, a slit is formed in the second contact layer;

after the heat treatment step, the gap is filled with the repaired first contact layer and the repaired second contact layer.

8. The method of manufacturing a semiconductor device according to claim 1, wherein the forming a contact hole in the semiconductor body substrate comprises:

providing a substrate; the substrate comprises a plurality of active areas which are isolated from each other and are arranged in an array, wherein the active areas comprise a source electrode area and a drain electrode area;

forming a dielectric layer and a mask layer which are sequentially stacked on the substrate;

the contact hole penetrating the mask layer and the dielectric layer and extending into the drain region or the source region is formed.

9. The method for manufacturing a semiconductor device according to claim 8, characterized in that the manufacturing method further comprises:

etching the repaired first contact layer and the repaired second contact layer back until the top surfaces of the repaired first contact layer and the repaired second contact layer are flush with the top surface of the dielectric layer;

removing the mask layer;

forming a bit line material layer covering the dielectric layer, the repaired first contact layer and the repaired second contact layer;

etching the bit line material layer to form a bit line extending along a first direction, and etching the repaired first contact layer and second contact layer to form a contact plug; wherein the first direction is parallel to the plane of the semiconductor substrate.

10. A semiconductor device, comprising:

a semiconductor substrate;

the contact plug extends into the semiconductor substrate and comprises a first contact part and a second contact part, the first contact part covers the side wall and the bottom of the second contact part, and the second contact part contains doping ions.

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