CN116208146A - Broadband high-speed multimode programmable frequency divider - Google Patents

Broadband high-speed multimode programmable frequency divider Download PDF

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Publication number
CN116208146A
CN116208146A CN202310228543.8A CN202310228543A CN116208146A CN 116208146 A CN116208146 A CN 116208146A CN 202310228543 A CN202310228543 A CN 202310228543A CN 116208146 A CN116208146 A CN 116208146A
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counter
frequency
adder
output
frequency divider
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伍锡安
田彤
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Shanghai Institute of Microsystem and Information Technology of CAS
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Shanghai Institute of Microsystem and Information Technology of CAS
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/004—Counters counting in a non-natural counting order, e.g. random counters
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00—Reducing energy consumption in communication networks
    • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

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Abstract

The invention relates to a broadband high-speed multimode programmable frequency divider, which comprises a programmable frequency divider module, a sigma-delta modulator module, an adder module and an algorithm control module; the programmable frequency divider module comprises a prescaler, a P counter and a pulse swallowing S counter; the prescaler integrates the frequency division functions of M/M+1 and 2M/2M+1; the sigma-delta modulator is used for generating random numbers of-3 to 4; the adder is used for adding the random number and an external digital input Int [ n:0 ]; the algorithm control module is used for controlling the working bit number of the pulse swallowing S counter and processing the pulse swallowing S counter based on the output L [ n-1:0] of the adder so as to meet the logic requirement of the programmable frequency divider module. The invention can widen the working frequency range of the frequency divider and simultaneously reduce the complexity, the power consumption and the area of the circuit.

Description

Broadband high-speed multimode programmable frequency divider
Technical Field
The present invention relates to programmable frequency dividers, and more particularly to a wideband high-speed multimode programmable frequency divider.
Background
Wireless communication systems, wired interface systems, etc. all require a phase locked loop based frequency synthesizer or clock generator to provide a carrier/local oscillator signal or clock signal. High performance frequency dividers are an essential key module in phase locked loop systems. In modern communication systems, in order to meet the requirements of different protocol standards and regions, phase locked loops are required to provide different output frequencies, requiring on the one hand that voltage controlled oscillators be capable of producing a wide range of frequency outputs, and on the other hand that frequency dividers be capable of operating over a wide frequency band and having different division ratio capabilities. To enhance the flexibility of the frequency divider, programmable frequency divider techniques are often required.
Currently, the technology for implementing programmable frequency dividers mainly has three forms: programmable frequency divider based on phase switch, programmable frequency divider based on pulse swallowing technique, multi-modulus frequency divider based on 2/3 frequency divider. The working frequency range of the traditional programmable frequency divider is limited, and most of the traditional programmable frequency divider works in the frequency bandwidth of hundreds of megahertz, with the development of modern electronic information technology, particularly in the application of millimeter wave radar systems, the working system of frequency modulation continuous waves is adopted, and the system bandwidth directly determines the system performances such as the ranging precision, the speed measuring precision and the like of the millimeter wave radar systems, so that the frequency divider is required to work in a very large bandwidth range to reach the frequency bandwidth of several GHz, and the working bandwidth range of the traditional 77GHz millimeter wave radar reaches about 4 GHz. When the frequency range is expanded, the existing technology designs two groups of frequency dividers with working frequencies in different ranges, and then switches through a switch to adapt to the requirements of different frequency ranges, so that the existing technology is often limited by power consumption and area, and the design and manufacturing cost is greatly increased.
Disclosure of Invention
The invention aims to solve the technical problem of providing a broadband high-speed multimode programmable frequency divider, which can widen the working frequency range and reduce the complexity, the power consumption and the area of a circuit.
The technical scheme adopted for solving the technical problems is as follows: the broadband high-speed multimode programmable frequency divider comprises a programmable frequency divider module, a sigma-delta modulator module, an adder module and an algorithm control module; the programmable frequency divider module comprises a prescaler, a P counter and a pulse swallowing S counter; the prescaler integrates the frequency division functions of M/M+1 and 2M/2M+1, so that the output frequency processed by the prescaler is the same under the condition that the input frequency is increased in multiple, the working frequency ranges of the P counter and the S counter are not increased, and the design difficulty is reduced; the sigma-delta modulator is used for generating random numbers of-3 to 4; the adder is used for adding the random number and an external digital input Int [ n:0 ]; the algorithm control module is used for controlling the working bit number of the pulse swallowing S counter and processing the pulse swallowing S counter based on the output L [ n-1:0] of the adder so as to meet the logic requirement of the programmable frequency divider module.
The P counter comprises a plurality of D trigger units which are connected in sequence, wherein the low-order D trigger unit connected with the output of the prescaler is a D trigger unit based on a TSPC structure, and the high-order D trigger unit connected with the output of the prescaler is a static D trigger unit based on a logic gate.
The number of bits of the P counter is greater than or equal to M, the number of bits of the P counter is reduced by one which is greater than the number of bits of the pulse-swallowing S counter, and the number of bits of the pulse-swallowing S counter is log 2 M, the most significant bit is log 2 M-1; the number of bits of the P counter is greater than or equal to log 2 M+1, lowest order log 2 M bits.
The algorithm control module comprises: an input signal judging unit for judging whether the frequency of the input signal exceeds a threshold value; the first processing unit is used for controlling the prescaler to adopt a frequency division function of 2M/2M+1 when the frequency of an input signal exceeds a threshold value, controlling the pulse swallowing S counter to work with a first working bit number K, sending L [ n-1:K ] in the output L [ n-1:0] of the adder to the P counter as a first control word signal, and sending L [ K-1:0] in the output L [ n-1:0] of the adder to the pulse swallowing S counter as a second control word signal; the second processing unit is used for controlling the prescaler to adopt the frequency division function of M/M+1 when the frequency of the input signal does not exceed a threshold value, controlling the pulse swallowing S counter to work with a second working bit number R, wherein the second working bit number R is smaller than the first working bit number K, and the third position of the pulse swallowing S counter is zero, L [ R-1:0] in the output L [ n-1:0] of the adder is used as a first control word signal to be sent to the pulse swallowing S counter, L [ n-2:R ] in the output L [ n-1:0] of the adder is used as a second control word signal to be sent to the P counter, and L [ n-1] in the output L [ n-1:0] of the adder is omitted.
After the prescaler is used for processing, if the frequency of the input signal has a double relation, the frequency of the output signal of the prescaler is the same, so that the working frequency ranges of the P counter and the S counter are not increased, and the design difficulty is reduced.
Advantageous effects
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects: aiming at the application requirements of broadband and multi-frequency dividing ratios, the invention provides a broadband multi-mode programmable frequency divider, which ensures the effective control of the binary code change of the multi-mode programmable broadband frequency divider integrated with a plurality of groups of pre-frequency dividers on a PS counter through algorithm control optimization, realizes the frequency divider with integer and decimal frequency division, avoids the need of using two or more groups of frequency dividers working in different frequency ranges in the traditional architecture, reduces the hardware manufacturing cost and the complexity of circuits, optimizes the power consumption, ensures that the configured programmable digit can realize a large range of frequency dividing ratios, meets most application scene requirements, and greatly enhances the application flexibility and universality of the frequency divider.
Drawings
Fig. 1 is a schematic diagram of a wideband high-speed multimode programmable divider according to this embodiment;
fig. 2 is a schematic diagram of the programmable divider module in the present embodiment;
fig. 3 is a schematic diagram of the structure of the P counter in the present embodiment;
fig. 4 is a flowchart showing the operation of the algorithm control module in the present embodiment.
Detailed Description
The invention will be further illustrated with reference to specific examples. It is to be understood that these examples are illustrative of the present invention and are not intended to limit the scope of the present invention. Further, it is understood that various changes and modifications may be made by those skilled in the art after reading the teachings of the present invention, and such equivalents are intended to fall within the scope of the claims appended hereto.
The embodiment of the invention relates to a broadband high-speed multimode programmable frequency divider, which is shown in fig. 1 and comprises a programmable frequency divider module, a sigma-delta modulator module, an adder module and an algorithm control module; the programmable frequency divider module comprises a prescaler, a P counter and a pulse swallowing S counter; the prescaler integrates the frequency division functions of M/M+1 and 2M/2M+1; the sigma-delta modulator is used for generating random numbers of-3 to 4; the adder is used for adding the random number and an external digital input Int [ n:0 ]; the algorithm control module is used for controlling the working bit number of the pulse swallowing S counter and processing the pulse swallowing S counter based on the output L [ n-1:0] of the adder so as to meet the logic requirement of the programmable frequency divider module.
In the embodiment, two groups of frequency division ratios with different modulus are integrated in one prescaler, and the counter bit number is configured by combining the algorithm control module, so that the complexity of a circuit is effectively reduced, and the area is saved. Meanwhile, the algorithm control module optimizes a programmable frequency divider chain and reduces the power consumption cost. In order to ensure that the binary control signal output after the binary code input from the outside is combined with the sigma-delta modulator can effectively reflect the constraint condition of the control code of the programmable P counter and the pulse-swallowing S counter, the algorithm control module is used for carrying out logic processing on the control word and adjusting the bit numbers of the programmable P counter and the pulse-swallowing S counter. Specifically:
the programmable frequency divider module in this embodiment can theoretically adopt any one of a programmable frequency divider based on a phase switch, a programmable frequency divider based on a pulse swallowing technology and a multi-mode frequency divider based on a 2/3 frequency divider, without any special change, so that the design difficulty of the circuit is not increased, and the programmable frequency divider module is also an advantage of the invention.
As shown in fig. 2, the programmable divider module in this embodiment is composed of a prescaler integrated with M/m+1 and 2M/2m+1 distribution functions, a programmable P counter, and a programmable pulse-swallowing S counter, where P and S represent the number of bits of the counter, respectively, and their sum represents the number of bits n of the entire high-speed wideband programmable divider, i.e., n=p+s. The frequency divider with the structure can realize the frequency division ratio of N=M×P+S, and can realize the frequency division ratio larger than M 2 The frequency divider implemented based on this structure is also referred to as MPS programmable divisionA frequency device. The programmable frequency divider module is mainly composed of D-based flip-flops, and the D-based flip-flops mainly comprise a static flip-flop based on a CML structure, a dynamic flip-flop based on a TSPC structure and a static flip-flop based on a logic gate. Wherein CML can be operated in a higher frequency range, often above 10GHz, but requires large static power consumption; TSPCs require only a single phase clock, operate in the hundreds to several gigahertz frequency range, and may fail at frequencies below hundreds MHz with relatively low power consumption. Conventional logic gate static flip-flops operate at frequencies within a few hundred megahertz with minimal static power consumption. For the purpose of optimizing and reducing power consumption, as shown in fig. 3, the P counter includes a plurality of D flip-flop units connected in sequence, wherein the low-order D flip-flop unit connected with the output of the prescaler is a D flip-flop unit based on a TSPC structure, and the high-order D flip-flop unit connected with the output of the prescaler is a static D flip-flop unit based on a logic gate. The pulse swallowing S counter uses a high-speed DFF unit based on a TSPC structure. The sigma-delta modulator in this embodiment has the main function of generating random numbers of-3 to 4 and the Int [ n:0] of external digital input]The sum is added by the adder and then is sent to the algorithm control module, and the sum is input to the programmable frequency divider module by the algorithm control module.
In this embodiment, in order to make the P counter and the pulse-swallowing S counter adapt to the wideband operating frequency and reduce the design difficulty, the pre-divider module in this embodiment integrates the frequency dividing functions of M/m+1 and 2M/2m+1 in the pre-divider, so that the frequencies processed by the P counter and the pulse-swallowing S counter in the frequency range twice as wide are consistent, and the design difficulty of the P counter and the S counter and the complexity of the circuit are greatly reduced, for example: in one embodiment, a wideband clock in the range of 500 MHz-8 GHz is processed, and then a 4/5 prescaler is used at 500MHz-4GHz, and an 8/9 prescaler is used at 4GHz-8GHz, so that the highest working frequencies of the programmable P counter and the pulse swallowing S counter are within 1GHz, and the design difficulty of the programmable P counter and the pulse swallowing counter is reduced.
The method effectively solves the problems of the prior artThe narrow-band working problem of the frequency divider and the optimization method aiming at reducing the power consumption are provided, but it is noted that in order to ensure that the binary control word input from the outside of the control word can be directly reflected on the change of the P counter and the pulse swallowing S counter, the following relations must be satisfied on M, P and S: m is the power of 2, P is greater than or equal to M, P-1>S, and the number of bits of the S counter is log 2 M, the most significant bit is log 2 M-1; the number of bits of the P counter is greater than or equal to log 2 M+1, lowest order log 2 M bits, the most significant bit is not limited. Because the prescaler integrates the frequency dividing functions of 4/5 and 8/9 at the same time, the pulse swallowing S counter needs to work at 2bit or 3bit according to the requirement and the selection of 4/5 and 8/9 made by the prescaler working at different bandwidths. In the traditional scheme, two groups of frequency dividers using different frequency ranges are designed, and then the frequency dividers are switched through a switch, namely a 4/5 prescaler and a 2-bit S counter are used as a group of frequency dividers, so that the frequency divider is suitable for 500MHz-4GHz bandwidth; in order to overcome the problem that the 8/9 prescaler and the 3-bit S counter are used as a group suitable for the bandwidth of 4GHz-8GHz, the scheme greatly increases the complexity of a circuit, the manufacturing area and the design and manufacturing cost, the embodiment provides that only one complete group of frequency dividers is used, and the algorithm control module is combined to control the bit number of the pulse-swallowing S counter and the external input Int [ n-1:0]With Frac [ q-1:0]]The logical operation output L [ n-1:0]]The processing meets the logic requirement of the MPS framework frequency divider.
The algorithm control module in this embodiment includes: an input signal judging unit for judging whether the frequency of the input signal exceeds a threshold value; the first processing unit is used for controlling the prescaler to adopt a frequency division function of 2M/2M+1 when the frequency of an input signal exceeds a threshold value, controlling the pulse swallowing S counter to work with a first working bit number K, sending L [ n-1:K ] in the output L [ n-1:0] of the adder to the P counter as a first control word signal, and sending L [ K-1:0] in the output L [ n-1:0] of the adder to the pulse swallowing S counter as a second control word signal; the second processing unit is used for controlling the prescaler to adopt the frequency division function of M/M+1 when the frequency of the input signal does not exceed a threshold value, controlling the pulse swallowing S counter to work with a second working bit number R, wherein the second working bit number R is smaller than the first working bit number K, and the third position of the pulse swallowing S counter is zero, L [ R-1:0] in the output L [ n-1:0] of the adder is used as a first control word signal to be sent to the pulse swallowing S counter, L [ n-2:R ] in the output L [ n-1:0] of the adder is used as a second control word signal to be sent to the P counter, and L [ n-1] in the output L [ n-1:0] of the adder is omitted.
The workflow of the algorithm control module is shown in fig. 4, and in the above embodiment: the programmable frequency divider module adopts the MPS programmable frequency divider shown in fig. 2, wherein the prescaler integrates 4/5 and 8/9 frequency division ratio prescaler, the number of bits of the P counter is 12 bits and is marked as P [11:0], the number of bits of the pulse-swallowing S counter is 3 bits and is marked as S [2:0], so that the total number of bits of the programmable frequency divider module is 15 bits, and the external input is correspondingly changed into 15 bits; when the input frequency range is 500MHz-4GHz, the pre-divider adopts 4/5 frequency dividing ratio under the control of the algorithm control module, the pulse swallowing S counter is set to 2bit, in order not to change other settings, as mentioned above, the third position 0 of the pulse swallowing S counter, namely N [3] =0, L [1:0] is assigned to N [1:0] and finally input to S [1:0], L [ N-2:2] is assigned to N [ N-1:3] and finally input to P counter, in this state, L [ N-1] is omitted after overflowing, at this moment, the frequency dividing ratio calculation formula is N=4xL [ N-2:2] +S1:0 ], if at this moment, the externally input Int [ N-1:0] and Frac [ q-1:0] are subjected to operation, then L [ N-2:2] =11111, S [1:0] =11, then the frequency dividing ratio is N=4×3=31+S1:0, and at this moment, if the externally input is L [ N-1:0] = 00000001111111, then the frequency dividing ratio is input to be 31.5MHz. When the input frequency range is 4GHz-8GHz, the prescaler adopts 8/9 frequency division ratio through algorithm control, S is set to 3 bits, L [ N-1:0] can be directly assigned to N [ N-1:0], and L [ N-1:3] is assigned to N [ N-1:3] to be finally input to the P counter, L [2:0] is assigned to N [2:0] to be finally input to the S counter, the frequency divider calculates the formula to be n=8×l [ N-1:3] +s2:0 ], and if the external input Int [ N-1:0] and Frac [ q-1:0] are calculated to be output to L [ N-1:0] = 00000001111111, L [ N-1:3] =1111, S [2:0] =111, then the frequency division ratio n=8×15+7=127 can be obtained if the eighth position 1 of L [ N-1:0] is required to be n=8×1:0 to be identical at the final output frequency, and if the eighth position 1×1×1:0 is required to be n=8×8+8:0, and the output is 254 MHz and the output is set to be 5.31. Through the above, it can be found that the complexity of the circuit design is greatly reduced after the optimization of the algorithm control module is added, and the difficulty of externally set binary codes is not changed. It should be noted that, for simplicity of description, the present embodiment uses an integer division ratio as an illustration, and in fact, the present embodiment satisfies both integer and fractional division functions.
It is easy to find that the invention provides a wideband multimode programmable frequency divider aiming at the application requirements of broadband and multiple frequency dividing ratios, ensures the effective control of the binary code change of the multimode programmable wideband frequency divider of the integrated multi-group prescaler to the PS counter by algorithm control optimization, realizes the frequency divider with integer and fractional frequency division simultaneously, avoids the need of using two or more groups of frequency dividers working in different frequency ranges in the traditional architecture, reduces the hardware manufacturing cost and the complexity of a circuit, optimizes the power consumption, can realize a large-scale frequency dividing ratio by the configured programmable digits, meets the requirements of most application scenes, and greatly enhances the application flexibility and the universality of the frequency divider.

Claims (5)

1. The broadband high-speed multimode programmable frequency divider is characterized by comprising a programmable frequency divider module, a sigma-delta modulator module, an adder module and an algorithm control module; the programmable frequency divider module comprises a prescaler, a P counter and a pulse swallowing S counter; the prescaler integrates the frequency division functions of M/M+1 and 2M/2M+1; the sigma-delta modulator is used for generating random numbers of-3 to 4; the adder is used for adding the random number and an external digital input Int [ n:0 ]; the algorithm control module is used for controlling the working bit number of the pulse swallowing S counter and processing the pulse swallowing S counter based on the output L [ n-1:0] of the adder so as to meet the logic requirement of the programmable frequency divider module.
2. The wideband high-speed multimode programmable divider of claim 1, wherein the P-counter comprises a plurality of D flip-flop cells connected in sequence, the low-order D flip-flop cells connected to the output of the prescaler being D flip-flop cells based on a TSPC structure, the high-order D flip-flop cells connected to the output of the prescaler being static D flip-flop cells based on logic gates.
3. The wideband high-speed multimode programmable divider of claim 1, wherein M is a power of 2 value, the number of bits of the P counter is greater than or equal to M, the number of bits of the P counter is reduced by one by greater than the number of bits of the swallow pulse S counter, and the number of bits of the swallow pulse S counter is log 2 M, the most significant bit is log 2 M-1; the number of bits of the P counter is greater than or equal to log 2 M+1, lowest order log 2 M bits.
4. The wideband high-speed multimode programmable divider of claim 1, wherein the algorithm control module comprises: an input signal judging unit for judging whether the frequency of the input signal exceeds a threshold value; the first processing unit is used for controlling the prescaler to adopt a frequency division function of 2M/2M+1 when the frequency of an input signal exceeds a threshold value, controlling the pulse swallowing S counter to work with a first working bit number K, sending L [ n-1:K ] in the output L [ n-1:0] of the adder to the P counter as a first control word signal, and sending L [ K-1:0] in the output L [ n-1:0] of the adder to the pulse swallowing S counter as a second control word signal; the second processing unit is used for controlling the prescaler to adopt the frequency division function of M/M+1 when the frequency of the input signal does not exceed a threshold value, controlling the pulse swallowing S counter to work with a second working bit number R, wherein the second working bit number R is smaller than the first working bit number K, and the third position of the pulse swallowing S counter is zero, L [ R-1:0] in the output L [ n-1:0] of the adder is used as a first control word signal to be sent to the pulse swallowing S counter, L [ n-2:R ] in the output L [ n-1:0] of the adder is used as a second control word signal to be sent to the P counter, and L [ n-1] in the output L [ n-1:0] of the adder is omitted.
5. The wideband high-speed multimode programmable divider of claim 4, wherein the output signal frequencies of the prescalers are identical if there is a double relationship between the input signal frequencies after processing by the prescalers.
CN202310228543.8A 2023-03-10 2023-03-10 Broadband high-speed multimode programmable frequency divider Pending CN116208146A (en)

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