CN116206990A

CN116206990A - Fan-out type heterogeneous chip packaging method

Info

Publication number: CN116206990A
Application number: CN202211553758.9A
Authority: CN
Inventors: 姜艳; 陶玉娟; 石磊; 夏鑫
Original assignee: Tongfu Microelectronics Co Ltd
Current assignee: Tongfu Microelectronics Co Ltd
Priority date: 2022-12-06
Filing date: 2022-12-06
Publication date: 2023-06-02

Abstract

The embodiment of the disclosure provides a fan-out heterogeneous chip packaging method, which comprises the following steps: providing a carrier plate, a plurality of silicon chips and a plurality of heterogeneous chips; forming an interconnection conductive structure on a plurality of silicon wafers respectively to form a plurality of silicon intermediaries; the interconnect conductive structures on different silicon interposer are different; cutting each silicon intermediate plate to obtain a plurality of sub-silicon intermediate plates; selecting a plurality of target sub-silicon intermediaries from the plurality of sub-silicon intermediaries, fixing the first surface of at least one target sub-silicon intermediaries on the carrier plate, and fixing the rest of second surfaces on the carrier plate; the height of at least one target sub-silicon interposer is different from the other heights; forming a first plastic sealing layer on one side of the plurality of target sub-silicon intermediate boards, which is away from the carrier board; the heterogeneous chip is bonded to the target daughter silicon interposer. The method can avoid warpage or breakage generated when a plurality of heterogeneous chips are bonded to a plurality of target sub-silicon intermediate boards; the target sub-silicon interposer can be formed with the heterogeneous chip at one time, so that the packaging integration level of the heterogeneous chip is improved.

Description

Fan-out type heterogeneous chip packaging method

Technical Field

The embodiment of the disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a fan-out type heterogeneous chip packaging method.

Background

The silicon interposer in the existing 2.5D fan-out package is mainly connected between the chip and the substrate, and amplifies the signal of the chip and connects to the substrate. The integration level of the current silicon medium layer is low, and the integration level needs to be improved. However, the thinner the package is, the more chips may be connected to the silicon interposer. Warpage or breakage of the silicon interposer is easily generated when the silicon interposer is thinned after the chip is mounted on the silicon interposer.

In view of the above, it is necessary to provide a fan-out heterogeneous chip packaging method which is reasonable in design and effectively solves the above problems.

Disclosure of Invention

The embodiment of the disclosure aims to at least solve one of the technical problems in the prior art and provides a fan-out type heterogeneous chip packaging method.

The embodiment of the disclosure provides a fan-out type heterogeneous chip packaging method and a packaging method

Comprising the following steps:

providing a carrier plate, a plurality of silicon chips and a plurality of heterogeneous chips respectively;

forming interconnection conductive structures on the plurality of silicon wafers respectively to form a plurality of silicon intermediaries; wherein the interconnect conductive structures on at least one of the silicon interposer are different from the interconnect conductive structures on other of the silicon interposer;

Cutting each silicon intermediate plate to obtain a plurality of sub silicon intermediate plates;

selecting a plurality of target sub-silicon intermediaries from the plurality of sub-silicon intermediaries, fixing the first surface of at least one of the target sub-silicon intermediaries to a carrier, and fixing the second surfaces of the rest of the target silicon intermediaries to the carrier; wherein the height of at least one of the target sub-silicon interposer is different from the height of the other target sub-silicon interposer;

forming a first plastic sealing layer on one side of the target sub-silicon intermediate boards, which is away from the carrier board;

the plurality of heterogeneous chips are bonded to the plurality of target daughter silicon interposer.

Optionally, selecting a plurality of target silicon intermediaries from the plurality of silicon intermediaries, and fixing a first surface of at least one of the target silicon intermediaries to a carrier, and fixing a second surface of the other target silicon intermediaries to the carrier includes:

the interconnect conductive structure of at least one of the target sub-silicon interposer is different from the interconnect conductive structures of other of the target sub-silicon interposer.

Optionally, the forming an interconnection conductive structure on each of the plurality of silicon wafers includes:

Forming a plurality of blind holes on the front surface of at least one silicon wafer; wherein the plurality of blind holes formed on the front surface of at least one of the silicon wafers are different from the plurality of blind holes formed on the front surfaces of the rest of the silicon wafers;

and filling conductive materials in the blind holes to form the interconnection conductive structure.

Optionally, the forming interconnection conductive structures on the plurality of silicon wafers respectively further includes:

filling conductive materials in the blind holes;

and thinning the back surface of the silicon wafer until the blind holes are exposed to form a plurality of through silicon holes so as to form the interconnection conductive structure.

filling conductive materials in the blind holes;

Forming a rewiring layer on the blind holes;

thinning the back surface of the silicon wafer until the blind holes are exposed, so as to form the interconnection conductive structure; or,

the forming of the interconnection conductive structures on the plurality of silicon wafers respectively further comprises:

filling conductive materials in the blind holes;

forming a rewiring layer on the blind holes;

forming a plurality of solder balls on the rewiring layer;

and thinning the back surface of the silicon wafer until the blind holes are exposed, so as to form the interconnection conductive structure.

Optionally, after the first molding layer is formed on a side of the plurality of target sub-silicon intermediaries facing away from the carrier, or after the bonding of the plurality of heterogeneous chips to the plurality of target sub-silicon intermediaries, the method further includes:

and forming a plurality of first through holes in the thickness direction of the first plastic sealing layer, and filling conductive materials in the plurality of first through holes to form a plurality of first conductive convex columns.

Optionally, when the interconnection conductive structure of at least one of the target sub-silicon interposer is a plurality of blind holes or a plurality of through silicon vias filled with conductive material, the first surface of the target sub-silicon interposer is fixed on the carrier, and the height of the target sub-silicon interposer is higher than that of other target sub-silicon interposer;

the bonding the plurality of heterogeneous chips to the plurality of target daughter silicon interposer includes:

removing the carrier plate, and bonding one side of the heterogeneous chips facing the target sub-silicon intermediaries with one side of the target sub-silicon intermediaries facing the carrier plate through a bonding structure;

after the bonding of the plurality of heterogeneous chips to the plurality of target daughter silicon interposer, further comprising:

thinning one side of the first plastic sealing layer, which faces away from the heterogeneous chips, so as to expose the interconnection conductive structure on one side of the target sub-silicon interposer, which faces away from the carrier; wherein,,

the thinned sides of the target sub-silicon intermediaries, which deviate from the carrier plate, are flush;

and forming a first interconnection circuit layer on one side of the thinned target sub-silicon intermediate boards, which is away from the carrier board.

Optionally, the bonding the plurality of heterogeneous chips to the plurality of target daughter silicon interposer further includes:

forming a second plastic sealing layer on one side of the heterogeneous chips away from the target sub-silicon interposer;

thinning one side of the first plastic sealing layer, which faces away from the carrier plate, so as to expose the interconnection conductive structures on one side of the plurality of target sub-silicon intermediate plates, which faces away from the carrier plate; wherein,,

bonding the heterogeneous chips and the second plastic sealing layers towards one sides of the target sub-silicon intermediate boards and one sides of the thinned target sub-silicon intermediate boards away from the carrier board through bonding structures;

and removing the carrier plate, and forming a first interconnection circuit layer on one side of the target sub-silicon intermediate plates facing the carrier plate.

Optionally, the height of at least one of the target sub-silicon intermediaries is lower than the height of the other target sub-silicon intermediaries;

thinning one side of the first plastic sealing layer, which faces away from the carrier plate, so as to expose the interconnection conductive structures on one side of the plurality of high target sub-silicon intermediate plates, which faces away from the carrier plate;

bonding one side of the heterogeneous chips and the second plastic sealing layers, which face the target sub-silicon intermediaries, with one side of the thinned target sub-silicon intermediaries, which faces away from the carrier plate, through a first bonding structure;

bonding one side of the heterogeneous chips and the second plastic sealing layers, which face the target sub-silicon intermediaries, with one side of the thinned target sub-silicon intermediaries, which faces away from the carrier plate, through a second bonding structure; wherein the height of the first bonding structure is greater than the height of the second bonding structure;

Optionally, after the first interconnection line layer is formed on a side of the plurality of target sub-silicon intermediaries toward the carrier, the method further includes:

forming a plurality of second through holes penetrating through the first plastic sealing layer and the second plastic sealing layer in the thickness direction;

filling conductive materials in the second through holes to form second conductive convex columns;

forming a second interconnection circuit layer on one side of the second plastic sealing layer away from the target sub-silicon intermediaries; wherein,,

and two ends of the second conductive convex columns are respectively and electrically connected with the first interconnection line layer and the second interconnection line layer.

According to the fan-out type heterogeneous chip packaging method, the interconnection conductive structures are formed on the silicon wafers respectively to form the silicon intermediaries, wherein the interconnection conductive structures on at least one silicon intermediaries are different from those on other silicon intermediaries, each silicon intermediaries is cut to form the silicon intermediaries, the silicon intermediaries are recombined, the target silicon intermediaries are selected from the silicon intermediaries, and the heterogeneous chips are bonded to the first surface of the silicon intermediaries and the second surface of the other silicon intermediaries, so that warping or breakage of the silicon intermediaries during packaging can be avoided; the silicon intermediate plate is cut into a plurality of sub-silicon intermediate plates, and the sub-silicon intermediate plates are recombined to be used as target sub-silicon intermediate plates, so that the silicon intermediate plates can be formed with a plurality of heterogeneous chips at one time, and the integration level of heterogeneous chip packaging is improved.

Drawings

Fig. 1 is a flow chart of a fan-out heterogeneous chip packaging method according to an embodiment of the disclosure;

FIG. 2 is a schematic illustration of forming blind vias in a silicon wafer according to another embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a first silicon interposer and a first interconnect conductive structure according to another embodiment of the present disclosure;

FIGS. 4-5 are schematic diagrams illustrating a packaging process of a second silicon interposer and a second interconnect conductive structure according to another embodiment of the present disclosure;

FIGS. 6-8 are schematic diagrams illustrating a packaging process of a third silicon interposer and a third interconnect conductive structure according to another embodiment of the present disclosure;

fig. 9-11 are schematic views illustrating a packaging process of a fourth silicon interposer and a fourth interconnect conductive structure according to another embodiment of the present disclosure;

FIG. 12 is a schematic diagram of a first sub-silicon interposer according to another embodiment of the present disclosure;

FIG. 13 is a schematic diagram of a second sub-silicon interposer according to another embodiment of the present disclosure;

FIG. 14 is a schematic diagram of a third sub-silicon interposer according to another embodiment of the present disclosure;

FIG. 15 is a schematic diagram of a fourth sub-silicon interposer according to another embodiment of the present disclosure;

Fig. 16 to 19 are schematic views of a packaging process of a fan-out heterogeneous chip packaging method according to another embodiment of the disclosure;

fig. 20 to 23 are schematic views of a packaging process of a fan-out heterogeneous chip packaging method according to another embodiment of the disclosure;

fig. 24 to 30 are schematic views of a packaging process of a fan-out heterogeneous chip packaging method according to another embodiment of the disclosure;

fig. 31 to 34 are schematic views of a packaging process of a fan-out heterogeneous chip packaging method according to another embodiment of the disclosure.

Detailed Description

In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are described in further detail below with reference to the accompanying drawings and detailed description.

As shown in fig. 1, an embodiment of the present disclosure provides a fan-out heterogeneous chip packaging method S100, where the packaging method S100 includes:

s110, respectively providing a carrier plate, a plurality of silicon chips and a plurality of heterogeneous chips.

Specifically, as shown in fig. 2 to 34, a carrier plate 110, a plurality of silicon wafers 120, and a plurality of hetero chips 130 are provided, respectively. The material of the carrier plate 110 may be glass, silicon wafer or metal, which is not limited in this embodiment. The number of the silicon chips 120 and the heterogeneous chips 130 is not particularly limited, and may be selected according to actual needs.

S120, respectively forming interconnection conductive structures on the plurality of silicon chips to form a plurality of silicon intermediate boards; wherein the interconnect conductive structures on at least one of the silicon interposer are different from the interconnect conductive structures on other of the silicon interposer.

Specifically, as shown in fig. 2 to 11, interconnect conductive structures (not shown) are formed on the plurality of silicon wafers 120, respectively, to form a plurality of silicon interposer. Wherein the interconnect conductive structures on at least one silicon interposer are different from the interconnect conductive structures on other silicon interposers. That is, different interconnect conductive structures are formed on different silicon wafers 120.

In the above embodiment, the interconnection conductive structures are formed on the plurality of silicon wafers respectively to form the plurality of silicon intermediaries, so that the manufacturing process is simple, the process difficulty is low, and the implementation is easy. The interconnection conductive structure on at least one silicon interposer is different from the interconnection conductive structures on other silicon interposers, so that high-integration packaging can be realized, and the packaging requirement of packaging the silicon interposers and a plurality of heterogeneous chips can be met.

In one embodiment, referring to fig. 2 to 3, step S120 is specifically described above

Comprising the following steps:

s101, forming a plurality of blind holes on the front surface of at least one silicon wafer; wherein the plurality of blind holes formed on the front surface of at least one silicon wafer is different from the plurality of blind holes formed on the front surface of the remaining silicon wafer.

Specifically, as shown in fig. 2, a plurality of blind holes 121 are formed in the front side of at least one silicon wafer 120 through photolithography and etching processes. An insulating layer, a diffusion barrier layer and a seed layer are then deposited on the sidewalls of the blind via 121, wherein none of the insulating layer, the diffusion barrier layer and the seed layer are shown. Wherein the plurality of blind holes 121 formed on the front surface of at least one silicon wafer 120 are different from the plurality of blind holes 121 formed on the front surface of the remaining silicon wafer 120.

That is, a plurality of blind holes 121 having different heights, depths, widths, pitches, etc. are formed on different silicon wafers 120, respectively. For example, the high aspect ratio of the plurality of blind holes 121 on each silicon wafer 120 is different, the spacing between the plurality of blind holes 121 is different, and so on. For example, as shown in fig. 1, a plurality of blind holes 121 are formed on a first silicon wafer 120a at equal intervals and with smaller pitches, a plurality of blind holes 121 are formed on a second silicon wafer 120b at equal intervals and with larger pitches, a plurality of blind holes 121 are formed on a third silicon wafer 120c at equal intervals, with larger pitches, with larger depths and with larger widths, and a plurality of blind holes 121 are formed on a fourth silicon wafer 120d at unequal intervals, with smaller pitches and with smaller depths and widths. Of course, the plurality of blind holes 121 on each silicon wafer 120 may be of other specifications, which are not specifically limited.

In the above embodiment, the plurality of blind holes formed on the front surface of at least one silicon wafer is different from the plurality of blind holes formed on the front surface of the other silicon wafer, so that the interconnection conductive structures with different integration levels can be formed, and the overall integration level of the package can be improved.

S102, filling conductive materials in the blind holes to form an interconnection conductive structure.

Specifically, as shown in fig. 3, conductive material is filled in the formed plurality of blind holes 121 by a process such as electroplating, and then the surface of the blind holes 121 is planarized by a chemical mechanical polishing process to form an interconnection conductive structure, that is, a first interconnection conductive structure 151.

In this embodiment, as shown in fig. 3, a first interconnect conductive structure 151 is formed on the silicon wafer 120 to form a first silicon interposer 141. That is, the first silicon interposer 141 is provided with a plurality of blind holes 121 filled with a conductive material.

Referring to fig. 2 to 5, in another embodiment, the step S120 further specifically includes:

step S201, step S201 is the same as step S101 described above, as shown in fig. 2, namely: a plurality of blind holes 121 are formed in the front surface of at least one silicon wafer 120. Wherein the plurality of blind holes 121 formed on the front surface of at least one silicon wafer 120 are different from the plurality of blind holes 121 formed on the front surface of the remaining silicon wafer 120.

Step S202, step S202 is the same as step S102 described above, as shown in fig. 3, namely: the plurality of blind holes 121 formed are filled with a conductive material by a plating process or the like. It should be noted that, the steps S201 and S202 are described in detail above, and are not described herein.

S203, thinning the back surface of the silicon wafer until the blind holes are exposed to form a plurality of through silicon vias, so as to form the interconnection conductive structure.

Specifically, after the conductive material is filled in the formed plurality of blind holes 121 by using a process such as electroplating, as shown in fig. 4, the front surface of the silicon wafer 120 is fixed on the temporary carrier 160, and then the back surface of the silicon wafer 120 is ground and thinned by using a process such as grinding to expose the plurality of blind holes 121, as shown in fig. 5, the temporary carrier 160 is removed, so as to form the interconnection conductive structure. That is, in the present embodiment, after the conductive material is filled in the plurality of blind holes 121, the front surface of the silicon wafer 120 is fixed on the temporary carrier 160, the back surface of the silicon wafer 120 is ground by adopting a grinding process to remove the excessive silicon material, and then the temporary carrier 160 is removed, so as to form the second interconnection conductive structure 152, that is, the second interconnection conductive structure 152 is a through silicon via filled with the conductive material.

Note that in this embodiment, as shown in fig. 5, a second interconnect conductive structure 152 is formed on the silicon wafer 120 to form a second silicon interposer 142. That is, the second silicon interposer 142 includes a plurality of through silicon vias. The through silicon vias may lead out the functionality of the second silicon interposer 142.

Referring to fig. 2 to 8, in another embodiment, the step S120 further specifically includes:

step S301, step S301 is the same as step S101 described above, and as shown in fig. 2, namely: a plurality of blind holes 121 are formed in the front surface of at least one silicon wafer 120. Wherein the plurality of blind holes 121 formed on the front surface of at least one silicon wafer 120 are different from the plurality of blind holes 121 formed on the front surface of the remaining silicon wafer 120.

Step S302, step S302 is the same as step S102 described above, as shown in fig. 3, namely: a plating process is used to fill the conductive material in the plurality of blind holes 121 formed. It should be noted that, the steps S210 and S220 are described in detail above, and will not be repeated here.

S303, forming a rewiring layer on the blind holes.

Specifically, as shown in fig. 6, a rewiring layer 122 is formed on the plurality of blind holes 121 filled with the conductive material. That is, a re-wiring layer 122 is formed on the front surface of the silicon wafer 120, and the re-wiring layer 122 is electrically connected to the plurality of blind holes 121 filled with the conductive material.

Further, in the present embodiment, the rewiring layer 122 may include a dielectric layer (not shown) and a metal layer (not shown) disposed on the dielectric layer. Specifically, a dielectric layer is coated on the surface of the silicon wafer 120 provided with the plurality of blind holes 121, the dielectric layer is patterned by using a photolithography process, a plurality of openings are formed on the dielectric layer, and then a metal layer is formed on the patterned dielectric layer by using processes such as sputtering and electroplating.

Note that, the material of the dielectric layer may be Polyimide (PI), polybenzoxazole (PBO), etc., and the coating method is usually heterogeneous chip spin coating, which is not limited in this embodiment. The material of the metal layer is typically titanium and copper, but other metal materials may be used, and the embodiment is not particularly limited.

In another embodiment, the process of forming the rewiring layer 122 may also be as follows: a photoresist layer is formed on the surface of the silicon wafer 120 where the plurality of blind holes 121 are formed, a plurality of openings are formed in the patterned photoresist layer, and a thick metal layer is formed at the plurality of openings through a sputtering process to form a re-wiring layer 122.

S304, thinning the back surface of the silicon wafer until a plurality of blind holes are exposed, and forming an interconnection conductive structure.

Specifically, as shown in fig. 7, the rewiring layer 122 is fixed on the temporary carrier 160, and then the back surface of the silicon wafer 120 is polished by a polishing process or the like to expose the plurality of blind holes 121, and as shown in fig. 8, the temporary carrier 160 is removed to form the third interconnection conductive structure 153, that is, the third interconnection conductive structure 153 includes a through silicon via and the rewiring layer 122 disposed on the through silicon via.

It should be further noted that, in the present embodiment, as shown in fig. 8, a third interconnection conductive structure 153 is formed on the silicon wafer 120 to form a third silicon interposer 143. That is, the third silicon interposer 143 includes a plurality of through silicon vias and the rewiring layer 122 disposed on the through silicon vias. The rewiring layer 122 may integrate the signals extracted from the through silicon vias and then uniformly extract the signals from the third silicon interposer 143.

Referring to fig. 2 to 10, in another embodiment, the step S120 further specifically includes:

s401, step S401 is the same as step S101 described above, and as shown in fig. 2, namely: a plurality of blind holes 121 are formed in the front surface of at least one silicon wafer 120. Wherein the plurality of blind holes 121 formed on the front surface of at least one silicon wafer 120 are different from the plurality of blind holes 121 formed on the front surface of the remaining silicon wafer 120.

Step S402, step S402 is the same as step S102 described above, as shown in fig. 3, namely: a plating process is used to fill the conductive material in the plurality of blind holes 121 formed. It should be noted that, the steps S210 and S220 are described in detail above, and will not be repeated here.

Step S403, step S403 is the same as step S303 described above, as shown in fig. 6, namely: a rewiring layer 122 is formed on the plurality of blind holes 121 filled with the conductive material.

S404, forming a plurality of solder balls on the rewiring layer.

Specifically, as shown in fig. 9, ball placement is performed on the rewiring layer 122 to form a plurality of solder balls 123.

S405, thinning the back surface of the silicon wafer until a plurality of blind holes are exposed, and forming an interconnection conductive structure.

Specifically, as shown in fig. 10, a plurality of solder balls 123 are fixed on the temporary carrier 160, and then the back surface of the silicon wafer 120 is polished by a polishing process or the like to expose the plurality of blind holes 121, and as shown in fig. 11, the temporary carrier 160 is removed to form a fourth interconnection conductive structure 154, that is, the fourth interconnection conductive structure 154 includes a through silicon via, a rewiring layer 122 disposed on the through silicon via, and a plurality of solder balls 123 disposed on the rewiring layer 122.

In this embodiment, as shown in fig. 11, a fourth interconnect conductive structure 154 is formed on the silicon wafer 120 to form a fourth silicon interposer 144. That is, the fourth silicon interposer 144 includes a plurality of through-silicon vias, a rewiring layer 122 disposed on the through-silicon vias, and a plurality of solder balls 123 disposed on the rewiring layer 122. The signal led out from the through silicon vias can be integrated by the rewiring layer 122 and the solder balls 123 disposed on the rewiring layer 122, and then the signal led out from the fourth silicon interposer 144 can be uniformly led out.

It should be further noted that, in this embodiment, the type of the silicon interposer may be other types besides the types described above, and the corresponding silicon interposer may be manufactured according to the need, which is not particularly limited.

S130, cutting each silicon intermediate plate to obtain a plurality of sub-silicon intermediate plates.

Specifically, as shown in fig. 12 to 15, each silicon interposer is cut and separated to obtain a plurality of sub-silicon interposers. As shown in fig. 11, in the present embodiment, the first silicon interposer 141 is cut and separated to obtain a plurality of first sub-silicon interposers 171. As shown in fig. 12, the structures of the sub-silicon intermediaries formed by cutting different silicon intermediaries may be different, for example, the densities, widths, depths, etc. of the interconnection conductive structures on the first sub-silicon intermediaries 171 formed by cutting and separating the first silicon intermediaries 141 with different structures may also be different, so that different packaging requirements may be satisfied, and a suitable first sub-silicon intermediaries 171 may be selected for packaging according to needs, thereby improving the packaging integration.

As shown in fig. 13, the second silicon interposer 142 is cut and separated to obtain a plurality of second sub-silicon interposers 172. As shown in fig. 13, the structures of the sub-silicon intermediaries formed by cutting different silicon intermediaries may be different, for example, the densities, widths, depths, etc. of the interconnection conductive structures on the second sub-silicon intermediaries 172 formed by cutting and separating the second silicon intermediaries 142 with different structures may also be different, so that different packaging requirements may be satisfied, and a suitable second sub-silicon intermediaries 172 may be selected for packaging according to needs, thereby improving the packaging integration.

As shown in fig. 14, the third silicon interposer 143 is diced and separated to obtain a plurality of third sub-silicon interposers 173. As shown in fig. 14, the structures of the sub-silicon intermediaries formed by cutting the different silicon intermediaries may be different, for example, the densities, widths, depths, etc. of the interconnection conductive structures on the third sub-silicon intermediaries 173 formed by cutting and separating the third silicon intermediaries 143 with different structures may also be different, so that different packaging requirements may be satisfied, and a suitable third sub-silicon intermediaries 173 may be selected for packaging according to needs, thereby improving the packaging integration.

As shown in fig. 15, the fourth silicon interposer 144 is diced and separated to obtain a plurality of fourth sub-silicon interposers 174. As shown in fig. 15, the structures of the sub-silicon intermediaries formed by cutting different silicon intermediaries may be different, for example, the densities, widths, depths, etc. of the interconnection conductive structures on the fourth sub-silicon intermediaries 174 formed by cutting and separating the fourth silicon intermediaries 144 with different structures may also be different, so that different packaging requirements may be satisfied, and a suitable fourth sub-silicon intermediaries 174 may be selected for packaging according to needs, so as to improve the packaging integration level.

The above four types of sub-silicon interposer are different, that is, the structure and specification of the interconnect conductive structure of each type of sub-silicon interposer are different. It should be noted that, in addition to the four types of sub-silicon intermediaries mentioned in the present embodiment, other types of sub-silicon intermediaries may be formed, and the present embodiment is not limited specifically.

It should be noted that the same type of silicon interposer may also have interconnect conductive structures with different levels of integration, for example, the first sub-silicon interposer 171 may also be the same, and the levels of integration of the interconnect conductive structures between each of the first sub-silicon interposers 171 may also be different, for example, the densities, widths, depths, etc. of the interconnect conductive structures may be different.

S140, selecting a plurality of target sub-silicon intermediaries from the plurality of sub-silicon intermediaries, fixing the first surface of at least one of the target sub-silicon intermediaries to a carrier, and fixing the second surfaces of the rest of the target sub-silicon intermediaries to the carrier; wherein the height of at least one of the target sub-silicon interposer is different from the height of the other target sub-silicon interposer.

Specifically, in this embodiment, the first surface of the target silicon interposer is the front surface of the target sub-silicon interposer, and the second surface of the target silicon interposer is the back surface of the target sub-silicon interposer. According to preset packaging requirements, selecting a plurality of target sub-silicon intermediaries from the plurality of sub-silicon intermediaries, fixing the front surface of at least one target sub-silicon intermediaries on the carrier 110, and fixing the back surfaces of the rest target silicon intermediaries on the carrier 110. That is, according to different packaging requirements, a plurality of target sub-silicon intermediaries are selected from the plurality of sub-silicon intermediaries, the plurality of target sub-silicon intermediaries are combined according to the packaging requirements, then the front surface of one part of the target sub-silicon intermediaries is fixed on the carrier 110, and the back surface of the other part of the target sub-silicon intermediaries is fixed on the carrier 110.

In this embodiment, the height of at least one target sub-silicon interposer is different from the height of the other target sub-silicon interposers. The target sub-silicon interposer can be ground according to packaging requirements to make the heights consistent, and then corresponding packaging steps are carried out. The high uniformity of the multiple target sub-silicon interposer can also be met by providing different bonding structures.

Illustratively, selecting a plurality of target sub-silicon intermediaries from the plurality of sub-silicon intermediaries, and fixing a front side of at least one of the target sub-silicon intermediaries to a carrier, and fixing a back side of the remaining target silicon intermediaries to the carrier, including:

the interconnect conductive structure of at least one target sub-silicon interposer is different from the interconnect conductive structures of other target silicon interposers.

In the above embodiment, the interconnection conductive structure of at least one target sub-silicon interposer is different from the interconnection conductive structures of other target sub-silicon intermediaries, and different target sub-silicon intermediaries are selected for packaging according to the packaging requirements of different heterogeneous chips, so that the packaging integration level of the target sub-silicon intermediaries and the packaging of a plurality of heterogeneous chips can be improved, and the packaging requirements of different heterogeneous chips can be satisfied.

It should be noted that the plurality of target sub-silicon intermediaries may be the same type of sub-silicon intermediaries, or may be different types of sub-silicon intermediaries. That is, in the present embodiment, the plurality of target sub-silicon intermediaries may be one selected from the first sub-silicon intermediaries 171, the second sub-silicon intermediaries 172, the third sub-silicon intermediaries 173 and the fourth sub-silicon intermediaries 174, or at least two of them may be selected to be combined and then the front surface thereof may be fixed on the carrier 110. The selection of the target sub-silicon interposer is not particularly limited, and may be selected according to actual needs.

It should be further noted that if the plurality of target silicon interposer may be the same type of silicon interposer, then the interconnect conductive structure of at least one of the target silicon interposers is different from the interconnect conductive structures of the other target silicon interposers. For example, the plurality of target sub-silicon interposer may be first sub-silicon interposer 171, but the first interconnect conductive structures 151 in each first sub-silicon interposer 171 are also different, e.g., the pitch, depth, and width of the first interconnect conductive structures 151 are also different.

In the above embodiment, according to the preset packaging requirement, a plurality of target sub-silicon intermediaries are selected from the plurality of sub-silicon intermediaries, the front surface of at least one target sub-silicon intermediaries is fixed on the carrier, and the back surfaces of the other target silicon intermediaries are fixed on the carrier, so that warpage or cracking of the target sub-silicon intermediaries can be avoided when a plurality of heterogeneous chips are bonded to the plurality of target sub-silicon intermediaries. The interconnection conductive structure of at least one target silicon intermediate block is different from the interconnection conductive structures of other target silicon intermediate blocks, so that the packaging requirements of different heterogeneous chips can be met, and the recombined target sub-silicon intermediate plate can be formed with a plurality of heterogeneous chips at one time, so that the integration level of the heterogeneous chip packaging is improved.

S150, forming a first plastic sealing layer on one side of the target sub-silicon intermediate boards, which is away from the carrier board.

Specifically, as shown in fig. 17, 21 and 25, after the plurality of target silicon interposer are fixed on the carrier 110, a first molding layer 180 is formed on a side of the plurality of target silicon interposer facing away from the carrier 110. That is, the first molding layer 180 wraps the plurality of target sub-silicon intermediaries, and protects the plurality of target sub-silicon intermediaries. The plastic packaging method may be film vacuum lamination or a conventional plastic packaging process, and the embodiment is not particularly limited.

As illustrated in fig. 17, 21 and 25, after forming the first molding layer on a side of the plurality of target sub-silicon interposer facing away from the carrier, the method further includes:

a plurality of first through holes are formed in the first molding layer 180 along the thickness direction thereof, and a conductive material is filled in the plurality of first through holes to form a plurality of first conductive studs 181.

It should be noted that, after the plurality of heterogeneous chips 130 are bonded to the plurality of target sub-silicon interposer, the plurality of first conductive bumps 181 may be formed. Specifically, after bonding the heterogeneous chips 130 to the target daughter silicon interposer, a plurality of first through holes are formed in the first molding layer 180 along the thickness direction thereof, and a conductive material is filled in the plurality of first through holes to form a plurality of first conductive bumps 181.

In the above embodiments, any process of forming the plurality of first conductive studs 181 may be used, and in general, after forming the first molding layer on the back surface of the plurality of target sub-silicon interposer, the plurality of first conductive studs 181 are formed.

S160, bonding the heterogeneous chips onto the target sub-silicon interposer.

For example, when the interconnection conductive structure of at least one of the target sub-silicon interposer is a plurality of blind holes or a plurality of through silicon vias filled with conductive material, the front surface of the target sub-silicon interposer is fixed on the carrier, and the height of the target sub-silicon interposer is higher than that of other target sub-silicon interposer;

the carrier 110 is removed, and a plurality of heterogeneous chips 130 are bonded to a side of the plurality of target sub-silicon intermediaries facing the carrier 110 through a bonding structure.

thinning the side of the first plastic layer 180 facing away from the heterogeneous chips 130 to expose the interconnection conductive structures of the side of the target daughter silicon interposer facing away from the carrier 110; wherein, the thinned sides of the plurality of target sub-silicon interposer facing away from the carrier 110 are flush.

A first interconnect line layer 192 is formed on a side of the thinned plurality of target sub-silicon interposer facing away from the carrier plate 110.

Specifically, as shown in fig. 16 to 19, in an embodiment, a plurality of first sub-silicon intermediaries 171 and a plurality of third sub-silicon intermediaries 173 are selected as target sub-silicon intermediaries, wherein the height of the plurality of third sub-silicon intermediaries 173 is lower than the height of the plurality of first sub-silicon intermediaries 171.

As shown in fig. 16, the front surface of the first sub-silicon interposer 171 is fixed to the carrier 110, and the back surface of the third sub-silicon interposer 173 is fixed to the carrier 110. An adhesive layer may be used to secure the front side of the first sub-silicon interposer 171 and the third sub-silicon interposer 173 to the carrier board 110.

As shown in fig. 17, a first molding layer 180 is formed on the back surface of the first sub-silicon interposer 171 and the front surface of the third sub-silicon interposer 173. And a plurality of first through holes are formed in the first molding layer 180 along the thickness direction thereof, and a conductive material is filled in the plurality of first through holes to form a plurality of first conductive studs 181.

As shown in fig. 18, a plurality of first metal pads 131 are formed on the back surface of the plurality of hetero chips 130 facing the first sub-silicon interposer 171 and the front surface of the third sub-silicon interposer 173, wherein in the present embodiment, the material of the plurality of first metal pads 131 may be metal copper, but may be other metal materials.

As shown in fig. 18, the carrier 110 is removed, and the plurality of hetero chips 130 are flip-chip mounted on the front surface of the first sub-silicon interposer 171 and the back surface of the third sub-silicon interposer 173 through the plurality of first metal pads 131.

As shown in fig. 19, the side of the first plastic layer 180 facing away from the carrier 110 is thinned to expose the interconnection conductive structures on the back surface of the first sub-silicon interposer 171 and the front surface of the third sub-silicon interposer 173 and the first conductive bumps 181, that is, to expose the plurality of through-silicon vias on the back surface of the first sub-silicon interposer 171 and the rewiring layer on the front surface of the third sub-silicon interposer 173 and the first conductive bumps 181. The back surface of the thinned first sub-silicon interposer 171 is flush with the front surface of the third sub-silicon interposer 173, that is, the back surface of the first sub-silicon interposer 171 is polished to be flush with the front surface of the third sub-silicon interposer 173.

As shown in fig. 19, a first interconnection line layer 192 is formed on the back surface of the thinned first sub-silicon interposer 171 and the front surface of the third sub-silicon interposer 173, and the package of the hetero chip is completed, and the hetero chip package is electrically connected to the outside through the first interconnection line layer 192. The first interconnect line layer 192 may include a rewiring layer and solder balls, and may include other interconnect line layers, which are not particularly limited in this embodiment. Through the first interconnection line layer 192, the signal amplification function of the target sub-silicon interposer can be achieved, the flexibility of package integration is improved, and the interconnection density of the package structure is increased.

In the above embodiments, the package height is reduced by bonding a plurality of heterogeneous chips to a plurality of target sub-silicon interposer through a flip-chip process. Of course, a hybrid bonding process or a thermocompression bonding process may be used to bond a plurality of heterogeneous chips to a plurality of target sub-silicon interposer, and the embodiment is not limited in detail.

the bonding the plurality of heterogeneous chips to the plurality of target daughter silicon interposer further comprises:

a second molding layer 191 is formed on a side of the plurality of hetero-chips 130 facing away from the plurality of target sub-silicon interposer.

Thinning the side of the first plastic layer 180 facing away from the carrier plate 110 to expose the interconnection conductive structures of the sides of the plurality of target sub-silicon intermediaries facing away from the carrier plate 110; wherein, the thinned sides of the plurality of target sub-silicon interposer facing away from the carrier 110 are flush.

Through the bonding structure, a side of the heterogeneous chips 130 and the second plastic layer 191 facing the target sub-silicon interposer and a side of the thinned target sub-silicon interposer facing away from the carrier 110 are bonded.

the carrier 110 is removed and a first interconnect line layer is formed on a side of the plurality of target sub-silicon interposer facing the carrier 110.

Specifically, as shown in fig. 20 to 23, in another embodiment, a plurality of second sub-silicon intermediaries 171 and a plurality of fourth sub-silicon intermediaries 174 are selected and recombined to be the target sub-silicon intermediaries, wherein the height of the fourth sub-silicon intermediaries 174 is lower than the height of the second sub-silicon intermediaries 172.

As shown in fig. 20, the front side of the second sub-silicon interposer 172 is fixed to the carrier 110, and the back side of the fourth sub-silicon interposer 174 is fixed to the carrier 110.

As shown in fig. 20, a first molding layer 180 is formed on the back side of the second sub-silicon interposer 172 and the front side of the fourth sub-silicon interposer 174. And a plurality of first through holes are formed in the first molding layer 180 along the thickness direction thereof, and a conductive material is filled in the plurality of first through holes to form a plurality of first conductive studs 181.

As shown in fig. 21, the side of the first plastic layer 180 facing away from the carrier 110 is polished and thinned to expose the interconnection conductive structures on the back side of the second sub-silicon interposer 172 and the front side of the fourth sub-silicon interposer 174, that is, to expose the plurality of through silicon vias on the back side of the second sub-silicon interposer 172 and the plurality of solder balls on the front side of the fourth sub-silicon interposer 174, and to expose the first conductive bumps 181. Wherein the back side of the thinned second sub-silicon interposer 172 is flush with the front side of the fourth sub-silicon interposer 174.

As shown in fig. 22, a second molding layer 191 is formed on a side of the plurality of hetero chips facing away from the rear surface of the plurality of second sub-silicon intermediaries 172 and the fourth sub-silicon intermediaries 174, exposing the surfaces of the plurality of hetero chips facing the rear surface of the plurality of second sub-silicon intermediaries 172 and the fourth sub-silicon intermediaries 174, and a first metal pad 131 and a first passivation layer 132 are formed on the surfaces of the plurality of hetero chips facing the rear surface of the plurality of second sub-silicon intermediaries 172 and the fourth sub-silicon intermediaries 174.

As shown in fig. 22, a second passivation layer 182 and a second metal pad 183 are formed on the back surface of the thinned second sub-silicon interposer 172 and the front surface of the fourth sub-silicon interposer 174.

In this embodiment, the material of the first passivation layer 132 and the second passivation layer 183 may be a silicon dioxide passivation layer or a silicon nitride layer, or may be other materials that can perform passivation, which is not specifically limited in this embodiment. The material of the first metal pad 131 and the second metal pad 183 may be copper metal or other metal materials, and the embodiment is not particularly limited.

As shown in fig. 22, the first metal pad 131 and the second metal pad 183 are bonded, and the first passivation layer 132 and the second passivation layer 182 are bonded, wherein the first metal pad 131 also corresponds to and is electrically connected with the first conductive stud 181, so as to perform hybrid bonding between the plurality of heterogeneous chips 130 and the back surface of the thinned second sub-silicon interposer 172 and the front surface of the fourth sub-silicon interposer 174.

As shown in fig. 23, the carrier plate 110 is removed, and a first interconnect wiring layer 192 is formed on the front side of the second sub-silicon interposer 172 and the back side of the fourth sub-silicon interposer 174. The package structure is electrically connected to the outside through the first interconnection line layer 192.

In this embodiment, a plurality of heterogeneous chips are bonded to a plurality of target sub-silicon interposer boards by a hybrid bonding process, so that high-density interconnection is realized, production efficiency is improved, and ultra-thin packaging is realized.

In the above embodiment, when the first sub-silicon interposer 171 or the second sub-silicon interposer 172 is selected from the target sub-silicon interposers, the front surface of the first sub-silicon interposer 171 or the second sub-silicon interposer 172 needs to be fixed on the carrier 110, and the height of the first sub-silicon interposer 171 or the second sub-silicon interposer 172 needs to be equal to that of the other target sub-silicon interposers, so that the packaging process in the above embodiment can be performed.

For example, when the interconnection conductive structure of at least one target sub-silicon interposer is a plurality of blind holes filled with conductive material, and the front surface of the target sub-silicon interposer is fixed on the carrier, the height of at least one target sub-silicon interposer is lower than the height of other target sub-silicon interposers;

Bonding the plurality of heterogeneous chips to the plurality of target daughter silicon interposer, comprising:

The side of the first plastic layer 180 facing away from the carrier plate 110 is thinned to expose the interconnect conductive structures of the plurality of high-level target sub-silicon interposer facing away from the carrier plate 110.

Through the first bonding structure, a side of the heterogeneous chips 130 and the second plastic layer 191 facing the target sub-silicon interposer is bonded to a side of the thinned target sub-silicon interposer with a height away from the carrier 110.

Bonding a plurality of heterogeneous chips 130 and a second plastic layer towards one side of the plurality of target sub-silicon intermediaries and one side of the thinned high target sub-silicon intermediaries away from the carrier 110 through a second bonding structure; wherein the height of the first bonding structure is greater than the height of the second bonding structure.

After bonding the plurality of heterogeneous chips to the plurality of target daughter silicon interposer, further comprising:

the carrier plate 110 is removed and a first interconnect line layer 192 is formed on a side of the plurality of target sub-silicon interposer facing the carrier plate 110.

Specifically, as shown in fig. 24 to 30, in another embodiment, a plurality of third sub-silicon intermediaries 173 and fourth sub-silicon intermediaries 174 are selected to be recombined as target sub-silicon intermediaries, wherein the height of the third sub-silicon intermediaries 173 is higher than the height of the fourth sub-silicon intermediaries 174.

As shown in fig. 26, a second molding layer 191 is formed on a side of the plurality of hetero chips 130 facing away from the plurality of third and fourth

sub-silicon intermediaries

173 and 174. First metal pads 131 and a first passivation layer 132 are formed on sides of the plurality of hetero chips 130 and the second molding layer 191 toward the third and fourth

sub-silicon intermediaries

173 and 174. In the present embodiment, the first metal pads 131 at the corresponding third sub-silicon interposer 173 and the first pads at the corresponding fourth sub-silicon interposer 174 are uniform in height.

As shown in fig. 24, the front surface of the third sub-silicon interposer 173 and the back surface of the fourth sub-silicon interposer 174 are fixed to the carrier 110. The back side of the plurality of third sub-silicon interposer 173 and the front side of the fourth sub-silicon interposer 174 are formed into a first molding layer 180. And a plurality of first through holes are formed in the first molding layer 180 along the thickness direction thereof, and a conductive material is filled in the plurality of first through holes to form a plurality of first conductive studs 181.

As shown in fig. 25, the side of the first molding layer 180 facing away from the back side of the third sub-silicon interposer 173 and the front side of the fourth sub-silicon interposer 174 is thinned to expose the interconnect conductive structures on the back side of the third sub-silicon interposer 173, i.e., to expose the plurality of through silicon vias on the back side of the third sub-silicon interposer 173. The front side of the fourth plurality of sub-silicon interposer 174 is also encapsulated by the first molding layer 180.

As shown in fig. 28, the second passivation layer 182 is formed on the back surface of the thinned third sub-silicon interposer 173 and the surface of the first molding layer 180 wrapping the fourth sub-silicon interposer 174 on the side facing away from the fourth sub-silicon interposer 174.

As shown in fig. 28, the second passivation layer 182 is patterned by photolithography and etching, etc., to form a plurality of first openings 185 on the second passivation layer 182 corresponding to the third sub-silicon interposer 173, and a plurality of second openings 186 on the second sub-passivation layer 182 corresponding to the fourth sub-silicon interposer 174. Wherein the depth of the second opening 186 is greater than the depth of the first opening 185, and the bottom of the second opening 186 extends to the fourth interconnect conductive structure 154 and corresponds to the fourth interconnect conductive structure 152, and the depth of the first opening 185 also extends to the third interconnect conductive structure 153 and corresponds to the third interconnect conductive structure 153.

As shown in fig. 29, first and second

sub-metal pads

183a and 183b are formed at the plurality of first and

second openings

185 and 186, respectively, by a plating or sputtering process or the like. Wherein the length dimension of the second sub-metal pad 183b is greater than the length dimension of the first sub-metal pad 183a.

As shown in fig. 29, the first passivation layer 132 is bonded to the second passivation layer 182, and the first metal pad 131 is bonded to the first and second

sub-metal pads

183a and 183b, respectively.

That is, the first hybrid bonding structure includes the first passivation layer 132 corresponding to the fourth sub-silicon interposer 174, the second passivation layer 182 corresponding to the fourth sub-silicon interposer 174, the first metal pad 131 corresponding to the fourth sub-silicon interposer 174, and the second sub-metal pad 183b.

The second bonding structure includes a first passivation layer 132 corresponding to the third sub-silicon interposer 173, a second passivation layer 182 corresponding to the third sub-silicon interposer 173, a first metal pad 131 corresponding to the third sub-silicon interposer 173, and a first sub-metal pad 183a.

The plurality of hetero chips 130 are hybrid-bonded with the front surfaces of the plurality of fourth sub-silicon intermediaries 174 and the back surfaces of the third sub-silicon intermediaries 173 by the first bonding structure bonding the second bonding structure.

Illustratively, after bonding the plurality of hetero-chips to the front side of the plurality of fourth sub-silicon intermediaries 174 and the back side of the third sub-silicon intermediaries 173, the packaging method further comprises:

as shown in fig. 30, the carrier plate 110 is removed, and a first interconnect wiring layer 192 is formed on the back surface of the plurality of fourth sub-silicon interposer 174 and the front surface of the third sub-silicon interposer 173.

In another embodiment, as shown in fig. 31 to 33, a plurality of fourth sub-silicon intermediaries 174 and a plurality of third sub-silicon intermediaries 173 are selected as target sub-silicon intermediaries, wherein the height of the fourth sub-silicon intermediaries 174 is lower than the height of the third sub-silicon intermediaries 173.

As shown in fig. 31, a second molding layer 191 is formed on a side of the plurality of hetero chips 130 facing away from the fourth sub-silicon interposer 174 and the third sub-silicon interposer 173.

As shown in fig. 31, a first passivation layer 132 is formed on a side of the plurality of hetero chips 130 and the second molding layer 191 facing the fourth sub-silicon interposer 174 and the third sub-silicon interposer 173. The first passivation layer 132 is patterned by photolithography and etching, a first sub-metal pad 131a is formed on the patterned first passivation layer 132 corresponding to the third sub-silicon interposer 173, and a second sub-metal pad 131b is formed on the patterned first passivation layer 132 corresponding to the fourth sub-silicon interposer 174. Wherein the second sub-metal pads 131b corresponding to the fourth sub-silicon interposer 172 have a longer length dimension than the first sub-metal pads 131a corresponding to the third sub-silicon interposer 173.

As shown in fig. 32, the front surface of the third sub-silicon interposer 173 and the back surface of the fourth sub-silicon interposer 174 are fixed to the carrier 110.

As shown in fig. 32, a first molding layer 180 is formed on the back side of the third sub-silicon interposer 173 and the front side of the fourth sub-silicon interposer 174. And a plurality of first through holes are formed in the first molding layer 180 along the thickness direction thereof, and a conductive material is filled in the plurality of first through holes to form a plurality of first conductive studs 181.

As shown in fig. 32, the side of the first molding layer 180 facing away from the third sub-silicon interposer 173 and the fourth sub-silicon interposer 174 is thinned to expose the interconnect conductive structures 153 on the back side of the plurality of third sub-silicon interposers 173, while the back side of the plurality of second sub-silicon interposers 172 is still encapsulated by the first molding layer 180.

As shown in fig. 32, a third sub-metal pad 183a is formed on the back surface of the thinned plurality of third sub-silicon interposer 173.

As shown in fig. 32, a second passivation layer 182 is formed on the third sub-metal pad 183a and on the surface of the first molding layer 180 corresponding to the front surface of the fourth sub-silicon interposer 174.

As shown in fig. 32, the second passivation layer 182 is patterned by a photolithography and etching process to form a plurality of second openings 186 on the first molding layer 180 corresponding to the second passivation layer 182 and the second passivation layer 182 on the fourth sub-silicon interposer 174. Wherein the depth of the second opening 186 is identical to the length of the second sub metal pad 131b of the corresponding fourth sub silicon interposer 172.

As shown in fig. 33, the first passivation layer 132 and the second passivation layer 182 are bonded, the first sub-metal pad 131a corresponding to the third sub-silicon interposer 173 and the third sub-metal pad 183a are bonded, and the second sub-metal pad 131a corresponding to the fourth sub-silicon interposer 174 is inserted into the second opening 186 corresponding thereto, thereby completing hybrid bonding of the plurality of heterogeneous chips 130 and the back surfaces of the plurality of second sub-silicon intermediaries 172 and the front surfaces of the fourth sub-silicon intermediaries 174.

That is, in the present embodiment, the first hybrid bonding structure includes the first passivation layer 132, the second passivation layer 182 corresponding to the fourth sub-silicon interposer 174, and the second metal pad 131a corresponding to the fourth sub-silicon interposer 174.

The second bonding structure includes a first passivation layer 132, a second passivation layer 182 corresponding to the third sub-silicon interposer 173, a first metal pad 131a and a third sub-metal pad 183a corresponding to the third sub-silicon interposer 173, respectively.

The plurality of hetero chips 130 are hybrid-bonded with the front surfaces of the plurality of fourth sub-silicon intermediaries 174 and the back surfaces of the plurality of third sub-silicon intermediaries 173 by the first bonding structure and the second bonding structure.

After the plurality of hetero chips 130 are mixed-bonded with the front sides of the plurality of fourth sub-silicon intermediaries 174 and the back sides of the plurality of third sub-silicon intermediaries 173, the packaging method further includes:

As shown in fig. 33, the carrier plate 110 is removed, and a first interconnect wiring layer 192 is formed on the back surface of the plurality of fourth sub-silicon intermediaries 174 and the front surface of the plurality of third sub-silicon intermediaries 173.

In the packaging process of the present embodiment, at least one or both of the first sub-silicon interposer 171, the second sub-silicon interposer 172, the third sub-silicon interposer 173, and the fourth sub-silicon interposer 174 may be selected and combined as the target sub-silicon interposer, for example, a combination of the plurality of second sub-silicon interposers 172 and the third sub-silicon interposer 173 may be selected as the target sub-silicon interposer, and the like, and the present invention is not limited to the combination of the target sub-silicon interposers in the present embodiment. However, the above-described packaging process may be performed only by selecting the first sub-silicon interposer 171, and fixing the front surface of the first sub-silicon interposer 171 to the carrier 110 is particularly limited. If other types of sub-silicon interposer are used as the target sub-silicon interposer, the surface of the target sub-silicon interposer to be fixed on the carrier plate need not be particularly limited. The type of the target sub-silicon interposer is not particularly limited.

Optionally, after forming the first interconnect line layer 192 on the back side of the plurality of fourth sub-silicon intermediaries 174 and the front side of the plurality of third sub-silicon intermediaries 173, the packaging method further includes:

As shown in fig. 34, in the present embodiment, a plurality of second through holes are formed in the thickness direction penetrating the first molding layer 180 and the second molding layer 191. A plurality of second conductive posts 193 are formed by filling a conductive material in the plurality of second vias. A second interconnect line layer 194 is formed on a side of the second molding layer 192 facing away from the plurality of target sub-silicon interposer. Wherein, two ends of the plurality of second conductive studs 193 are electrically connected with the first interconnection line layer 192 and the second interconnection line layer 194, respectively. The packaging of the plurality of heterogeneous chips 130 and the plurality of target sub-silicon interposer is completed.

The plurality of second conductive pillars 193 may enable vertical electrical interconnection between the heterogeneous chip package structure and other heterogeneous chips or modules, and reduce package height.

It should be noted that, in the present embodiment, the second interconnect line layer 194 includes a dielectric layer and a metal layer, where the metal layer may be formed by electroplating or directly formed by pasting. In this embodiment, the second interconnect line layer 194 may be a microstrip antenna radiating patch. Both ends of the plurality of second conductive pillars 193 are electrically connected to the metal layer in the second interconnect line layer 194 and the metal layer in the rewiring layer in the first interconnect line layer 192, respectively. A second interconnect line layer 194 is formed on a side of the second molding layer 192 facing away from the plurality of target sub-silicon interposer, the second interconnect line layer 194 may enhance the signals of the overall package structure.

The packaging structure comprises a second interconnection line layer, and the communication type heterogeneous chip or module can be arranged on the packaged second interconnection line layer.

It should be noted that, in the heterogeneous chip packaging process in the above embodiments, the plurality of second conductive pillars 193 may be formed in the thickness direction penetrating the first molding layer 180 and the second molding layer 191, and the second interconnect line layer 194 may be formed on the side of the second molding layer 191 facing away from the plurality of target sub-silicon intermediaries. And will not be described in detail herein.

It is to be understood that the above implementations are merely exemplary implementations employed to illustrate the principles of the disclosed embodiments, which are not limited thereto. Various modifications and improvements may be made by those skilled in the art without departing from the spirit and substance of the embodiments of the disclosure, and these modifications and improvements are also considered to be within the scope of the embodiments of the disclosure.

Claims

1. The fan-out type heterogeneous chip packaging method is characterized by comprising the following steps of:

2. The fan-out heterogeneous chip packaging method according to claim 1, wherein the selecting a plurality of target sub-silicon intermediaries from the plurality of sub-silicon intermediaries, and fixing a first surface of at least one of the target sub-silicon intermediaries to a carrier, and fixing a second surface of the remaining target silicon intermediaries to the carrier, comprises:

3. The fan-out heterogeneous chip packaging method of claim 1, wherein forming the interconnection conductive structures on the plurality of silicon chips respectively comprises:

4. The fan-out heterogeneous chip packaging method of claim 1, wherein the forming of the interconnection conductive structures on the plurality of silicon chips, respectively, further comprises:

filling conductive materials in the blind holes;

5. The fan-out heterogeneous chip packaging method of claim 1, wherein the forming of the interconnection conductive structures on the plurality of silicon chips, respectively, further comprises:

filling conductive materials in the blind holes;

forming a rewiring layer on the blind holes;

filling conductive materials in the blind holes;

forming a rewiring layer on the blind holes;

forming a plurality of solder balls on the rewiring layer;

6. The fan-out heterogeneous chip packaging method according to any one of claims 1 to 5, wherein after forming a first molding layer on a side of the plurality of target sub-silicon intermediaries facing away from the carrier board, or after bonding the plurality of heterogeneous chips to the plurality of target sub-silicon intermediaries, further comprising:

7. The fan-out heterogeneous chip packaging method according to any one of claims 1 to 5, wherein when the interconnection conductive structure of at least one target sub-silicon interposer is a plurality of blind holes or a plurality of through silicon vias filled with conductive material, the first surface of the target sub-silicon interposer is fixed to the carrier board, and the height of the target sub-silicon interposer is higher than that of other target sub-silicon interposers;

8. The fan-out heterogeneous chip packaging method of claim 7, wherein,

9. The fan-out heterogeneous chip packaging method according to any one of claims 1 to 5, wherein at least one of the target sub-silicon interposer has a height lower than that of the other target sub-silicon interposer;

10. The fan-out heterogeneous chip packaging method according to claim 9, wherein after the plurality of target sub-silicon intermediaries forms the first interconnect wiring layer toward the side of the carrier, further comprising: