CN115881554A

CN115881554A - Heterogeneous chip packaging method

Info

Publication number: CN115881554A
Application number: CN202211553696.1A
Authority: CN
Inventors: 李骏; 戴颖; 石磊; 夏鑫
Original assignee: Tongfu Microelectronics Co Ltd
Current assignee: Tongfu Microelectronics Co Ltd
Priority date: 2022-12-06
Filing date: 2022-12-06
Publication date: 2023-03-31

Abstract

The embodiment of the disclosure provides a heterogeneous chip packaging method, which includes: providing a substrate, a plurality of silicon wafers and a plurality of heterogeneous chips; forming a plurality of groups of conductive connection structures on the first surfaces of the silicon wafers respectively to obtain a plurality of silicon intermediate plates; respectively cutting the silicon medium plates to obtain a plurality of silicon medium blocks; selecting a plurality of target silicon interposers from the plurality of silicon interposers and fixing first surfaces of the plurality of target silicon interposers on the substrate; a plurality of heterogeneous chip interconnects are disposed on the corresponding plurality of target silicon interposer blocks, respectively. The large silicon interposer is cut into small silicon interposer blocks, and warping and cracking of the silicon interposer during thinning are avoided. The silicon medium blocks with different specifications are combined according to the installation requirements of the heterogeneous chips, are correspondingly installed with the heterogeneous chips and can be formed at one time, the whole area of the silicon medium layer and the distance between the chips are reduced, and the integration level of the whole package is greatly improved.

Description

Heterogeneous chip packaging method

Technical Field

The disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a heterogeneous chip packaging method.

Background

In the 2.5D package technology, the silicon interposer is mainly an intermediate structure connected between the chip and the substrate for amplifying and transmitting signals of the chip to the substrate. At present, the thinner the chip package is, and a plurality of chips may be connected to the silicon interposer, so when the chip is mounted on the silicon interposer and the silicon interposer is thinned, the warpage and even the crack of the silicon interposer are easily caused. And the integration level of the existing silicon interposer and chip is yet to be further improved.

Disclosure of Invention

Embodiments of the present disclosure are directed to solving at least one of the technical problems in the prior art, and provide a heterogeneous chip packaging method.

The packaging method comprises the following steps:

providing a substrate, a plurality of silicon wafers and a plurality of heterogeneous chips;

forming a plurality of groups of conductive connection structures on the first surfaces of the silicon wafers respectively to obtain a plurality of silicon intermediate plates; wherein at least one of the silicon interposers is different from the other silicon interposers;

respectively cutting the plurality of silicon medium plates to obtain a plurality of silicon medium blocks; wherein the plurality of silicon interposer blocks are all equal in thickness;

selecting a plurality of target silicon interposers from the plurality of silicon interposers and fixing first surfaces of the plurality of target silicon interposers on the substrate;

the plurality of heterogeneous chip interconnects are disposed on the corresponding plurality of target silicon interposer blocks, respectively.

Optionally, the method for forming at least one silicon interposer includes:

forming a plurality of groups of blind holes on the first surface of the silicon wafer;

and filling conductive materials in the plurality of groups of blind holes to form the conductive connection structure, so as to obtain the silicon interposer.

Optionally, the method for forming at least one silicon interposer includes:

filling conductive materials in the plurality of groups of blind holes to form the conductive connection structure;

and thinning the second surface of the silicon wafer until the conductive connecting structure is exposed to form a through silicon via, and obtaining the silicon interposer.

Optionally, the method for forming at least one silicon interposer includes:

filling conductive materials in the multiple groups of blind holes;

and arranging a rewiring layer on the first surface of the silicon wafer to form the conductive connection structure, so as to obtain the silicon interposer.

Optionally, the method for forming at least one silicon interposer includes:

filling conductive materials in the multiple groups of blind holes;

arranging a rewiring layer on the first surface of the silicon wafer to form the conductive connection structure;

Optionally, the method for forming at least one silicon interposer includes:

filling conductive materials in the multiple groups of blind holes;

arranging a rewiring layer on the first surface of the silicon wafer;

and arranging solder balls on the redistribution layer to form the conductive connection structure, so as to obtain the silicon interposer.

The forming method of at least one silicon interposer comprises the following steps:

filling conductive materials in the multiple groups of blind holes;

arranging a rewiring layer on the first surface of the silicon wafer;

arranging solder balls on the rewiring layer to form the conductive connection structure;

Optionally, the fixing the first surfaces of the plurality of target silicon interposer blocks on the substrate further comprises:

fixing the first surface of each target silicon intermediate block at a corresponding position on a substrate;

prefabricating a plurality of conductive columns on the substrate, and plastically packaging the conductive columns on the substrate and the target silicon medium blocks; or the like, or a combination thereof,

plastically packaging the target silicon intermediate blocks on the substrate to form a plastic packaging layer, forming a plurality of through holes along the thickness direction of the plastic packaging layer, and filling conductive materials into the through holes to form the conductive columns;

wherein the conductive posts are used for electrically connecting the substrate and the chip.

Optionally, one surface of the substrate is provided with a plurality of grooves; said securing first surfaces of said plurality of target silicon interposer blocks on said substrate comprises:

and fixing the first surface of each target silicon intermediate block in the corresponding groove.

Optionally, the substrate is provided with a plurality of through grooves; the securing the first surfaces of the plurality of target silicon interposer blocks on the substrate further comprises:

fixing one surface of the substrate to a temporary carrier plate;

and fixing the first surface of each target silicon intermediate block in the corresponding through groove and on the temporary carrier plate.

Optionally, the plurality of heterogeneous chips are fixed on a carrier plate for plastic packaging, and then the carrier plate is removed to obtain a chip recombinant.

According to the heterogeneous chip packaging method, the large silicon interposer is cut into the small silicon interposer, and warping and cracking of the silicon interposer in the thinning process are avoided. The silicon medium blocks with different specifications are combined according to the installation requirements of the heterogeneous chips, are correspondingly installed with the heterogeneous chips and can be formed at one time, the whole area of the silicon medium layer and the distance between the chips are reduced, and the integration level of the whole package is greatly improved.

Drawings

Fig. 1 is a flowchart of a heterogeneous chip packaging method according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of a method for forming a silicon interposer according to another embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a method for forming a silicon interposer according to another embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a method for forming a silicon interposer according to another embodiment of the present disclosure;

fig. 5 is a schematic diagram of a chip interconnection setup method according to another embodiment of the disclosure;

FIG. 6 is a schematic diagram of a method for providing a chip interconnect in accordance with another embodiment of the present disclosure;

fig. 7 is a schematic diagram of a chip interconnection setup method according to another embodiment of the disclosure;

fig. 8 is a schematic diagram of a chip interconnection setup method according to another embodiment of the disclosure;

fig. 9 is a schematic diagram of a chip interconnection setup method according to another embodiment of the disclosure;

fig. 10 is a schematic diagram of a chip interconnection setup method according to another embodiment of the disclosure;

fig. 11 is a schematic diagram of a chip interconnection arrangement method according to another embodiment of the disclosure;

Detailed Description

In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

As shown in fig. 1, a heterogeneous chip packaging method according to an embodiment of the present disclosure includes:

s11, providing a substrate, a plurality of silicon wafers and a plurality of heterogeneous chips.

Specifically, embodiments of the present disclosure provide three substrates (substrates), the first being a conventional Substrate having a shape of a plate with at least upper and lower flat surfaces; the second substrate is based on the first substrate, and a plurality of grooves are etched at each preset position on one flat surface, for convenience of description, the embodiments of the disclosure assume a general case that the depths of the plurality of grooves are all equal; the third substrate is formed by etching through at each preset position on one flat surface of the first substrate to form a plurality of through grooves. A plurality of heterogeneous chips are chips to be packaged in the embodiment of the present disclosure, and "heterogeneous" means that the specification of each single chip is arbitrary.

The heterogeneous chip packaging method provided by the embodiment of the disclosure can be suitable for various substrates and various chips with different specifications, and can meet various packaging requirements in modern chip packaging technology.

Preferably, the heterogeneous chips are fixed on a carrier plate for plastic package, and then the carrier plate is removed to obtain a chip recombinant. Therefore, a plurality of preset heterogeneous chips can be packaged into a whole for bonding with a silicon interposer (Si interposer) and a substrate in a subsequent whole, steps are saved, operation is facilitated, and the integration level of the whole is improved.

S12, forming a plurality of groups of conductive connection structures on the first surfaces of the silicon wafers respectively to obtain a plurality of silicon intermediate boards; wherein at least one of the silicon interposers is different from the other silicon interposers.

Specifically, embodiments of the present disclosure provide a six-type silicon interposer with the formation step as a distinction. Each type of silicon interposer can be further subdivided into a plurality of different types according to the different depths, widths, densities, etc. of the formed holes, and usually only one type of silicon interposer is processed for each silicon wafer.

As shown in fig. 2, the first type of silicon interposer is formed by the following steps: s21, forming a plurality of groups of blind holes on the first surface of the silicon wafer. S22, filling conductive materials in the multiple groups of blind holes to form the conductive connection structure, and obtaining the silicon interposer.

As shown in fig. 2, on the basis of the first type of silicon interposer, adding S23, and thinning the second surface of the silicon wafer until the conductive connection structure is exposed to form a through hole, thereby obtaining the silicon interposer. Thus, a second type silicon interposer is formed.

As shown in fig. 3, the third type silicon interposer is formed by the following steps: s31, forming a plurality of groups of blind holes on the first surface of the silicon wafer. And S32, filling conductive materials in the multiple groups of blind holes. And S33, arranging a ReDistribution Layer (RDL) on the first surface of the silicon wafer to form the conductive connection structure, so as to obtain the silicon interposer.

As shown in fig. 3, on the basis of the third type silicon interposer, adding S34 and thinning the second surface of the silicon wafer until the conductive connection structure is exposed to form a through hole, thereby obtaining the silicon interposer. Thus, a fourth type silicon interposer is formed.

As shown in fig. 4, a fifth type silicon interposer is formed by the following steps: s41, forming a plurality of groups of blind holes on the first surface of the silicon wafer. And S42, filling conductive materials in the multiple groups of blind holes. S43, arranging a rewiring layer on the first surface of the silicon wafer. And S44, arranging solder balls (Bump) on the redistribution layer to form the conductive connection structure, so as to obtain the silicon interposer.

As shown in fig. 4, on the basis of the fifth type silicon interposer, adding S45, and thinning the second surface of the silicon wafer until the conductive connection structure is exposed to form a through hole, thereby obtaining the silicon interposer. Thus, a sixth type silicon interposer is formed.

Embodiments of the present disclosure provide a silicon interposer with a plurality of different conductive connection structures, which can meet various packaging requirements in combination with the aforementioned substrate and the heterogeneous chip.

S13, respectively cutting the silicon medium plates to obtain a plurality of silicon medium blocks; wherein the plurality of silicon interposer blocks are all equal in thickness.

Specifically, the silicon interposer obtained in the above steps can be cut into silicon interposer blocks with different specifications. That is, the conductive connection structure and the depth, width, and density of the holes are different for each silicon interposer. In embodiments of the present disclosure, the thickness of all silicon interposer blocks is cut to be uniform.

The embodiment of the disclosure cuts the large silicon interposer into small silicon interposer blocks, avoiding warpage and cracking of the silicon interposer during thinning. Different types of silicon intermediate blocks can be combined together at will according to the packaging requirements, and the integration level is improved.

S14, selecting a plurality of target silicon intermediate blocks from the plurality of silicon intermediate blocks, and fixing the first surfaces of the plurality of target silicon intermediate blocks on the substrate.

Specifically, according to the pin arrangement of the chip to be packaged, if the substrate is provided with the groove or the through groove, the silicon intermediate block required to be used in the packaging process is determined according to the position of the groove or the through groove, so that the conductive connection structure on the silicon intermediate block can be correspondingly connected with the pins of the chip, and the chip is convenient to conduct. The silicon interposer thus selected is the target silicon interposer. These target silicon interposers are secured to corresponding locations or within corresponding slots on the substrate and their first surfaces are bonded to the substrate.

According to the embodiment of the disclosure, the silicon medium blocks with different specifications are combined and installed on the substrate at will, so that heterogeneous chips with different specifications can be installed on the corresponding silicon medium blocks as required, and the integral integration level is improved.

S15, respectively arranging the heterogeneous chips on the corresponding target silicon intermediate blocks in an interconnecting mode.

Specifically, before and after the step, a plurality of sets of parallel different implementation flows are required to be completed according to different types of substrates, different types of target silicon intermediate blocks and the shapes of the target silicon intermediate blocks placed in the grooves. In order to make the technical effects of the present disclosure and the technical solutions of the present disclosure clear and complete, some different implementation flows are illustrated below.

The first embodiment is as follows:

as shown in fig. 5, a plurality of target silicon interposer 51 with blind vias and a planar substrate 52 are taken. First, the first surface, which is the open surface of the blind hole of each target silicon interposer 51, is fixed to a position corresponding to the surface of the substrate 52.

Then, a plurality of conductive pillars 53 are preset in the vacant positions on the substrate 52 where the target silicon interposer 51 is not fixed, and the conductive pillars 53 may be copper pillars; the height of the conductive post 53 is greater than the height of the lowest blind via. And then the target silicon intermediate block 51 and the conductive post 53 on the substrate 52 are integrally molded to form a molding layer 54.

The molding layer 54 is then ground down until all the blind holes are exposed, i.e., all the blind holes become through holes. At this time, the conductive post 53 is also exposed.

Finally, re-wiring (RDL) is performed on the thinned plane, and the chip recombinant 55 is flipped on the re-wiring layer 57 through bumps (Bump) 56, so as to complete the interconnection of the plurality of chips on the plurality of target silicon interposers.

As another scheme, "a plurality of conductive pillars are preset in the vacant areas on the substrate where the target silicon interposer is not fixed, where the conductive pillars may be copper pillars, etc.; the height of the conductive column is greater than that of the lowest blind hole. And then the target silicon intermediate block and the conductive column on the substrate are subjected to integral plastic package to form a plastic package layer, which can be replaced by:

the method comprises the steps of carrying out integral plastic package on a target silicon intermediate block on a substrate to form a plastic package layer, then forming through holes in the thickness direction of the plastic package layer by using a TMV (thermoplastic glass) process, and filling conductive materials such as copper into the through holes to form conductive columns. When the plastic package layer is perforated by a TMV process, attention needs to be paid to the protection of the substrate.

Additionally, the side of the substrate 52 facing away from the target silicon interposer 51 may be subsequently ball bumped (Bumping) for further possible operations on the process, such as stacking of chips, etc.

Example two:

as shown in fig. 6, a plurality of target silicon interposer blocks 61 with blind vias and a substrate 62 with grooves etched in corresponding locations are taken. First, the first surfaces of all the target silicon intermediate blocks 61 are respectively fixed in the corresponding grooves previously etched on the substrate 62. The height of all the blind holes of the target silicon interposer 61 should be greater than or equal to the plane of the substrate 62 except for the grooves.

All of the target silicon interposer 61 is then ground down to be flush with the surface of the substrate 62 except for the recess. At this point, the blind holes of the target silicon interposer 61 are exposed.

Finally, arranging bonding structures 63 on the thinned flush surfaces, and fixing the chip recombinant 64 on the target silicon intermediate blocks 61 through the bonding structures 63 to complete the interconnection arrangement of the chips on the target silicon intermediate blocks.

Additionally, the side of the substrate facing away from the groove can be thinned subsequently until the target silicon interposer is exposed, and rewiring, ball mounting and the like can be performed on the thinned plane for further possible operations on the process, such as stacking of chips and the like.

Example three:

as shown in fig. 7, a plurality of target silicon interposers 71 having through holes and a substrate 72 in which grooves are etched in advance are taken, and the depth of the grooves is the same as the height of the target silicon interposers 71.

The target silicon interposer 71 is first secured in the corresponding recess.

The side of the substrate 72 facing away from the recess is then ground down until the target silicon interposer 71 is exposed.

Finally, a plurality of heterogeneous chips 73 with different specifications are fixed on the corresponding target silicon interposer. The chip 73 may be fixed to the original side of the target silicon interposer 71 having the conductive connection structure, or may be fixed to the newly exposed side of the target silicon interposer 71 after thinning, so as to complete the interconnection of the plurality of chips 73 on the plurality of target silicon interposers 71.

Additionally, the substrate and the side surface of the target silicon interposer not bonded to the chip may be subsequently re-routed, ball-mounted, etc. for further possible further operations on the process, such as stacking of chips, etc.

Example four:

as shown in fig. 8, a plurality of target silicon intermediate blocks 81 having through holes are taken, and a substrate 82 with grooves etched in advance is taken; the height of the single target silicon interposer 81 is lower than or equal to the height of the recess on the substrate 82.

First, the first surface of the target silicon interposer 81 is fixed in a corresponding recess on the substrate 82.

Subsequently, a bonding structure 84 is disposed on the chip recombinant 83 at a position corresponding to the silicon interposer 81 having a height lower than the groove, as described above, and the height of the bonding structure 84 is just equal to the height difference between the target silicon interposer 81 and the groove.

Finally, the chip recombinants 83 are disposed on the plurality of target silicon interposer blocks 81 through the bonding structures 84.

Example five:

as shown in fig. 9, a plurality of target silicon interposers 91 having through-holes and a substrate 92 with grooves etched in advance are taken. All of the target silicon interposer 91 have a uniform height and are higher than the height of the grooves on the substrate 92.

First, the first surface of the target silicon interposer 91 is fixed in the corresponding groove on the substrate 92, and the ball is planted on the same surface of the substrate 92 as the groove except the groove, and the height of the planted solder ball 93 is just equal to the height difference between the target silicon interposer 91 and the groove.

A planar package substrate 94 is then taken and mounted on the solder balls 93, i.e., on the target silicon interposer 91. An underfill is filled in the gap between the substrate 92 and the package substrate 94 and the solder ball 93.

Finally, the surface of the substrate 92, which is away from the package substrate 94, is ground to thin until the target silicon interposer 91 is exposed. The chip recombinants 95 described above are then interconnected on the plurality of target silicon interposer blocks 91.

Example six:

as shown in fig. 10, a plurality of target silicon interposer blocks 101 with blind holes and a substrate 102 with through grooves etched in advance are taken, and a temporary carrier plate 103 is taken. A film 104 is attached to one surface of the temporary carrier 103, and the substrate 102 is adhered to the temporary carrier 103 through the film 104.

First, the first surface of the target silicon interposer 101 is fixed in the corresponding through-groove of the substrate 102 and attached to the temporary carrier 103. The height of all the target silicon intermediate blocks 101 is greater than that of the through grooves, and the height of all the blind holes is greater than or equal to that of the through grooves.

The side of the target silicon interposer 101 facing away from the temporary carrier 103 is then ground down to the same height as the substrate 102, and a bonding structure 105 is formed on the thinned plane.

Finally, the chip recombinants 106 are interconnected and disposed on the corresponding target silicon interposer blocks 101 through the bonding structures 105, the temporary carrier 103 is removed, and a package substrate 107 is taken to replace the original temporary carrier 103 and is attached to the substrate 102 and the target silicon interposer blocks 101.

For example, as shown in fig. 10, if the target silicon interposer 101 has solder balls 108 on one surface attached to the temporary carrier, the solder balls may protrude from the surface of the substrate 102 after removing the temporary carrier 103. At this time, the solder balls 109 may be implanted on the surface of the substrate 102 except the through-groove portion, and the height of the implanted solder balls 109 is just equal to the height of the solder balls 108 on the target silicon interposer 101 protruding from the surface of the substrate. A package substrate 107 is then attached to all of the solder balls and the voids are filled with underfill.

Example seven:

as shown in fig. 11, a plurality of target silicon interposers 111 with through holes and a plurality of target silicon interposers 112 with blind holes are taken, and a substrate 113 with grooves etched in advance is taken.

First, the target silicon interposer 111 is fixed in a corresponding recess of the substrate 113, and has a thickness just as high as the recess. The first surface of the target silicon interposer 112 is fixed in the corresponding groove of the substrate 113, and the thickness of the first surface is larger than the height of the groove, and the height of the blind hole exceeds the groove.

The side of the target silicon interposer 112 facing away from the substrate 113 is then ground down to the same height as the substrate 113, at which point the blind vias in the target silicon interposer 112 are exposed and become through vias. And grinding and thinning the non-groove-etched surface of the substrate 113 until all the target silicon intermediate blocks are exposed.

Finally, the chip recombinants described above are disposed on either side of the substrate 113 through the target silicon interposer interconnects.

Additionally, the substrate and the other side of the target silicon interposer where no chip is disposed may be subsequently re-routed, ball-mounted, etc. for further possible operations on the process, such as stacking of chips, etc.

It should be noted that the bonding structure described in the embodiments of the present disclosure generally includes a copper bump on the surface of its carrier (substrate, chip or silicon interposer), and a SiO2 layer or a SiCN layer (collectively referred to as a passivation layer) around the copper bump and at the same height as the copper bump. In addition, in the embodiment of the disclosure, if a mode that a plurality of chips are combined into a chip recombinant and then the chip recombinant is integrally interconnected and arranged on the target silicon intermediate block is not used, a bonding mode that a single chip is respectively inverted and then the whole is integrally subjected to underfill (FC) can also be adopted.

In the chip packaging process, various kinds of substrates and various kinds of target silicon interposer may be required according to various packaging requirements. Embodiments of the present disclosure provide some cases of specific targeted silicon interposer and substrate combinations packaging operations. Therefore, the heterogeneous chip packaging method disclosed by the invention has high universality.

According to the packaging method of the heterogeneous chip, the large silicon interposer is cut into the small silicon interposer blocks, and warping and cracking of the silicon interposer in the thinning process are avoided. The silicon intermediary blocks with different specifications are combined according to the installation requirements of the heterogeneous chips, are correspondingly installed with the heterogeneous chips, and can be formed at one time, so that the overall area of the silicon intermediary layer and the distance between the chips are reduced, and the overall integration level of the package is greatly improved.

It will be understood that the above description of embodiments is not intended to be exhaustive of all possible scenarios, and the purpose of particular embodiments is to provide some reproducible reference methods for illustrating the principles of the present disclosure. However, the present disclosure is not limited thereto, and it is possible for those skilled in the art to make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements will also be considered as the protection scope of the present invention.

Claims

1. A heterogeneous chip packaging method is characterized by comprising the following steps:

forming a plurality of groups of conductive connection structures on the first surfaces of the plurality of silicon wafers respectively to obtain a plurality of silicon intermediate boards; wherein at least one of the silicon interposers is different from the other silicon interposers;

respectively cutting the silicon medium plates to obtain a plurality of silicon medium blocks;

selecting a plurality of target silicon interposers from the plurality of silicon interposers and fixing first surfaces of the plurality of target silicon interposers on the substrate; wherein the target silicon interposer blocks are all equal in thickness;

disposing the plurality of heterogeneous chip interconnects on the corresponding plurality of target silicon interposer blocks, respectively.

2. The method of packaging a split silicon interposer with a hetero-chip as claimed in claim 1, wherein the method of forming at least one of the silicon interposers comprises:

3. The method of packaging a split silicon interposer with a hetero-chip as claimed in claim 1, wherein the method of forming at least one of the silicon interposers comprises:

4. The method of packaging a split silicon interposer with a hetero-chip as claimed in claim 1, wherein the method of forming at least one of the silicon interposers comprises:

filling conductive materials in the multiple groups of blind holes;

5. The method of packaging a split silicon interposer with a hetero-chip as claimed in claim 1, wherein the method of forming at least one of the silicon interposers comprises:

filling conductive materials in the multiple groups of blind holes;

6. The method of packaging a split silicon interposer with a hetero-chip as claimed in claim 1, wherein the method of forming at least one of the silicon interposers comprises:

filling conductive materials in the multiple groups of blind holes;

arranging a rewiring layer on the first surface of the silicon wafer;

7. The method of packaging a split silicon interposer with a hetero-chip as claimed in claim 1, wherein the method of forming at least one of the silicon interposers comprises:

filling conductive materials in the multiple groups of blind holes;

arranging a rewiring layer on the first surface of the silicon wafer;

and thinning the second surface of the silicon wafer until the conductive connecting structure is exposed to form a through silicon via, thus obtaining the silicon interposer.

8. The method for packaging a split silicon interposer heterogeneous chip according to any one of claims 1 to 7, wherein the fixing the first surfaces of the plurality of target silicon interposers on the substrate further comprises:

prefabricating a plurality of conductive columns on the substrate, and plastically packaging the conductive columns on the substrate and the target silicon intermediate blocks; or the like, or, alternatively,

9. The method for packaging the split silicon interposer heterogeneous chip as claimed in any one of claims 1 to 7, wherein one surface of the substrate is provided with a plurality of grooves; said securing first surfaces of said plurality of target silicon interposer blocks on said substrate comprises:

10. The method for packaging the split silicon interposer heterogeneous chip according to any one of claims 1 to 7, wherein the substrate is provided with a plurality of through slots; the securing the first surfaces of the plurality of target silicon interposer blocks on the substrate further comprises:

fixing one surface of the substrate to a temporary carrier plate;