CN115799080A - Heterogeneous chip packaging method - Google Patents

Abstract

The embodiment of the disclosure provides a heterogeneous chip packaging method, which includes: providing a substrate, a plurality of silicon wafers and a plurality of heterogeneous chips; forming a plurality of groups of conductive connection structures on the plurality of silicon chips respectively to obtain a plurality of silicon intermediate boards; respectively cutting the silicon medium plates to obtain a plurality of target silicon medium blocks; fixing the target silicon intermediate blocks in corresponding grooves on the substrate; the plurality of heterogeneous chip interconnects are disposed on the corresponding plurality of target silicon interposer blocks, respectively. The large silicon interposer is cut into small silicon interposer blocks, and warping and cracking of the silicon interposer during thinning are avoided. The silicon medium blocks with different specifications are combined according to the installation requirements of the heterogeneous chips, are correspondingly installed with the heterogeneous chips and can be formed at one time, the whole area of the silicon medium layer and the distance between the chips are reduced, and the integration level of the whole package is greatly improved.

Description

Heterogeneous chip packaging method

Technical Field

The disclosure belongs to the technical field of semiconductor packaging, and particularly relates to a heterogeneous chip packaging method.

Background

In the 2.5D package technology, the silicon interposer is mainly an intermediate structure connected between the chip and the substrate for amplifying and transmitting signals of the chip to the substrate. At present, the thinner the chip package is, and a plurality of chips may be connected to the silicon interposer, so when the chip is mounted on the silicon interposer and the silicon interposer is thinned, the warpage and even the crack of the silicon interposer are easily caused. And the integration level of the existing silicon interposer and chip is yet to be further improved.

Disclosure of Invention

Embodiments of the present disclosure are directed to solving at least one of the technical problems in the prior art, and provide a heterogeneous chip packaging method.

The packaging method comprises the following steps:

providing a substrate, a plurality of silicon wafers and a plurality of heterogeneous chips; the front surface of the substrate is provided with a plurality of grooves;

forming a plurality of groups of conductive connection structures on the plurality of silicon chips respectively to obtain a plurality of silicon intermediate boards; wherein at least one of the silicon interposers is different from the other silicon interposers;

respectively cutting the silicon medium plates to obtain a plurality of target silicon medium blocks;

fixing the front surface of at least one target silicon intermediate block in the corresponding groove, and fixing the back surfaces of the rest at least one silicon intermediate block in the corresponding groove; wherein at least one of the target silicon interposer is different in thickness from other target silicon interposers;

disposing the plurality of heterogeneous chip interconnects on the corresponding plurality of target silicon interposer blocks, respectively.

Optionally, forming a plurality of groups of blind holes on the front surface of at least one silicon wafer;

filling conductive materials in the multiple groups of blind holes to form the conductive connection structure, so as to obtain the silicon interposer; alternatively, the first and second electrodes may be,

forming a plurality of groups of conductive connection structures on the plurality of silicon chips respectively to obtain a plurality of silicon intermediate boards, including:

forming a plurality of groups of blind holes on the front surface of at least one silicon wafer;

filling conductive materials in the plurality of groups of blind holes to form the conductive connection structure;

and thinning the back surface of the silicon wafer until the conductive connecting structure is exposed to form a silicon through hole, and obtaining the silicon intermediate plate.

Optionally, the forming a plurality of groups of conductive connection structures on the plurality of silicon wafers respectively to obtain a plurality of silicon interposer includes:

forming a plurality of groups of blind holes on the front surface of at least one silicon wafer;

filling conductive materials in the multiple groups of blind holes;

forming a rewiring layer on the front side of the silicon wafer to form the conductive connection structure, so as to obtain the silicon interposer; alternatively, the first and second electrodes may be,

forming a plurality of groups of conductive connection structures on the plurality of silicon chips respectively to obtain a plurality of silicon intermediate boards, including:

forming a plurality of groups of blind holes on the front surface of at least one silicon wafer;

filling conductive materials in the multiple groups of blind holes;

forming a rewiring layer on the front side of the silicon wafer to form the conductive connection structure;

and thinning the back surface of the silicon wafer until the conductive connecting structure is exposed to form a silicon through hole, and obtaining the silicon intermediate plate.

Optionally, the forming a plurality of groups of conductive connection structures on the plurality of silicon wafers respectively to obtain a plurality of silicon interposer includes:

forming a plurality of groups of blind holes on the front surface of at least one silicon wafer;

filling conductive materials in the multiple groups of blind holes;

forming a rewiring layer on the front side of the silicon wafer;

arranging solder balls on the redistribution layer to form the conductive connection structure to obtain the silicon interposer; alternatively, the first and second electrodes may be,

forming a plurality of groups of conductive connection structures on the plurality of silicon chips respectively to obtain a plurality of silicon intermediate boards, including:

forming a plurality of groups of blind holes on the front surface of at least one silicon wafer;

filling conductive materials in the multiple groups of blind holes;

forming a rewiring layer on the front side of the silicon wafer;

arranging solder balls on the rewiring layer to form the conductive connection structure;

and thinning the back of the silicon chip until the conductive connecting structure is exposed to form a through silicon via, thus obtaining the silicon interposer.

Preferably, the plurality of chips are fixed on a carrier plate for plastic package, and then the carrier plate is removed to obtain a chip recombinant.

Optionally, the thickness of at least one of the target silicon interposer blocks is lower than the height of the groove;

after the front surface of at least one of the target silicon interposer blocks is fixed in the corresponding groove and the back surface of the rest of at least one of the silicon interposer blocks is fixed in the corresponding groove, the method further comprises:

and forming a bonding structure at the position of the chip recombinant corresponding to the target silicon intermediate block with the thickness lower than the groove.

Optionally, the respectively disposing the chip interconnects on the corresponding target silicon interposer blocks includes:

and fixing the chip recombinants on the surfaces of the target silicon intermediate blocks, which are opposite to the substrate, through bonding structures, and finishing the interconnection arrangement of the chips on the target silicon intermediate blocks.

Optionally, the thickness of at least one target silicon interposer is greater than the height of the groove, the height of the blind hole of the target silicon interposer is greater than or equal to the height of the groove, and the front surface of the target silicon interposer is fixed to the corresponding groove;

after the front surface of at least one of the target silicon interposer blocks is fixed in the corresponding groove and the back surface of the rest of at least one of the silicon interposer blocks is fixed in the corresponding groove, the method further comprises:

and thinning the back surfaces of all the target silicon intermediate blocks with the thickness higher than that of the grooves until the thickness of all the target silicon intermediate blocks is equal to the height of the grooves, and exposing the blind holes of all the target silicon intermediate blocks.

Optionally, the back surfaces of all the target silicon intermediate blocks with the thickness higher than the groove are thinned until the thickness of all the target silicon intermediate blocks is equal to the height of the groove and the blind holes of all the target silicon intermediate blocks are exposed, and the method is implemented

The method also comprises the following steps:

and thinning the back surface of the substrate until all the target silicon intermediate blocks are exposed.

Optionally, after the substrate is thinned to expose all of the target silicon interposer, the method further includes:

and forming a rewiring layer on the back of the thinned substrate.

According to the heterogeneous chip packaging method, the large silicon interposer is cut into the small silicon interposer, and warping and cracking of the silicon interposer in the thinning process are avoided. The silicon medium blocks with different specifications are combined according to the installation requirements of the heterogeneous chips, are correspondingly installed with the heterogeneous chips and can be formed at one time, the whole area of the silicon medium layer and the distance between the chips are reduced, and the integration level of the whole package is greatly improved.

Drawings

FIG. 1 is a flowchart of a heterogeneous chip packaging method according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of a method for forming a silicon interposer according to another embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a method for forming a silicon interposer according to another embodiment of the present disclosure;

FIG. 4 is a schematic diagram illustrating a method for forming a silicon interposer according to another embodiment of the present disclosure;

fig. 5 is a schematic diagram of a chip interconnection setup method according to another embodiment of the disclosure;

FIG. 6 is a schematic diagram of a method for providing a chip interconnect in accordance with another embodiment of the present disclosure;

Detailed Description

In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.

As shown in fig. 1, a heterogeneous chip packaging method according to an embodiment of the present disclosure includes:

s11, providing a substrate, a plurality of silicon wafers and a plurality of heterogeneous chips; wherein, the front of base plate is provided with a plurality of recesses.

Specifically, an embodiment of the present disclosure provides a Substrate (Substrate) with a groove, which is manufactured in advance, and a manufacturing method thereof is as follows: a conventional planar substrate is taken, and a plurality of grooves are etched at each preset position on one flat surface. For ease of illustration, embodiments of the present disclosure assume the general case where the depths of the plurality of grooves are all equal. A plurality of heterogeneous chips are chips to be packaged in the embodiment of the present disclosure, "heterogeneous" means that the specification of each single chip is arbitrary.

The heterogeneous chip packaging method provided by the embodiment of the disclosure can be suitable for various substrates and various chips with different specifications, and can meet various packaging requirements in modern chip packaging technology.

Preferably, the heterogeneous chips are fixed on a carrier plate for plastic package, and then the carrier plate is removed to obtain a chip recombinant. Therefore, a plurality of preset heterogeneous chips can be packaged into a whole for bonding with a silicon interposer (Si interposer) and a substrate in a subsequent whole, steps are saved, operation is facilitated, and the integration level of the whole is improved.

S12, forming a plurality of groups of conductive connection structures on the plurality of silicon chips respectively, and obtaining a plurality of silicon intermediate boards; wherein at least one of the silicon interposers is different from the other silicon interposers.

Specifically, embodiments of the present disclosure provide a six-type silicon interposer with the formation step as a distinction. Each type of silicon interposer can be further subdivided into a plurality of different types according to the different depths, widths, densities, etc. of the formed holes, and usually only one type of silicon interposer is processed for each silicon wafer.

As shown in fig. 2, the first type of silicon interposer is formed by the following steps: and S21, forming a plurality of groups of blind holes on the front surface of the silicon wafer. S22, filling conductive materials in the multiple groups of blind holes to form the conductive connection structure, and obtaining the silicon interposer.

As shown in fig. 2, on the basis of the first type of silicon interposer, S23 is added, and the back surface of the silicon wafer is thinned until the conductive connection structure is exposed to form a through hole, so as to obtain the silicon interposer. Thus, a second type silicon interposer is formed.

As shown in fig. 3, the third type silicon interposer is formed by the following steps: and S31, forming a plurality of groups of blind holes on the front surface of the silicon wafer. And S32, filling conductive materials in the multiple groups of blind holes. And S33, arranging a ReDistribution Layer (RDL) on the front surface of the silicon wafer to form the conductive connection structure, so as to obtain the silicon interposer.

As shown in fig. 3, on the basis of the third type silicon interposer, adding S34, and thinning the back surface of the silicon wafer until the conductive connection structure is exposed to form a through hole, thereby obtaining the silicon interposer. A fourth type of silicon interposer is thus formed.

As shown in fig. 4, a fifth type silicon interposer is formed by: and S41, forming a plurality of groups of blind holes on the front surface of the silicon wafer. And S42, filling conductive materials in the multiple groups of blind holes. And S43, arranging a rewiring layer on the front surface of the silicon wafer. And S44, arranging solder balls (Bump) on the redistribution layer to form the conductive connection structure, so as to obtain the silicon interposer.

As shown in fig. 4, on the basis of the fifth type silicon interposer, adding S45, and thinning the back surface of the silicon wafer until the conductive connection structure is exposed to form a through hole, thereby obtaining the silicon interposer. Thus, a sixth type silicon interposer is formed.

Embodiments of the present disclosure provide a silicon interposer with a plurality of different conductive connection structures, which can meet various packaging requirements in combination with the aforementioned substrate and the heterogeneous chip.

And S13, respectively cutting the silicon medium plates to obtain a plurality of target silicon medium blocks.

Specifically, the silicon interposer obtained in the above steps can be cut into silicon interposer blocks with different specifications. That is, the thickness, the width, and the density of the conductive connection structure and the holes are different for each silicon interposer.

The embodiment of the disclosure cuts the large silicon interposer into small silicon interposer blocks, avoiding warpage and cracking of the silicon interposer during thinning. Different types of silicon intermediate blocks can be combined together at will according to the packaging requirements, and the integration level is improved.

S14, fixing the front surface of at least one target silicon intermediate block in the corresponding groove, and fixing the back surface of the rest at least one silicon intermediate block in the corresponding groove; wherein at least one of the target silicon interposer is different in thickness from the other target silicon interposers.

Specifically, the silicon interposer block to be used in the packaging process is determined according to the pin arrangement of the chip to be packaged and the position of the groove, so that the conductive connection structure on the silicon interposer block can be correspondingly connected with the pins of the chip, and the conduction is facilitated. The silicon interposer thus selected is the target silicon interposer. These target silicon interposer are fixed to corresponding locations or in corresponding slots on the substrate.

According to the embodiment of the disclosure, the silicon medium blocks with different specifications are combined and installed on the substrate at will, so that heterogeneous chips with different specifications can be installed on the corresponding silicon medium blocks as required, and the integral integration level is improved.

And S15, respectively arranging the heterogeneous chips on the corresponding target silicon intermediate blocks.

Specifically, before and after the step, a plurality of sets of parallel different implementation flows are required to be completed according to different types of substrates, different types of target silicon intermediate blocks and the shapes of the target silicon intermediate blocks placed in the grooves. In order to make the technical effects of the present disclosure and the technical solutions of the present disclosure clear and complete, some different implementation flows are illustrated below.

The first example is as follows:

as shown in fig. 5, a plurality of target silicon intermediate blocks with through holes are taken, and a substrate 52 with grooves etched in advance is taken; some of the target silicon interposer 51 has a height equal to the height of the grooves on the substrate 52, and the remaining target silicon interposer 55 has a height lower than the height of the grooves on the substrate 52.

First, the front surface of the target silicon interposer 51 and the back surface of the target silicon interposer 55 are fixed in the corresponding grooves of the substrate 52.

Then, a bonding structure 54 is disposed on the chip recombinant 53 at a position corresponding to the silicon interposer 51 with a height lower than the groove, and the height of the bonding structure 54 is just equal to the height difference between the target silicon interposer 51 and the groove.

Finally, the chip recombinants 53 are disposed on the plurality of target silicon interposer blocks by interconnecting the bonding structures 54.

Additionally, the side of the substrate away from the groove may be thinned subsequently until the target silicon interposer is exposed, and redistribution traces (RDL), ball mounting (Bumping), etc. may be performed on the thinned plane for further possible operations on the process, such as stacking of chips, etc.

Example two:

as shown in fig. 6, take a plurality of target silicon interposers 61 with through holes and a plurality of target silicon interposers 62 with blind holes, and a substrate 63 with grooves etched in advance.

Firstly, the opening direction of the blind hole of the target silicon intermediate block 61 is outwards fixed in the corresponding groove of the substrate 63, the thickness of the blind hole is equal to the height of the groove, the opening direction of the blind hole of the target silicon intermediate block 62 is inwards fixed in the corresponding groove of the substrate 63, the thickness of the blind hole is larger than the height of the groove, and the height of the blind hole exceeds the height of the groove.

The side of the target silicon interposer 62 facing away from the substrate 63 is then ground down to the same height as the substrate 63, at which point the blind vias in the target silicon interposer 62 are exposed and become through vias. And grinding and thinning the side of the substrate 63 not etched with the groove until all the target silicon intermediate blocks are exposed.

Finally, the chip recombinants described above are disposed on either side of the substrate 133 through the target silicon interposer interconnects.

Additionally, the substrate and the other side of the target silicon interposer where no chip is disposed may be subsequently re-routed, ball-mounted, etc. for further possible operations on the process, such as stacking of chips, etc.

It should be noted that the bonding structure described in the embodiments of the present disclosure generally includes a copper bump on the surface of its carrier (substrate, chip or silicon interposer), and a SiO2 layer or a SiCN layer (collectively referred to as a passivation layer) around the copper bump and at the same height as the copper bump. In addition, in the embodiment of the present disclosure, if a mode of combining a plurality of chips into a chip recombinant and then interconnecting and disposing the chip recombinant on a target silicon interposer is not used, a bonding mode of respectively flip-chip and then entirely underfill (FC) on a single chip may be adopted. While all "frontside" refer to the functional side, the "frontside" of the target silicon interposer, i.e., the side of the blind via opening and forming the conductive connection structure.

In the chip packaging process, various kinds of substrates and various kinds of target silicon interposer may be required according to various packaging requirements. Embodiments of the present disclosure provide packaging operations for some specific target silicon interposer and substrate combinations. Therefore, the heterogeneous chip packaging method disclosed by the invention has high universality.

According to the heterogeneous chip packaging method, the large silicon interposer is cut into the small silicon interposer, and warping and cracking of the silicon interposer in the thinning process are avoided. The silicon medium blocks with different specifications are combined according to the installation requirements of the heterogeneous chips, are correspondingly installed with the heterogeneous chips and can be formed at one time, the whole area of the silicon medium layer and the distance between the chips are reduced, and the integration level of the whole package is greatly improved.

It will be understood that the above description of embodiments is not intended to be exhaustive of all possible scenarios, and the purpose of particular embodiments is to provide some reproducible reference methods for illustrating the principles of the present disclosure. However, the present disclosure is not limited thereto, and it is possible for those skilled in the art to make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements will also be considered as the protection scope of the present invention.

Claims (10)

1. A heterogeneous chip packaging method is characterized by comprising the following steps:

providing a substrate, a plurality of silicon wafers and a plurality of heterogeneous chips; the front surface of the substrate is provided with a plurality of grooves;

forming a plurality of groups of conductive connection structures on the plurality of silicon chips respectively to obtain a plurality of silicon intermediate boards; wherein at least one of the silicon interposers is different from the other silicon interposers;

respectively cutting the silicon medium plates to obtain a plurality of target silicon medium blocks;

fixing the front surface of at least one target silicon intermediate block in the corresponding groove, and fixing the back surfaces of the rest at least one silicon intermediate block in the corresponding groove; wherein at least one of the target silicon interposer blocks has a different thickness than other target silicon interposer blocks;

the plurality of heterogeneous chip interconnects are disposed on the corresponding plurality of target silicon interposer blocks, respectively.

2. The method of claim 1, wherein the forming the plurality of sets of conductive connection structures on the plurality of silicon wafers respectively and obtaining a plurality of silicon interposers comprises:

forming a plurality of groups of blind holes on the front surface of at least one silicon wafer;

filling conductive materials in the multiple groups of blind holes to form the conductive connection structure, so as to obtain the silicon intermediate board; alternatively, the first and second liquid crystal display panels may be,

forming a plurality of groups of conductive connection structures on the plurality of silicon chips respectively to obtain a plurality of silicon intermediate boards, including:

forming a plurality of groups of blind holes on the front surface of at least one silicon wafer;

filling conductive materials in the plurality of groups of blind holes to form the conductive connection structure;

and thinning the back of the silicon chip until the conductive connecting structure is exposed to form a through silicon via, thus obtaining the silicon interposer.

3. The method of claim 1, wherein the forming the plurality of sets of conductive connection structures on the plurality of silicon wafers respectively and obtaining a plurality of silicon interposers comprises:

forming a plurality of groups of blind holes on the front surface of at least one silicon wafer;

filling conductive materials in the multiple groups of blind holes;

forming a rewiring layer on the front surface of the silicon wafer to form the conductive connection structure to obtain the silicon interposer; alternatively, the first and second electrodes may be,

forming a plurality of groups of conductive connection structures on the plurality of silicon chips respectively to obtain a plurality of silicon intermediate boards, including:

forming a plurality of groups of blind holes on the front surface of at least one silicon wafer;

filling conductive materials in the multiple groups of blind holes;

forming a rewiring layer on the front side of the silicon wafer to form the conductive connection structure;

and thinning the back of the silicon chip until the conductive connecting structure is exposed to form a through silicon via, thus obtaining the silicon interposer.

4. The method of claim 1, wherein the forming the plurality of sets of conductive connection structures on the plurality of silicon wafers respectively and obtaining a plurality of silicon interposers comprises:

forming a plurality of groups of blind holes on the front surface of at least one silicon wafer;

filling conductive materials in the multiple groups of blind holes;

forming a rewiring layer on the front side of the silicon wafer;

arranging solder balls on the redistribution layer to form the conductive connection structure to obtain the silicon interposer; alternatively, the first and second electrodes may be,

forming a plurality of groups of conductive connection structures on the plurality of silicon chips respectively to obtain a plurality of silicon intermediate boards, including:

forming a plurality of groups of blind holes on the front surface of at least one silicon wafer;

filling conductive materials in the multiple groups of blind holes;

forming a rewiring layer on the front side of the silicon wafer;

arranging solder balls on the rewiring layer to form the conductive connection structure;

and thinning the back surface of the silicon wafer until the conductive connecting structure is exposed to form a silicon through hole, and obtaining the silicon intermediate plate.

5. The chip packaging method according to any one of claims 1 to 4, wherein the plurality of chips are fixed on a carrier plate for plastic encapsulation, and then the carrier plate is removed to obtain a chip recombinant.

6. The chip packaging method according to claim 5, wherein the thickness of at least one of the target silicon interposer blocks is lower than the height of the recess;

after the front surface of at least one of the target silicon interposer blocks is fixed in the corresponding groove and the back surface of the rest of at least one of the silicon interposer blocks is fixed in the corresponding groove, the method further comprises:

and forming a bonding structure at the position of the chip recombinant corresponding to the target silicon intermediate block with the thickness lower than the groove.

7. The method of claim 6, wherein the respectively disposing the plurality of chip interconnects on the corresponding plurality of target silicon interposer blocks comprises:

and fixing the chip recombinant on the surface of the target silicon intermediate blocks, which faces away from the substrate, through a bonding structure, and finishing the interconnection arrangement of the chips on the target silicon intermediate blocks.

8. The chip packaging method according to any one of claims 1 to 4, wherein the thickness of at least one of the target silicon interposer is greater than the height of the recess, the blind via height of the target silicon interposer is greater than or equal to the height of the recess, and the front surface of the target silicon interposer is fixed in the corresponding recess;

after the front surface of at least one of the target silicon interposer blocks is fixed in the corresponding groove and the back surface of the rest of at least one of the silicon interposer blocks is fixed in the corresponding groove, the method further comprises:

and thinning the back surfaces of all the target silicon intermediate blocks with the thickness higher than that of the grooves until the thickness of all the target silicon intermediate blocks is equal to the height of the grooves, and exposing the blind holes of all the target silicon intermediate blocks.

9. The method of claim 8, wherein after thinning the back surface of the target silicon interposer with a thickness higher than the recess until the thickness of the target silicon interposer equals to the height of the recess and the blind vias of the target silicon interposer are exposed, the method further comprises:

and thinning the back surface of the substrate until all the target silicon intermediate blocks are exposed.

10. The method of claim 9, wherein after thinning the substrate backside to expose all of the target silicon interposer, the method further comprises:

and forming a rewiring layer on the back of the thinned substrate.

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