CN116203802B - Wafer photoetching parameter acquisition method and device and wafer photoetching implementation method and device - Google Patents
Wafer photoetching parameter acquisition method and device and wafer photoetching implementation method and device Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 79
- 238000001259 photo etching Methods 0.000 title claims abstract description 37
- 230000010363 phase shift Effects 0.000 claims abstract description 176
- 238000004088 simulation Methods 0.000 claims abstract description 80
- 230000008569 process Effects 0.000 claims abstract description 22
- 238000013041 optical simulation Methods 0.000 claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 claims abstract description 10
- 238000001459 lithography Methods 0.000 claims description 43
- 238000003860 storage Methods 0.000 claims description 16
- 238000007667 floating Methods 0.000 claims description 6
- 230000010287 polarization Effects 0.000 claims description 3
- 239000013078 crystal Substances 0.000 abstract description 2
- 235000012431 wafers Nutrition 0.000 description 121
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- 238000000206 photolithography Methods 0.000 description 3
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- 238000004891 communication Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/26—Phase shift masks [PSM]; PSM blanks; Preparation thereof
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/20—Exposure; Apparatus therefor
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70691—Handling of masks or workpieces
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
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Abstract
The embodiment of the application discloses a method and a device for acquiring wafer photoetching parameters and a method and a device for realizing wafer photoetching, wherein the method for acquiring the wafer photoetching parameters comprises the following steps of; acquiring a database of pre-established corresponding relation between parameters of the full-transparent phase shift mask and parameters of the wafer; acquiring target wafer parameters, and acquiring target full-transparent phase shift mask parameters according to the database and the target wafer parameters; performing optical simulation of the full-transparent phase shift mask according to the target full-transparent phase shift mask parameters to obtain simulation parameters and final target full-transparent phase shift mask parameters, wherein the simulation parameters enable simulation results to meet preset requirements; the simulation parameters are taken as wafer photoetching process parameters, and the final target full-transparent phase shift mask parameters are taken as parameters of the full-transparent phase shift mask required by wafer photoetching. The embodiment scheme reduces the period of the crystal circle by half compared with the mask period, improves the resolution, and correspondingly reduces the mask manufacturing cost due to the fact that the line width of the full-transparent phase shift mask is larger in size and the speed of the mask writing board is increased.
Description
Technical Field
The embodiments of the present disclosure relate to wafer lithography, and in particular, to a method and apparatus for obtaining wafer lithography parameters, and a method and apparatus for implementing wafer lithography.
Background
Continued optimization of photolithography is an inherent driving force for the ever shrinking nodes of integrated circuits. The photoetching machine is a hardware device for realizing photoetching, and how to use the resolution of the photoetching machine to the greatest extent is always pursued by scientific researchers.
Disclosure of Invention
The embodiment of the application provides a wafer photoetching parameter acquisition method and device and a wafer photoetching realization method and device, which can halve the period of a wafer compared with the period of a mask, improve the resolution, and correspondingly reduce the manufacturing cost of the mask because the line width of the full-transparent phase shift mask is larger, and the writing speed of the mask is increased.
The embodiment of the application provides a wafer photoetching parameter acquisition method, which can comprise the following steps:
acquiring a database of pre-established corresponding relation between parameters of the full-transparent phase shift mask and parameters of the wafer;
acquiring target wafer parameters, and acquiring target full-transparent phase shift mask parameters according to the database and the target wafer parameters;
performing optical simulation of the full-transparent phase shift mask according to the target full-transparent phase shift mask parameters to obtain simulation parameters and final target full-transparent phase shift mask parameters, wherein the simulation parameters enable simulation results to meet preset requirements;
and taking the simulation parameters as wafer photoetching process parameters, and taking the final target full-transparent phase shift mask parameters as parameters of full-transparent phase shift masks required by wafer photoetching.
In an exemplary embodiment of the present application, the full transparent phase shift mask parameters include full transparent phase shift mask linewidth and/or pitch size; the wafer parameters comprise wafer linewidth and/or spacing size;
the database for establishing the corresponding relation between the parameters of the full transparent phase shift mask and the parameters of the wafer can comprise:
determining the minimum limit of the wafer line width which can be achieved by different photoetching machines according to a Rayleigh formula, and determining the minimum line width of the full-transparent phase shift mask corresponding to the minimum limit of the wafer line width according to a preset multiple relation; determining a preset maximum line width of a wafer, and determining a maximum line width of a full-transparent phase shift mask corresponding to the maximum line width of the wafer according to the preset multiple relation; thereby determining the maximum linewidth of the full transparent phase shift mask; and/or the number of the groups of groups,
determining minimum limit of the wafer spacing size which can be achieved by different lithography machines according to a Rayleigh formula, and determining minimum spacing size of the full-transparent phase shift mask corresponding to the minimum limit of the wafer spacing size according to a preset multiple relation; determining a preset maximum pitch size of a wafer, and determining a maximum pitch size of a full-transparent phase shift mask corresponding to the maximum pitch size of the wafer according to the preset multiple relation; thereby determining the full transparent phase shift mask maximum pitch size.
In an exemplary embodiment of the present application, the preset multiple relationship may include:
the line width of the full transparent phase shift mask is a times of the line width of the wafer;
the pitch size of the full transparent phase shift mask is a times the pitch size of the wafer;
wherein a is a positive integer; when the wafer and the full transparent phase shift mask are one-to-one structure, a comprises 2.
In an exemplary embodiment of the present application, performing optical simulation of the full-transparent phase shift mask according to the target full-transparent phase shift mask parameter to obtain a simulation parameter and a final target full-transparent phase shift mask parameter that enable a simulation result to meet a preset requirement may include:
step 41, setting simulation parameters, and performing full-transparent phase shift mask optical simulation according to the target full-transparent phase shift mask parameters;
step 42, judging whether the simulation result meets the preset requirement, if so, entering step 44, and if not, entering step 43;
step 43, correcting the target full-transparent phase shift mask parameters according to the simulation result, obtaining corrected target full-transparent phase shift mask parameters, and adjusting the simulation parameters to obtain adjusted simulation parameters; taking the corrected target full transparent phase shift mask parameter as the target full transparent phase shift mask parameter, taking the adjusted simulation parameter as the simulation parameter to be set, and returning to the step 41;
and step 44, outputting the set simulation parameters, and taking the target full-transparent phase shift mask parameters as the final target full-transparent phase shift mask parameters.
In an exemplary embodiment of the present application, the preset requirements may include any one or more of the following:
the log slope of the space image normalized image is more than 1.5;
the linewidth of the wafer obtained after simulation is within a floating range of a preset target wafer linewidth; the method comprises the steps of,
the wafer pitch size obtained after simulation is within a floating range of a preset target wafer pitch size;
the target wafer parameters include the target wafer linewidth and the target wafer pitch size.
In an exemplary embodiment of the present application, the method may further include:
and updating the full-transparent phase shift mask parameters corresponding to the target wafer parameters in the database by adopting the final target full-transparent phase shift mask parameters.
In an exemplary embodiment of the present application, the simulation parameters may include any one or more of the following: light source shape, light source aperture and polarization;
the target full transparent phase shift mask parameters may further include: phase difference.
The embodiment of the application also provides a wafer lithography parameter obtaining device, which may include: the wafer lithography parameter acquisition method comprises a first processor and a first computer readable storage medium, wherein first instructions are stored in the first computer readable storage medium, and when the first instructions are executed by the first processor, the wafer lithography parameter acquisition method is realized.
The embodiment of the application also provides a wafer photoetching implementation method, which can comprise the following steps:
the simulation parameters and the final target full-transparent phase shift mask parameters obtained by the wafer photoetching parameter obtaining method are obtained;
manufacturing a full-transparent phase shift mask according to the final target full-transparent phase shift mask parameters;
and executing a wafer photoetching process by taking the acquired simulation parameters as wafer photoetching process parameters based on the manufactured full-transparent phase shift mask.
The embodiment of the application also provides a wafer lithography parameter obtaining device, which may include: the wafer lithography implementation method includes a second processor and a second computer readable storage medium having second instructions stored therein that when executed by the second processor implement the wafer lithography implementation method.
Compared with the related art, the embodiment of the application can comprise the following steps: acquiring a database of pre-established corresponding relation between parameters of the full-transparent phase shift mask and parameters of the wafer; acquiring target wafer parameters, and acquiring target full-transparent phase shift mask parameters according to the database and the target wafer parameters; performing optical simulation of the full-transparent phase shift mask according to the target full-transparent phase shift mask parameters to obtain simulation parameters and final target full-transparent phase shift mask parameters, wherein the simulation parameters enable simulation results to meet preset requirements; and taking the simulation parameters as wafer photoetching process parameters, and taking the final target full-transparent phase shift mask parameters as parameters of full-transparent phase shift masks required by wafer photoetching. According to the embodiment, the wafer period can be halved compared with the mask period, the resolution is improved, and the mask writing plate speed is increased due to the fact that the line width of the full-transparent phase shift mask is larger, so that the mask manufacturing cost is correspondingly reduced.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. Other advantages of the present application may be realized and attained by the structure particularly pointed out in the written description and drawings.
Drawings
The accompanying drawings are included to provide an understanding of the technical aspects of the present application, and are incorporated in and constitute a part of this specification, illustrate the technical aspects of the present application and together with the examples of the present application, and not constitute a limitation of the technical aspects of the present application.
FIG. 1 is a flowchart of a method for obtaining wafer lithography parameters according to an embodiment of the present application;
FIG. 2 is a schematic illustration of halving the wafer line cycle according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a full transparent phase shift mask structure according to an embodiment of the present application;
FIG. 4 is a flow chart of a method for performing optical simulation of a full-transparent phase shift mask according to the target full-transparent phase shift mask parameters in accordance with an embodiment of the present application;
FIG. 5 is a block diagram of a wafer lithography parameter acquiring apparatus according to an embodiment of the present application;
FIG. 6 is a flow chart of a wafer lithography implementation method according to an embodiment of the present application;
FIG. 7 is a block diagram of a wafer lithography apparatus according to an embodiment of the present application.
Detailed Description
The present application describes a number of embodiments, but the description is illustrative and not limiting and it will be apparent to those of ordinary skill in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are possible. Any feature or element of any embodiment may be used in combination with or in place of any other feature or element of any other embodiment unless specifically limited.
The present application includes and contemplates combinations of features and elements known to those of ordinary skill in the art. The embodiments, features and elements of the present disclosure may also be combined with any conventional features or elements to form a unique inventive arrangement as defined in the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive arrangements to form another unique inventive arrangement as defined in the claims. Thus, it should be understood that any of the features shown and/or discussed in this application may be implemented alone or in any suitable combination. Accordingly, the embodiments are not to be restricted except in light of the attached claims and their equivalents. Further, various modifications and changes may be made within the scope of the appended claims.
Furthermore, in describing representative embodiments, the specification may have presented the method and/or process as a particular sequence of steps. However, to the extent that the method or process does not rely on the particular order of steps set forth herein, the method or process should not be limited to the particular sequence of steps described. Other sequences of steps are possible as will be appreciated by those of ordinary skill in the art. Accordingly, the particular order of the steps set forth in the specification should not be construed as limitations on the claims. Furthermore, the claims directed to the method and/or process should not be limited to the performance of their steps in the order written, and one skilled in the art can readily appreciate that the sequences may be varied and still remain within the spirit and scope of the embodiments of the present application.
The embodiment of the application provides a wafer lithography parameter obtaining method, as shown in fig. 1, the method may include steps S101 to S104:
s101, acquiring a database of pre-established corresponding relation between parameters of a full-transparent phase shift mask and parameters of a wafer;
s102, acquiring target wafer parameters, and acquiring target full-transparent phase shift mask parameters according to the database and the target wafer parameters;
s103, performing optical simulation of the full-transparent phase shift mask according to the target full-transparent phase shift mask parameters to obtain simulation parameters and final target full-transparent phase shift mask parameters, wherein the simulation parameters enable simulation results to meet preset requirements;
s104, taking the simulation parameters as wafer photoetching process parameters, and taking the final target full-transparent phase shift mask parameters as parameters of full-transparent phase shift masks required by wafer photoetching.
In the exemplary embodiments of the present application, the known phase shift mask technique is a resolution enhancement technique, while the fully transparent phase shift mask [ similar to the chromeless phase shift mask, except that the regions of the fully transparent phase shift mask used for exposure are chrome-free (the regions are all quartz) and the other regions are chrome-free ] provides a stronger resolution enhancement than the existing binary mask and attenuated phase shift mask. The full transparent phase shift mask has no stop layer when the mask etches quartz, and the etching depth is easily influenced by the pattern density, so that the phase difference of the pattern dense region and the non-dense region is uneven, and the use of the full transparent phase shift mask has certain limitation. However, the full transparent phase shift mask with equidistant and periodic lines can halve the period of the final wafer lines, as shown in fig. 2, which is possible to be applied in a photolithography special process, and simultaneously, the full transparent mask size corresponding to the process of preparing the same wafer lines is increased, thereby reducing the mask manufacturing cost, and the full transparent mask etching process of the equal period lines is better controlled.
In an exemplary embodiment of the present application, a wafer lithography parameter acquisition method is proposed based on a full-transparent phase shift mask, and a database of correspondence between full-transparent phase shift mask parameters and wafer parameters is first established; and performing optical simulation of the full transparent phase shift mask based on the database to obtain proper wafer lithography parameters through simulation.
In an exemplary embodiment of the present application, the wafer lithography parameters may include: wafer lithography process parameters and parameters of the desired full transparent phase shift mask.
In exemplary embodiments of the present application, the full transparent phase shift mask parameters may include, but are not limited to: phase difference, line width and pitch dimensions of the fully transparent phase shift mask; wafer parameters may include, but are not limited to: wafer linewidth and pitch size.
In an exemplary embodiment of the present application, the database of the correspondence between the parameters of the full-transparent phase shift mask and the parameters of the wafer may refer to a database of the correspondence between the line width and the pitch size of the full-transparent phase shift mask and the line width and the pitch size of the wafer.
In an exemplary embodiment of the present application, establishing a database of correspondence between parameters of a full transparent phase shift mask and parameters of a wafer may include:
determining the minimum limit of the wafer line width which can be achieved by different photoetching machines according to a Rayleigh formula, and determining the minimum line width of the full-transparent phase shift mask corresponding to the minimum limit of the wafer line width according to a preset multiple relation; determining a preset maximum line width of a wafer, and determining a maximum line width of a full-transparent phase shift mask corresponding to the maximum line width of the wafer according to the preset multiple relation; thereby determining the maximum linewidth of the full transparent phase shift mask; and/or the number of the groups of groups,
determining minimum limit of the wafer spacing size which can be achieved by different lithography machines according to a Rayleigh formula, and determining minimum spacing size of the full-transparent phase shift mask corresponding to the minimum limit of the wafer spacing size according to a preset multiple relation; determining a preset maximum pitch size of a wafer, and determining a maximum pitch size of a full-transparent phase shift mask corresponding to the maximum pitch size of the wafer according to the preset multiple relation; thereby determining the full transparent phase shift mask maximum pitch size.
In an exemplary embodiment of the present application, the preset multiple relationship may include:
the line width of the full transparent phase shift mask is a times of the line width of the wafer;
the pitch size of the full transparent phase shift mask is a times the pitch size of the wafer;
wherein a is a positive integer; when the wafer and the full transparent phase shift mask are one-to-one structure, a comprises 2.
In the exemplary embodiments of the present application, the linewidth and pitch dimensions of the wafer and the fully transparent phase shift mask are all one-to-one structures. According to the space image frequency doubling characteristic of the full-transparent phase shift mask, a double relation between the line width and the space size of the full-transparent phase shift mask and the line width and the space size of a wafer can be established; the database is thus a wafer track period halving database, as shown in table 1.
TABLE 1
In the exemplary embodiment of the present application, the correspondence between different values of the line widths and the minimum values and the maximum values of the pitch sizes of the wafer and the full-transparent phase shift mask may be determined by first determining the minimum values and the maximum values of the line widths and the pitch sizes of the wafer and the full-transparent phase shift mask, and then determining the minimum values and the maximum values of the line widths and the pitch sizes of the full-transparent phase shift mask according to the above-mentioned two-fold relationship, so as to form a correspondence database satisfying the minimum line widths to the maximum line widths and the minimum pitch sizes to the certain range of the maximum pitch sizes. In the database which is initially established, the line width and the space size of each group of full transparent phase shift masks are in a double relation with the line width and the space size of a corresponding group of wafers.
In an exemplary embodiment of the present application, for example, the full transparent phase shift mask linewidth and pitch dimensions are 80nm and 80nm, and the wafer linewidth and pitch dimensions are 40nm and 40nm, respectively.
In an exemplary embodiment of the present application, a schematic diagram of a fully transparent phase shift mask structure is shown in fig. 3. Where pi and 0 represent the phase of the fully transparent phase shift mask.
In the exemplary embodiment of the application, since different lithography machines have different performances, the minimum limit of the wafer line width that can be achieved by the different lithography machines is also different, so that the minimum limit of the wafer line width that can be achieved by the different lithography machines can be determined through a rayleigh formula, and the minimum value of the line width of the full-transparent phase shift mask is obtained according to the double relationship.
In an exemplary embodiment of the present application, the performing optical simulation of the full-transparent phase shift mask according to the target full-transparent phase shift mask parameter to obtain a simulation parameter and a final target full-transparent phase shift mask parameter that enable a simulation result to meet a preset requirement, as shown in fig. 4, may include steps S201 to S204:
s201, setting simulation parameters, and performing optical simulation of the full-transparent phase shift mask according to the target full-transparent phase shift mask parameters;
s202, judging whether a simulation result meets the preset requirement, if so, entering a step S204, and if not, entering a step S203;
s203, correcting the target full-transparent phase shift mask parameters according to simulation results, obtaining corrected target full-transparent phase shift mask parameters, adjusting the simulation parameters, and obtaining adjusted simulation parameters; taking the corrected target full-transparent phase shift mask parameter as the target full-transparent phase shift mask parameter, taking the adjusted simulation parameter as the simulation parameter to be set, and returning to the step S201;
s204, outputting the set simulation parameters, and taking the target full-transparent phase shift mask parameters as the final target full-transparent phase shift mask parameters.
In exemplary embodiments of the present application, the preset requirements that the simulation needs to meet may be predetermined prior to performing the full transparent phase shift mask optical simulation, so that it may be determined when the simulation results are acceptable.
In an exemplary embodiment of the present application, the preset requirements may include any one or more of the following:
the log slope of the space image normalized image is more than 1.5;
the linewidth of the wafer obtained after simulation is within a floating range of a preset target wafer linewidth; the method comprises the steps of,
the wafer pitch size obtained after simulation is within a floating range of a preset target wafer pitch size;
the target wafer parameters include the target wafer linewidth and the target wafer pitch size.
In an exemplary embodiment of the present application, the above-described optical simulation of the full transparent phase shift mask may be performed in an iterative manner, i.e., steps S201 to S204 are performed in a loop until the simulation result meets the preset requirement.
In an exemplary embodiment of the present application, after each execution of the full-transparent phase shift mask optical simulation, the full-transparent phase shift mask parameters (such as the full-transparent phase shift mask line width and the full-transparent phase shift mask pitch size) may be corrected according to a preset correction algorithm and the obtained wafer parameters (such as the wafer line width and the wafer pitch size), and the next full-transparent phase shift mask optical simulation may be executed according to the corrected full-transparent phase shift mask parameters until the simulation result meets the preset requirement.
In the exemplary embodiment of the application, when the simulation result meets the preset requirement, the simulation success can be determined, so that the simulation parameters adopted by the last simulation and the parameters of the full transparent phase shift mask can be derived and used as parameters in actual wafer lithography production.
In exemplary embodiments of the present application, the simulation parameters may include, but are not limited to, any one or more of the following: light source shape, light source aperture and polarization;
the derived full transparent phase shift mask parameters may include: phase difference, line width and pitch size.
In an exemplary embodiment of the present application, the method may further include:
and updating the full-transparent phase shift mask parameters corresponding to the target wafer parameters in the database by adopting the final target full-transparent phase shift mask parameters.
In the exemplary embodiment of the present application, in order to improve the accuracy of the scheme, the database may be updated with the obtained final target full-transparent phase shift mask parameters (i.e., derived full-transparent phase shift mask parameters) after the simulation is completed, so that the database is continuously perfected, thereby improving the simulation efficiency and the simulation accuracy when the simulation is performed subsequently according to the database.
The embodiment of the present application further provides a wafer lithography parameter acquiring apparatus 1, as shown in fig. 5, may include: a first processor 11 and a first computer readable storage medium 12, wherein the first computer readable storage medium 12 stores first instructions, which when executed by the first processor 11, implement the wafer lithography parameter acquiring method.
In the exemplary embodiments of the present application, any embodiment of the foregoing wafer lithography parameter obtaining method is applicable to the embodiment of the apparatus, and will not be described herein in detail.
The embodiment of the application also provides a wafer lithography implementation method, as shown in fig. 6, the method may include steps S301 to S303:
s301, obtaining simulation parameters and final target full-transparent phase shift mask parameters obtained by the wafer photoetching parameter obtaining method;
s302, manufacturing a full-transparent phase shift mask according to the final target full-transparent phase shift mask parameters;
s303, executing a wafer photoetching process by taking the acquired simulation parameters as wafer photoetching process parameters based on the manufactured full-transparent phase shift mask.
In an exemplary embodiment of the present application, after the simulation parameters and the final target full-transparent phase shift mask parameters are obtained according to the foregoing full-transparent phase shift mask optical simulation, a corresponding full-transparent phase shift mask may be fabricated according to the final target full-transparent phase shift mask parameters (e.g., phase difference, line width, and pitch size), and a wafer photolithography process may be performed using the full-transparent phase shift mask and the derived simulation parameters.
In the exemplary embodiments of the present application, the wafer lithography process based on the optical simulation of the full-transparent phase-shift mask halves the wafer circumference, and improves the lithography efficiency and accuracy, improves the resolution, and reduces the manufacturing cost of the full-transparent phase-shift mask.
The embodiment of the present application further provides a wafer lithography parameter obtaining apparatus 2, as shown in fig. 7, may include: a second processor 21 and a second computer readable storage medium 22, said second computer readable storage medium 22 having stored therein second instructions which, when executed by said second processor 21, implement said wafer lithography implementation method.
In the exemplary embodiments of the present application, any of the foregoing embodiments of the wafer lithography implementation method are applicable to the device embodiment, and are not described herein in detail.
In exemplary embodiments of the present application, at least the following advantages are included:
1. the period of the crystal is halved compared with the period of the mask, and the resolution is improved.
2. The full transparent phase shift mask has larger line width, and the mask writing board has high speed and can reduce the mask manufacturing cost.
3. The contrast and aerial image normalized image log slope are significantly improved compared to Binary and AttPSM (attenuated phase shift mask).
4. The wafer photoetching process based on the full transparent phase shift mask optical simulation improves the photoetching efficiency and accuracy.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, functional modules/units in the apparatus, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. In a hardware implementation, the division between the functional modules/units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component may have multiple functions, or one function or step may be performed cooperatively by several physical components. Some or all of the components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media (or non-transitory media) and communication media (or transitory media). The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
Claims (9)
1. A method for obtaining wafer lithography parameters, the method comprising:
acquiring a database of pre-established corresponding relations between all-transparent phase shift mask parameters and wafer parameters, wherein the all-transparent phase shift mask parameters comprise all-transparent phase shift mask line width and/or space size; the wafer parameters comprise wafer linewidth and/or spacing size;
acquiring target wafer parameters, and acquiring target full-transparent phase shift mask parameters according to the database and the target wafer parameters;
performing optical simulation of the full-transparent phase shift mask according to the target full-transparent phase shift mask parameters to obtain simulation parameters and final target full-transparent phase shift mask parameters, wherein the simulation parameters enable simulation results to meet preset requirements;
taking the simulation parameters as wafer photoetching process parameters, and taking the final target full-transparent phase shift mask parameters as parameters of full-transparent phase shift masks required by wafer photoetching;
wherein the database is established by the following method: determining the minimum limit of the wafer line width which can be achieved by different photoetching machines according to a Rayleigh formula, and determining the minimum line width of the full-transparent phase shift mask corresponding to the minimum limit of the wafer line width according to a preset multiple relation; determining a preset maximum line width of a wafer, and determining a maximum line width of a full-transparent phase shift mask corresponding to the maximum line width of the wafer according to the preset multiple relation; thereby determining the maximum linewidth of the full transparent phase shift mask; and/or the number of the groups of groups,
determining minimum limit of the wafer spacing size which can be achieved by different lithography machines according to a Rayleigh formula, and determining minimum spacing size of the full-transparent phase shift mask corresponding to the minimum limit of the wafer spacing size according to a preset multiple relation; determining a preset maximum pitch size of a wafer, and determining a maximum pitch size of a full-transparent phase shift mask corresponding to the maximum pitch size of the wafer according to the preset multiple relation; thereby determining the full transparent phase shift mask maximum pitch size.
2. The method of claim 1, wherein the predetermined multiple relationship comprises:
the line width of the full transparent phase shift mask is a times of the line width of the wafer;
the pitch size of the full transparent phase shift mask is a times the pitch size of the wafer;
wherein a is a positive integer; when the wafer and the full transparent phase shift mask are one-to-one structure, a comprises 2.
3. The method according to claim 1, wherein performing optical simulation of the full-transparent phase-shift mask according to the target full-transparent phase-shift mask parameter to obtain a simulation parameter and a final target full-transparent phase-shift mask parameter that enable a simulation result to meet a preset requirement comprises:
step 41, setting simulation parameters, and performing full-transparent phase shift mask optical simulation according to the target full-transparent phase shift mask parameters;
step 42, judging whether the simulation result meets the preset requirement, if so, entering step 44, and if not, entering step 43;
step 43, correcting the target full-transparent phase shift mask parameters according to the simulation result, obtaining corrected target full-transparent phase shift mask parameters, and adjusting the simulation parameters to obtain adjusted simulation parameters; taking the corrected target full transparent phase shift mask parameter as the target full transparent phase shift mask parameter, taking the adjusted simulation parameter as the simulation parameter to be set, and returning to the step 41;
and step 44, outputting the set simulation parameters, and taking the target full-transparent phase shift mask parameters as the final target full-transparent phase shift mask parameters.
4. A method of obtaining a lithographic parameter of a wafer according to any one of claims 1 to 3, wherein the predetermined requirements include any one or more of:
the log slope of the space image normalized image is more than 1.5;
the linewidth of the wafer obtained after simulation is within a floating range of a preset target wafer linewidth; the method comprises the steps of,
the wafer pitch size obtained after simulation is within a floating range of a preset target wafer pitch size;
the target wafer parameters include the target wafer linewidth and the target wafer pitch size.
5. A method of wafer lithography parameter acquisition according to any one of claims 1-3, further comprising:
and updating the full-transparent phase shift mask parameters corresponding to the target wafer parameters in the database by adopting the final target full-transparent phase shift mask parameters.
6. A method of wafer lithography parameter acquisition according to any one of claims 1-3, wherein the simulation parameters include any one or more of: light source shape, light source aperture and polarization;
the target full transparent phase shift mask parameters include: phase difference.
7. A wafer lithography parameter acquisition apparatus, comprising: a first processor and a first computer readable storage medium having first instructions stored therein that when executed by the first processor, implement the wafer lithography parameter acquisition method according to any one of claims 1-6.
8. A method for wafer lithography, the method comprising:
obtaining simulation parameters and final target full transparent phase shift mask parameters obtained by the wafer lithography parameter obtaining method according to any one of claims 1-6;
manufacturing a full-transparent phase shift mask according to the final target full-transparent phase shift mask parameters;
and executing a wafer photoetching process by taking the acquired simulation parameters as wafer photoetching process parameters based on the manufactured full-transparent phase shift mask.
9. A wafer lithography parameter acquisition apparatus, comprising: a second processor and a second computer readable storage medium having stored therein second instructions that, when executed by the second processor, implement the wafer lithography implementation method of claim 8.
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