JP2003344985A - Layout pattern data correction system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a layout pattern data correction system for correcting the pattern distortion produced in a pattern forming process at a high speed with high accuracy. <P>SOLUTION: The layout pattern data correction system for correcting the layout patterns of circuits by using simulation has means (53, 54 and 55) for correcting the layout pattern data in case a difference in level produced by an OPC reaches a prescribed reference value or above, by redividing the edge of the object for correction by repeating the division until the above difference in level attains the reference value or less. <P>COPYRIGHT: (C)2004,JPO

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a layout pattern data correction apparatus for correcting pattern distortion generated in a pattern forming process such as lithography or etching used in semiconductor manufacturing. 2. Description of the Related Art At present, the design rule of a semiconductor device has reached a level of 0.13 μm, which is smaller than the wavelength of a light source of a stepper for transferring the same. For example, when using a KrF excimer laser, the wavelength of the light source is 0.248 μm. Therefore, since the resolution is extremely deteriorated, the resolution performance is improved by using a special technique such as a modified illumination technique. When such a special transfer technique is used,
While the resolution improves, the fidelity of the pattern deteriorates.
Also, in other processes such as an etching process, dimensional variations due to differences in pattern density occur with the miniaturization of patterns. In order to solve these problems, an optical proximity correction (OPC) that deforms a pattern of a design layout so that a desired pattern is obtained.
ct Correction) is commonly performed. This optical proximity effect correction (hereinafter abbreviated as OPC) includes (1) a model-based OPC that deforms a pattern based on a simulation result, and (2) a graphic feature of a design layout pattern (width of each pattern, adjacent Distance to the pattern to be
OPC rules for deforming the design layout pattern in advance in consideration of the distance from the corner portion, etc.), and a rule-based OPC for deforming the design layout pattern based on this rule, (3) a model-based OPC and a rule-based OPC 3 with hybrid OPC that combines
There are different ways. The present invention relates to the model-based OPC of (1) and (3). Next, a conventional model-based OPC will be described with reference to the accompanying drawings. FIG. 8 is a processing flowchart showing the processing of the conventional layout pattern data correction apparatus. FIG. 3 shows a layout pattern of a metal wiring formed on a wafer. First, in step S101, an edge to be corrected is extracted, and is divided into edges that are moved by correction. The edge is divided according to conditions such as the vertices of the figure, the distance from the vertices, and the perpendicular from the vertices of other figures. FIG. 9 shows a layout pattern after extraction and division. In the figure, the edge to be corrected is divided by the division points 114 to 129. Next, in step S103, a finished pattern is predicted by simulation. In the prediction of a finished pattern by simulation, if the entire pattern is simulated, generally, processing takes a long time. Therefore, a simulation point is provided for an edge to be corrected, and a simulation is performed only for that point. FIG. 10 shows an example of setting simulation points. In the figure, simulation points 100, 101, and 1 are located near the center of the edge divided by division point 116 and division point 117.
02, 103, 104, and 105 are set. continue,
By calculating the light intensity or the like at that point, the finish is predicted. Next, in step S105, the distortion amount of the finished pattern with respect to the patterns 10 and 11 which are the reference patterns and the design patterns shown in FIG. 3 is determined based on the finished prediction result obtained by the simulation in step S103. Measure. Subsequently, step S10
In step 7, the distortion amount measured in step S105 is compared with a preset reference value of the distortion amount. If the measured amount of distortion does not satisfy the preset reference value, the process proceeds to step S109, whereas if it does, the process ends. In step S109, the movement amount of the edge moved by the correction is calculated. The calculated edge movement amount is usually set to a value obtained by multiplying the distortion amount by a predetermined coefficient in the direction opposite to the direction in which the pattern distortion occurs so as to cancel the pattern distortion. Next, in step S111, the edge to be corrected is moved by the movement amount obtained in step S109, and the layout pattern is provisionally corrected. here,
The reason why the temporary correction is made is that the finished pattern does not match the reference pattern, even if it is usually moved only once in the direction opposite to the direction in which the pattern distortion occurs. Therefore, in order to improve the accuracy of the correction, step S1
In step 03, each process is sequentially executed from the prediction of the finished pattern by simulation. The correction processing of the layout pattern data is performed as described above.
If the measured distortion amount cannot satisfy the preset distortion amount criterion, these processes are repeated indefinitely. Therefore, the number of repetitions is set, and if the repetition exceeds a predetermined number, the process is terminated. FIG. 11 shows layout pattern data after correction. A mask is created based on the layout pattern data after the correction, and processes such as lithography and etching are performed. FIG. 12 shows a finished pattern of the metal wiring on the wafer after the process processing. In the same drawing, the finished pattern 72 is processed based on the layout pattern data 70 in FIG. 11, and the finished pattern 73 is a metal wiring processed based on the layout turn 71 in FIG. As shown in FIG. 12, among the finished patterns 72 and 73, in the finished pattern 73, metal wiring is formed along with the distorted parts 74 and 75 whose dimensional accuracy has deteriorated. The distorted portions 74 and 75 are caused by the difference in the amount of movement between the correction target edges, that is, the step d in FIG. As described above, despite the large difference in the amount of distortion between the correction target edges, the correction target edges are not divided between the correction target edges, so that there is no simulation point, and dimensional accuracy cannot be ensured. On the other hand, as shown in FIG. 13, when the edge to be corrected is finely divided, the edge to be corrected is finely divided even in the layout pattern 70 in which dimensional accuracy can be secured without finely dividing the edge. Will be. Therefore, simulation points increase,
Processing time increases. As described above, in the conventional model OPC, when performing correction with high accuracy, it is necessary to divide the edge to be corrected finely. When the number increases, the number of simulation points also increases, so that there is a problem that the processing time increases. On the other hand, if the processing time is to be reduced, it is necessary to set the division of the edge to be corrected roughly and to reduce the number of simulation points, so that there is a problem that high-precision correction cannot be performed. That is, with the conventional model OPC, high-precision and high-speed processing was impossible. SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide a layout pattern data correction apparatus for correcting pattern distortion generated in a pattern forming process in semiconductor manufacturing with high accuracy and high speed. According to a first aspect of the present invention, there is provided a layout pattern data correction apparatus for correcting a circuit layout pattern using simulation, wherein an edge to be corrected is extracted. Then, a correction target edge extraction / division unit that divides the image into units of edges to be moved by correction, a simulation prediction unit that predicts a finished pattern by simulation, and a distortion amount of the finished pattern with respect to a predetermined reference pattern is measured. Prediction result determination means for comparing a set reference value of the distortion amount, and when the distortion amount does not satisfy the reference value,
A layout pattern temporary correction unit that calculates a moving amount of the correction target edge and temporarily corrects the layout pattern by moving the correction target edge based on the calculation result; and when the distortion amount satisfies the distortion amount reference value. A step measurement / judgment means for measuring a step which is a difference in the amount of movement between adjacent correction target edges, and comparing the result with a preset reference value of the step; and wherein the step is a reference value of the step. In the above case, a correction target edge re-dividing means for re-dividing the correction target edge is provided. Embodiments of the present invention will be described below in detail with reference to the accompanying drawings. Embodiment 1 FIG. 1 is a block diagram showing the configuration of the layout pattern data correction device. A layout pattern data correction apparatus according to the present invention includes a layout pattern data holding unit 1 for holding layout pattern data, a correction condition holding unit 2 for holding a file in which conditions for correction are described, and an edge for correction. , A correction target edge extracting / dividing means 3 for extracting the image data for each edge to be moved by correction, and a layout pattern correction repeating means 4 for performing correction by simulation
And a corrected layout pattern data holding unit 5. The conditions for performing the correction stored in the correction condition storage unit 2 include, for example, the conditions for extracting and dividing the edge to be corrected, the optical conditions, the number of simulations, the reference value for the amount of distortion, the reference value for the level difference, and the reference value for the edge to be corrected. , Etc. Further, the layout pattern correction repetition means 4 includes a simulation prediction means 50, a prediction result determination means 51, a layout pattern temporary correction means 52,
It comprises a step measuring unit 53, a step determining unit 54, and a correction target edge re-dividing unit 55. The simulation prediction means 50 predicts the finished pattern by simulation. The prediction result determination unit 51 predicts the amount of pattern distortion based on the simulation result output from the simulation prediction unit 50, and determines the amount of movement of the correction target edge. The layout pattern temporary correction unit 52 includes a prediction result determination unit 5
The correction target edge is moved by the movement amount of the edge obtained in step 1 to temporarily correct the layout pattern. The level difference measuring unit 53 predicts a difference between the movement amounts of adjacent correction target edges. The step determining unit 54 determines whether it is necessary to further divide the correction target edge based on the step measured by the step measuring unit 53. The correction target edge subdivision unit 55 subdivides the correction target edge based on the determination result output from the step determination unit 54. Next, the operation of the layout pattern data correction apparatus of the present invention will be described in detail. FIG. 2 is a flowchart showing the processing operation of the layout pattern data correction device of the present invention. FIG. 3 shows a layout pattern of a metal wiring formed on a wafer. First, in step S1, the edge to be corrected is extracted by the correction target edge extracting / dividing means 3 and is divided into the moving edges by the correction. In the next step S3, the simulation prediction means 50 predicts a finished pattern by simulation. Subsequently, in step S5, the distortion amount of the finished pattern with respect to the reference patterns which are the design patterns 10 and 11 shown in FIG. 3 is measured by the prediction result determining means 51 based on the finished prediction result obtained by the simulation in step S3. Then, in step S7, the distortion amount measured in step S5 is compared with a preset reference value of the distortion amount. If the distortion amount does not satisfy the reference value, the process proceeds to step S9, and if so, the process proceeds to step S13. In step S9, the amount of movement of the edge to be corrected which is moved by the correction is calculated. Then, step S
In step 11, the layout pattern temporary correction unit 52 moves the correction target edge based on the movement amount calculated in step S9, and temporarily corrects the layout pattern.
Thereafter, the process returns to step S3. In step S13, the step measuring means 53 measures a step which is a difference in the amount of movement between adjacent edges to be corrected. Here, FIG. 4 shows a layout pattern corrected so that the distortion amount satisfies a preset reference value. As shown in the drawing, steps d1 and d2 occur in the patterns 10 and 11. At each of the division points 23, 25, 26, and 28 in the pattern 11, the step d2 is large. Next, in step S15, the step determining means 54 determines whether further division of the edge to be corrected is necessary based on the steps d1 and d2 measured in step S13. That is, step S13
The steps d1 and d2 measured in the step are compared with a preset reference value of the step. If the measured steps d1 and d2 are equal to or greater than the reference value, the process proceeds to step S17. Ends the processing. In step S17, the correction target edge is re-divided by the correction target edge re-dividing means 55, and the process returns to step S3 to repeat a series of processes. Here, FIG. 5 shows a layout pattern after the subdivision of the correction target edge. As shown in the figure, in the pattern 10 in which the step d1 is not larger than the reference value of the step, the correction target edge is not subdivided, but in the pattern 11 in which the step d2 is larger than the reference value of the step, it is subdivided. Division point 3
0, 31, 32, 33, 34, 35, 36, and 37 are division points 22, 2 of the step d2 in the pattern 11, respectively.
This is a division point by subdivision, which is divided from 3, 24, 25, 26, 27, 28, 29 by a predetermined length. Subdivision is
It may be divided into a plurality of places with different lengths, or may be divided according to the size of the step. In addition, in the correction repetition processing, the division may be performed while changing the re-division length. If the magnitudes of the steps d1 and d2 measured in step S13 do not become smaller than the reference value in step S15, the process is repeated indefinitely. The process may be interrupted. FIG. 6 shows the result of correcting the layout pattern by performing Optical Proximity Effect Correction (OPC) by the above-described method. Note that the steps formed in the patterns 10 and 11 are d3 and d4, respectively. As shown in FIG. 6, as compared with the case shown in FIG.
4 is smaller than the step d2. On the other hand, pattern 1
At 0, there is no change in the steps d1 and d3. A mask is formed based on the layout pattern corrected in this manner, and a process such as lithography and etching is performed. FIG. 7 shows a finished pattern of the metal wiring formed on the wafer after the processing. In the figure, the finished pattern 40 is a metal wiring that has been processed based on the layout pattern data 10 in FIG. 6, and the finished pattern 41 is a metal wiring that has been processed based on the layout turn 11 in FIG. As shown in FIG. 7, when the finished pattern 41 of the metal wiring subjected to the OPC by the method of the present invention is compared with the finished pattern 73 shown in FIG. 11 formed by performing the conventional OPC, the pattern 41 shown in FIG. Now, the pattern 73 shown in FIG.
The distortion parts 74 and 75 whose dimensional accuracy has deteriorated in FIG. According to the flow described above, the layout pattern data correction apparatus of the present invention corrects layout pattern data. According to the layout pattern data correcting apparatus of the present invention, when the distortion amount of a finished pattern with respect to a predetermined reference pattern satisfies the reference value of the distortion amount, the movement amount between adjacent correction target edges is adjusted. A step measuring / judging means for measuring a step which is a difference between the step and a preset step reference value, and subdividing an edge to be corrected when the step is equal to or more than the step reference value. And a correction target edge re-dividing unit for performing the following. With such a configuration, when the step generated by the OPC is equal to or larger than the preset reference value of the step, the edge to be corrected is re-divided so that the step becomes smaller than the preset reference value. Then, by performing the correction, it is possible to specify a place where the dimensional accuracy is deteriorated and to make the division fine. Therefore, the number of places where the simulation is performed can be reduced, and the OPC can be performed with high accuracy and high speed. Further, it is possible to repeat the subdivision of the edge to be corrected until the level difference becomes less than the set reference value, thereby increasing the number of edge divisions at places where the dimensional accuracy is not high, and performing OPC with high accuracy. it can.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing a layout pattern data correction device of the present invention. FIG. 2 is a flowchart showing a process of the layout pattern data correction device of the present invention. FIG. 3 is a diagram showing metal wiring layout pattern data at the time of design. FIG. 4 is a diagram showing layout pattern data before dividing an edge to be corrected; FIG. 5 is a diagram showing layout pattern data after a correction target edge is subdivided. FIG. 6 is a diagram showing layout pattern data after correction. FIG. 7 is a diagram showing a finished layout pattern formed on a wafer. FIG. 8 is a flowchart showing a process performed by a conventional layout pattern data correction device. FIG. 9 is a diagram showing layout pattern data after an edge to be corrected is divided by a conventional layout pattern data correction device. FIG. 10 is a diagram showing an example of setting simulation points. FIG. 11 is a diagram showing layout pattern data after correction by a conventional layout pattern data correction device. 12 is a diagram showing a finished pattern of a metal wiring formed on a wafer using the layout pattern data shown in FIG. FIG. 13 is a diagram showing layout pattern data after a correction target edge is further finely divided by a conventional layout pattern data correction device. [Description of Signs] 1 layout pattern data storage unit, 2 auxiliary condition storage unit, 3 auxiliary object edge extraction / division means, 4
Layout pattern correction repeating means, 5 layout pattern data holding unit after correction, 10, 11, 70, 7
1 layout pattern, 14-37, 80-95
Division point, 50 simulation prediction means, 51
Prediction result determination means, 52 layout pattern temporary correction means, 53 step difference measurement means, 54 step difference determination means,
55 auxiliary object edge subdivision means, 74, 75 distorted part, 100-105 simulation points

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H01L 21/82 H01L 21/30 502P

Claims (1)

Claims 1. A layout pattern data correction apparatus for correcting a circuit layout pattern using a simulation, wherein an edge to be corrected is extracted and divided into units of edges to be moved by the correction. Correction target edge extraction / division means, simulation prediction means for predicting a finished pattern by simulation, measuring the distortion amount of the finished pattern with respect to a predetermined reference pattern, and comparing the measurement result with a preset reference value of the distortion amount A prediction result determining unit that calculates a movement amount of a correction target edge when the distortion amount does not satisfy the reference value, and temporarily corrects a layout pattern by moving the correction target edge based on the calculation result. Provisional pattern correction means, wherein the distortion amount satisfies a reference value of the distortion amount A step measurement / judgment means for measuring a step which is a difference in the amount of movement between adjacent correction target edges, and comparing the result with a preset reference value of the step; and the step is a reference value of the step. A layout pattern data correction apparatus, comprising: a correction target edge subdivision unit configured to redivide a correction target edge in the above case.