CN116192138A - Partial interleaving high-speed successive approximation-pipelined analog-to-digital converter - Google Patents
Partial interleaving high-speed successive approximation-pipelined analog-to-digital converter Download PDFInfo
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- CN116192138A CN116192138A CN202310079029.2A CN202310079029A CN116192138A CN 116192138 A CN116192138 A CN 116192138A CN 202310079029 A CN202310079029 A CN 202310079029A CN 116192138 A CN116192138 A CN 116192138A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/1205—Multiplexed conversion systems
- H03M1/121—Interleaved, i.e. using multiple converters or converter parts for one channel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
- H03M1/1245—Details of sampling arrangements or methods
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention relates to a partially-interleaved high-speed successive approximation-pipeline analog-to-digital converter, which comprises a plurality of intermediate stage pipeline modules, a final stage analog-to-digital converter and a redundant bit digital coding circuit, wherein the intermediate stage pipeline modules are sequentially connected in series and are used for collecting analog differential input signals and outputting quantized digital codes and amplified residual signals; the input end of the redundant bit digital coding circuit is respectively connected with each sub-stage analog-to-digital converter and each final stage analog-to-digital converter and is used for receiving the digital codes and converting the digital codes into binary digital codes corresponding to the analog differential input signals. The invention solves the waiting time problem of amplifying and sampling through multiplexing the residual amplifier, and greatly improves the working efficiency while saving the hardware cost and the circuit power consumption.
Description
Technical Field
The invention belongs to the field of analog-to-digital conversion, and particularly relates to a partially-interleaved high-speed successive approximation-pipelined analog-to-digital converter.
Background
Thanks to the continuous reduction of the process size of the current integrated circuits, the speed of digital circuits is faster and faster nowadays, and the successive approximation (Successive Approximation Register, SAR) analog-to-digital converter in the analog-to-digital converter (Analog To Digital Converter, ADC) has no large number of analog modules, so that the advanced process adaptation is well performed, and the working speed is also significantly improved. However, in some high-precision application scenarios, the successive approximation analog-to-digital converter does not perform as well as a pipelined analog-to-digital converter because there is no analog amplification unit to reduce the noise level. Therefore, for high-speed and high-precision application scenarios, successive approximation-pipeline analog-to-digital converter circuits have been developed.
The successive approximation-pipelined analog-to-digital converter circuit is a hybrid analog-to-digital converter combining a pipelined analog-to-digital converter and a successive approximation analog-to-digital converter, and the traditional structure of the successive approximation-pipelined analog-to-digital converter circuit is composed of a sample hold circuit, an intermediate sub-pipelined stage, a rear successive approximation analog-to-digital converter and a redundant bit digital coding circuit (Digital Error Correction Block), wherein each stage of intermediate sub-pipelined stage is composed of a successive approximation analog-to-digital converter and an inter-stage residual error amplifier. However, the existing successive approximation-pipelined analog-to-digital converter has large hardware overhead and large overall power consumption, and the working speed of the existing successive approximation-pipelined analog-to-digital converter needs to be improved due to the conflict of time waiting caused by sequential execution of intermediate-stage amplification and sampling of the sub-analog-to-digital converter.
Disclosure of Invention
The invention provides a partially-interleaved high-speed successive approximation-pipeline analog-to-digital converter, which comprises a plurality of intermediate stage pipeline modules, a final stage analog-to-digital converter and a redundant bit digital coding circuit, wherein,
the intermediate stage pipeline modules are sequentially connected in series, are used for collecting analog differential input signals, quantizing the analog differential input signals, generating residual difference signals and quantized digital codes, amplifying the residual difference signals, and outputting the quantized digital codes and amplified residual difference signals, wherein each intermediate stage pipeline module comprises a first sub-stage analog-to-digital converter, a second sub-stage analog-to-digital converter, a first control switch, a second control switch, a third control switch, a fourth control switch and a residual difference amplifier, the first control switch is connected between the first sub-stage analog-to-digital converter and the residual difference amplifier, the second control switch is connected between the first sub-stage analog-to-digital converter and the redundant digital coding circuit, the third control switch is connected between the second sub-stage analog-to-digital converter and the residual digital coding circuit, and the fourth control switch is connected between the second sub-stage analog-to-digital converter and the redundant digital coding circuit; the output end of the residual difference amplifier in the former intermediate stage pipeline module is respectively connected with the input end of the first sub-stage analog-to-digital converter and the input end of the second sub-stage analog-to-digital converter in the latter intermediate stage pipeline module;
the input end of the final-stage analog-to-digital converter is connected with the output end of the last residual error amplifier, and the final-stage analog-to-digital converter is used for receiving the amplified residual error signal, quantizing the amplified residual error signal and outputting quantized digital codes;
the input end of the redundant bit digital coding circuit is respectively connected with the output end of each first sub-stage analog-to-digital converter, the output end of each second sub-stage analog-to-digital converter and the output end of the final stage analog-to-digital converter, and is used for receiving quantized digital codes from each intermediate stage pipeline module and the final stage analog-to-digital converter, and outputting all the received quantized digital codes after coding conversion.
In one embodiment of the present invention, the apparatus further includes a front-end sample-and-hold circuit, wherein an output end of the front-end sample-and-hold circuit is connected to an input end of the first sub-stage analog-to-digital converter and an input end of the second sub-stage analog-to-digital converter in the first intermediate stage pipeline module, respectively, and is configured to collect an analog differential input signal, and output the analog differential input signal as a signal source of the plurality of intermediate stage pipeline modules.
In one embodiment of the invention, the first sub-stage analog-to-digital converter, the second sub-stage analog-to-digital converter and the final stage analog-to-digital converter are identical in structure.
In one embodiment of the invention, the first sub-stage analog-to-digital converter, the second sub-stage analog-to-digital converter and the final stage analog-to-digital converter are all successive approximation type analog-to-digital converters.
In one embodiment of the present invention, the front-end sample-and-hold circuit is a bootstrap switch-type sample-and-hold circuit.
In one embodiment of the invention, in each intermediate stage pipeline module,
when the quantization of the first sub-level analog-to-digital converter is completed, the first control switch and the second control switch are controlled to be turned on according to a preset time sequence, and the third control switch and the fourth control switch are controlled to be turned off;
when the first sub-level analog-to-digital converter finishes transmitting the generated residual signal to the residual amplifier and transmitting the generated binary digital code to the redundant bit digital coding circuit, the first control switch and the second control switch are controlled to be closed according to the preset time sequence, and the third control switch and the fourth control switch are controlled to be opened.
Compared with the prior art, the invention has the beneficial effects that:
1. the partial interleaving high-speed successive approximation-pipeline analog-to-digital converter provided by the invention realizes parallel processing in the time domain by multiplexing the same residual difference amplifier and controlling the first sub-stage analog-to-digital converter and the second sub-stage analog-to-digital converter to alternately sample and quantize the voltage signal in the middle stage pipeline module, and solves the problem of waiting time between middle stage amplification and sampling of the sub-analog-to-digital converter in the whole successive approximation-pipeline analog-to-digital converter, so that more time can be allocated for an interstage amplification stage and a sampling stage in the same conversion period, the double-channel time domain interleaving work is realized, and the working efficiency is greatly improved.
2. Compared with the traditional successive approximation analog-digital converter with a double-channel structure, the partial interleaving high-speed successive approximation-pipeline analog-digital converter provided by the invention has the advantages that the first sub-stage analog-digital converter and the second sub-stage analog-digital converter multiplex the same residual amplifier and the front-end sample hold circuit, so that the whole area and the power consumption of the circuit are effectively reduced, the hardware cost brought by using other high-speed technical schemes such as one-step multi-bit and the like is saved, the error of the time domain interleaving caused by the influence of non-ideal factors such as clock deviation and mismatch among channels is greatly reduced, and meanwhile, the same quantization bit number of each intermediate stage pipeline module is realized by using the same intermediate stage pipeline module, the complexity of circuit design is reduced, and the replicability of the circuit module is improved.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a partially interleaved high-speed successive approximation-pipelined analog-to-digital converter according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of another partially interleaved high-speed successive approximation-pipelined analog-to-digital converter according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an operation timing sequence of an intermediate stage pipeline module according to an embodiment of the present invention;
fig. 4 is a diagram showing the comparison of the operation timing sequences of a conventional single-channel successive approximation-pipelined analog-to-digital converter and a partially-interleaved high-speed successive approximation-pipelined analog-to-digital converter according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
In the description of the present invention, the terms "first," "second," and the like are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Example 1
Referring to fig. 1, fig. 1 is a schematic structural diagram of a partially-interleaved high-speed successive approximation-pipeline analog-to-digital converter according to an embodiment of the present invention, where the successive approximation-pipeline analog-to-digital converter is configured to convert an analog differential input signal into analog digital information, and the analog differential input signal is a pair of fully-differential input signals with equal magnitudes and opposite phases, and is used for characterizing an analog voltage signal.
The successive approximation-pipelined analog-to-digital converter includes a plurality of intermediate stage pipeline modules 20, a final stage analog-to-digital converter 30, and a redundant bit digital encoding circuit 40. Specifically, the plurality of intermediate stage pipeline modules 20 are sequentially connected in series, and the plurality of intermediate stage pipeline modules 20 are configured to collect an analog differential input signal, quantize the analog differential input signal, generate a residual signal and a quantized digital code, amplify the residual signal, and output the quantized digital code and the amplified residual signal. Further, each intermediate stage pipeline module 20 includes a first Sub-stage Analog-To-Digital Converter (Sub-ADC) 200, a second Sub-stage Analog-To-digital converter 201, a first control switch, a second control switch, a third control switch, a fourth control switch, and a residual amplifier (Residual Amplifier, RA) 202. Specifically, the first control switch is connected between the first sub-stage analog-to-digital converter 200 and the residual amplifier 202, the second control switch is connected between the first sub-stage analog-to-digital converter 200 and the redundant digital encoding circuit 40, when the first control switch and the second control switch are turned on, the first sub-stage analog-to-digital converter 200 samples and quantizes, specifically, the first sub-stage analog-to-digital converter 200 collects an analog differential input signal, quantizes the analog differential input signal after the sampling is completed, then the first sub-stage analog-to-digital converter 200 generates a binary number after the quantization and a residual signal, the first sub-stage analog-to-digital converter 200 outputs the binary number after the quantization to the redundant digital encoding circuit 40, and outputs the generated residual signal to the residual amplifier 202, and the first sub-stage analog-to-digital converter 200 completes the quantization. The residual amplifier 202 then amplifies, specifically, the residual amplifier 202 amplifies the received residual signal, and outputs the amplified residual signal to the pipeline module 20 of the subsequent intermediate stage, and the amplification process of the residual amplifier 202 is completed. The second sub-stage analog-to-digital converter 201 and the first sub-stage analog-to-digital converter 200 have the same circuit connection structure and the same function, that is, the third control switch is connected between the second sub-stage analog-to-digital converter 201 and the residual amplifier 202, and the fourth control switch is connected between the second sub-stage analog-to-digital converter 201 and the redundant bit digital coding circuit 40.
The output of the residual amplifier 202 in the previous intermediate stage pipeline module 20 is connected to the input of the first sub-stage analog-to-digital converter 200 and the input of the second sub-stage analog-to-digital converter 201 in the subsequent intermediate stage pipeline module 20, respectively, and the output of the residual amplifier 202 in the last intermediate stage pipeline module 20 is connected to the final stage analog-to-digital converter 30. The intermediate stage pipeline modules 20 sequentially perform the quantization and amplification processes according to the connection sequence, the next intermediate stage pipeline module 20 receives the residual signal output by the previous intermediate stage pipeline module 20, quantizes and amplifies the received residual signal, each intermediate stage pipeline module 20 outputs the binary digital code quantized by the module to the redundancy digital coding circuit 40, and the last residual amplifier 202 outputs the amplified residual signal to the final analog-to-digital converter 30.
Further, the first sub-stage analog-to-digital converter 200, the second sub-stage analog-to-digital converter 201 and the final stage analog-to-digital converter 30 have the same structure, and all the existing analog-to-digital converters are adopted.
Further, the first sub-stage analog-to-digital converter 200, the second sub-stage analog-to-digital converter 201 and the final stage analog-to-digital converter 30 are all successive approximation type analog-to-digital converters, and the residual amplifier 202 adopts an existing circuit structure, and in this embodiment, the residual amplifier 202 is a ring amplifier.
In each intermediate stage pipeline module 20, the first sub-stage analog-to-digital converter 200, the second sub-stage analog-to-digital converter 201 and the residual amplifier 202 complete the acquisition-quantization-amplification process in parallel by alternately controlling the on and off of the first control switch to the fourth control switch in time sequence, so that the working mode of the two-channel time domain interleaving is realized, the working efficiency is greatly improved, and the working mode of the two-channel time domain interleaving of the invention is described below.
In each intermediate stage pipeline module 20, the first sub-stage analog-to-digital converter 200 and the second sub-stage analog-to-digital converter 201 alternately sample the analog differential input signal and alternately implement quantization after sampling. Specifically, in the first intermediate stage pipeline module 20, the first sub-stage analog-to-digital converter 200 collects analog differential input signals of a first period, performs quantization, generates binary digital codes after the quantization is completed, and controls the first control switch and the second control switch to be simultaneously turned on according to a preset time sequence, and the third control switch and the fourth control switch to be turned off. The first sub-stage analog-to-digital converter 200 transmits the generated residual signal to the residual amplifier 202, and the first sub-stage analog-to-digital converter 200 transmits the generated binary digital code to the redundant bit digital encoding circuit 40. At this time, the sampling of the second sub-stage analog-to-digital converter 201 is also completed, the second sub-stage analog-to-digital converter 201 performs quantization, when the second sub-stage analog-to-digital converter 201 completes quantization, the first sub-stage analog-to-digital converter 200 completes transmission of the generated residual signal to the residual amplifier 202 and transmission of the generated binary digital code to the redundant bit digital coding circuit 40, the first control switch and the second control switch are controlled to be turned off according to a preset time sequence, the third control switch and the fourth control switch are turned on, the residual signal generated by the second sub-stage analog-to-digital converter 201 is output to the residual amplifier 202, and the binary digital code of the second sub-stage analog-to-digital converter 201 is transmitted to the redundant bit digital coding circuit 40. The above operation is repeated for all subsequent cycles as well, and the operation mode of the other intermediate stage pipeline modules 20 is the same as that of the first intermediate stage pipeline module 20, with only a delay of one cycle in time compared to the previous intermediate stage pipeline module 20.
The pipelined analog-to-digital converter provided in this embodiment performs signal sampling and quantization alternately by multiplexing the same residual amplifier and controlling the first sub-stage analog-to-digital converter 200 and the second sub-stage analog-to-digital converter 201 in the intermediate stage pipeline module, so as to implement dual-channel parallel processing in the time domain, solve the problem of waiting for time between intermediate stage amplification and sampling of the sub-analog-to-digital converter in the whole successive approximation-pipelined analog-to-digital converter, and therefore, can allocate more time for the inter-stage amplification stage and the sampling stage in the same conversion period, implement dual-channel time domain interleaving work, and greatly improve the working efficiency.
The input end of the final analog-to-digital converter 30 is connected to the last residual amplifier 202, and the final analog-to-digital converter 30 is configured to receive the amplified residual signal output by the last residual amplifier 202, quantize the amplified residual signal, and output the quantized digital code.
The input end of the redundant bit digital encoding circuit 40 is respectively connected to the output end of each first sub-stage analog-to-digital converter 200, the output end of each second sub-stage analog-to-digital converter 201 and the output end of the final-stage analog-to-digital converter 30, the output end of the redundant bit digital encoding circuit 40 is the output end of the partially interleaved high-speed successive approximation-pipelined analog-to-digital converter, and the redundant bit digital encoding circuit 40 is configured to receive the quantized digital codes from each first sub-stage analog-to-digital converter 200, each second sub-stage analog-to-digital converter 201 and the final-stage analog-to-digital converter 30, and encode all the received quantized digital codes to output a multi-bit binary digital code, where the multi-bit binary digital code corresponds to an analog differential input signal, and in this embodiment, the redundant bit digital encoding circuit 40 adopts an existing circuit structure.
In this embodiment, the partially interleaved high-speed successive approximation-pipeline analog-to-digital converter includes two intermediate stage pipeline modules 20, a final stage analog-to-digital converter 30, and a redundant bit digital encoding circuit 40. The two intermediate stage pipeline modules 20 are a first intermediate stage pipeline module and a second intermediate stage pipeline module, the first intermediate stage pipeline module collects analog differential input signals, quantizes the analog differential input signals, generates residual signals and quantized D1 bit digital codes, amplifies the residual signals, outputs the amplified residual signals to the second intermediate stage pipeline module, and the second intermediate stage pipeline module quantizes and amplifies the received residual signals again to generate quantized D2 bit digital codes and outputs amplified residual signals. The final analog-to-digital converter 30 receives the amplified residual signal output by the second intermediate stage pipeline module, quantizes the residual signal and generates a quantized D3-bit digital code. The redundant bit digital encoding circuit 40 receives the D1 bit digital code, the D2 bit digital code and the D3 bit digital code, and outputs the d1+d2+d3-2 bit digital code after encoding and conversion, in this embodiment, each intermediate stage pipeline module 20 and the final stage analog-to-digital converter 30 output the same quantized bit number, that is, the values of D1, D2 and D3 are the same.
According to the partial interleaving high-speed successive approximation-pipeline analog-to-digital converter provided by the embodiment, each intermediate stage pipeline module 20 adopts a working mode of two-channel time domain interleaving, and amplification is realized in parallel between two channels, so that multiplexing of a residual error amplifier is realized, a working mode of two-channel parallel sampling-quantization-amplification is realized, compared with the traditional successive approximation analog-to-digital converter with a two-channel structure, the working efficiency is improved, the whole area and the power consumption of a circuit are effectively reduced, and hardware expenditure caused by using a one-step multi-bit technology is saved. In addition, by designing the plurality of intermediate stage pipeline modules 20, the same quantization bit number of the analog-to-digital converter of each pipeline sub-stage is realized, the complexity of circuit design is reduced, and the replicability of the circuit modules is improved.
Example two
Referring to fig. 2, fig. 2 is a schematic diagram of another partially-interleaved high-speed successive approximation-pipeline analog-to-digital converter according to an embodiment of the present invention, and based on the first embodiment, the partially-interleaved high-speed successive approximation-pipeline analog-to-digital converter further includes a front-end Sample-and-Hold Circuit (S/H) 10, wherein an output end of the front-end Sample-and-Hold Circuit 10 is connected to an input end of the first sub-stage analog-to-digital converter 200 and an input end of the second sub-stage analog-to-digital converter 201 of the first mid-stage pipeline module 20, respectively, and the front-end Sample-and-Hold Circuit 10 is configured to collect analog differential input signals and output the collected analog differential input signals to the first mid-stage pipeline module 20 as a signal source of the mid-stage pipeline module 20.
The circuit structure of the front-end sample-and-hold circuit 10 is an existing circuit structure, and in this embodiment, the front-end sample-and-hold circuit 10 is a bootstrap switch-type sample-and-hold circuit. The partial interleaving high-speed successive approximation-pipelined analog-to-digital converter provided in this embodiment, the front-end sample-and-hold circuit 10 can collect and hold the analog differential input signal, and the analog differential input signal in the holding stage is stable, so that the stable analog differential input signal is output to the mid-stage pipeline module 20, the sampling error of the mid-stage pipeline module 20 due to clock deviation is reduced, and the time domain interleaving error caused by the influence of non-ideal factors such as clock deviation and mismatch between channels is greatly reduced.
Referring to fig. 3, fig. 3 is a schematic diagram of an operation timing sequence of an intermediate stage pipeline module according to an embodiment of the present invention, each intermediate stage pipeline module 20 is represented as an operation mode of a two-phase clock when viewed from the outside of the pipeline stage, because the time domain of the sampling phase of the second sub-stage analog-to-digital converter 201 is combined with the time domain of the amplifying phase of the first sub-stage analog-to-digital converter 200 by using a partial time domain interleaving technology, so that the operation mode of each intermediate stage pipeline module 20 is only switched between two phases, namely, the sampling/amplifying phase and the quantizing phase, and the operation efficiency is improved compared with the operation mode of the conventional three phase switching of the sampling phase, the amplifying phase and the quantizing phase.
In addition, as can be seen from the overall operation time sequence of the first stage intermediate stage pipeline module 20, the first sub-stage analog-to-digital converter 200, the second sub-stage analog-to-digital converter 201 and the residual amplifier 202 sample, quantize and amplify through the partial time domain interleaving technology, so that the effect of parallel amplification of the residual signals output by the first sub-stage analog-to-digital converter 200 and the second sub-stage analog-to-digital converter 201 through the residual amplifier 202 is achieved, and multiplexing of the residual amplifier 202 is achieved.
Referring to fig. 4, fig. 4 is a diagram illustrating a comparison of operation timing sequences of a conventional single-channel successive approximation-pipelined analog-to-digital converter and a partially-interleaved high-speed successive approximation-pipelined analog-to-digital converter according to the present invention. The working modes of the successive approximation-pipeline analog-to-digital converter with the traditional single-channel structure are three phase switching working modes of sampling, amplifying phase and quantizing phase, and after the analog-to-digital converter of the intermediate-stage pipeline module finishes quantizing, the capacitor array of the analog-to-digital converter needs to wait for a period of time for amplifying differential signals, so that the next sampling work cannot be directly carried out. The partial interleaving high-speed successive approximation-pipeline analog-to-digital converter provided by the invention uses a partial time domain interleaving technology, wherein one channel of the analog-to-digital converter of the intermediate stage pipeline module amplifies differential signals after quantization is completed, and the other channel can simultaneously sample signals. The waiting time of the amplifying phase is saved, and the combination of sampling and amplifying on two phase time domains is realized. Therefore, compared with the traditional single-channel structure, one third of working time is saved, and the working efficiency of the device is greatly improved.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. Modifications made by those skilled in the art without departing from the spirit of the invention should be considered as falling within the scope of the invention.
Claims (6)
1. A partially interleaved high-speed successive approximation-pipeline analog-to-digital converter is characterized by comprising a plurality of intermediate stage pipeline modules (20), a final stage analog-to-digital converter (30) and a redundant bit digital coding circuit (40), wherein,
the plurality of intermediate stage pipeline modules (20) are sequentially connected in series, the plurality of intermediate stage pipeline modules (20) are used for collecting analog differential input signals, quantizing the analog differential input signals, generating residual difference signals and quantized digital codes, amplifying the residual difference signals, outputting the quantized digital codes and amplified residual difference signals, wherein each intermediate stage pipeline module (20) comprises a first sub-stage analog-to-digital converter (200), a second sub-stage analog-to-digital converter (201), a first control switch, a second control switch, a third control switch, a fourth control switch and a residual difference amplifier (202), the first control switch is connected between the first sub-stage analog-to-digital converter (200) and the residual difference amplifier (202), the second control switch is connected between the first sub-stage analog-to-digital converter (200) and the redundant bit digital coding circuit (40), and the third control switch is connected between the second sub-stage analog-to-digital converter (201) and the residual difference amplifier (202), and the fourth control switch is connected between the second sub-stage analog-to-digital converter (201) and the redundant bit digital coding circuit (40); the output end of the residual difference amplifier (202) in the former intermediate stage pipeline module (20) is respectively connected with the input end of the first sub-stage analog-to-digital converter (200) and the input end of the second sub-stage analog-to-digital converter (201) in the latter intermediate stage pipeline module (20);
the input end of the final-stage analog-to-digital converter (30) is connected with the output end of the last residual amplifier (202), and the final-stage analog-to-digital converter (30) is used for receiving the amplified residual signal, quantizing the amplified residual signal and outputting quantized digital codes;
the input end of the redundant bit digital coding circuit (40) is respectively connected with the output end of each first sub-stage analog-to-digital converter (200), the output end of each second sub-stage analog-to-digital converter (201) and the output end of the final stage analog-to-digital converter (30), and is used for receiving quantized digital codes from each intermediate stage pipeline module (20) and the final stage analog-to-digital converter (30) and outputting all the received quantized digital codes after coding conversion.
2. The partially interleaved high speed successive approximation-pipeline analog to digital converter according to claim 1, further comprising a front end sample and hold circuit (10), wherein an output of the front end sample and hold circuit (10) is connected to an input of a first sub-stage analog to digital converter (200) and an input of a second sub-stage analog to digital converter (201) in a first intermediate stage pipeline module (20), respectively, for collecting analog differential input signals and outputting the analog differential input signals as a signal source for the plurality of intermediate stage pipeline modules (20).
3. The partially interleaved high speed successive approximation-pipelined analog to digital converter according to claim 1, wherein the first sub-stage analog to digital converter (200), the second sub-stage analog to digital converter (201) and the final stage analog to digital converter (30) are identical in structure.
4. A partially interleaved high speed successive approximation-pipelined analog to digital converter according to claim 3 wherein the first sub-stage analog to digital converter (200), the second sub-stage analog to digital converter (201) and the final stage analog to digital converter (30) are all successive approximation analog to digital converters.
5. The partially interleaved high speed successive approximation to pipeline analog to digital converter according to claim 2 wherein the front end sample and hold circuit (10) is a bootstrap switch mode sample and hold circuit.
6. The partially interleaved high speed successive approximation to pipeline analog to digital converter according to any of claims 1 to 5, wherein in each intermediate stage pipeline module (20),
when the quantization of the first sub-level analog-to-digital converter (200) is completed, the first control switch and the second control switch are controlled to be turned on according to a preset time sequence, and the third control switch and the fourth control switch are controlled to be turned off;
when the first sub-level analog-to-digital converter (200) finishes transmitting the generated residual signal to the residual amplifier (202) and transmits the generated binary digital code to the redundant bit digital coding circuit (40), the first control switch and the second control switch are controlled to be closed according to the preset time sequence, and the third control switch and the fourth control switch are controlled to be opened.
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