CN116191601A

CN116191601A - Path management system and method suitable for charging chip

Info

Publication number: CN116191601A
Application number: CN202310011351.1A
Authority: CN
Inventors: 鲍小亮; 范思强; 杨康
Original assignee: Xinhe Electronics Shanghai Co ltd
Current assignee: Xinhe Electronics Shanghai Co ltd
Priority date: 2023-01-05
Filing date: 2023-01-05
Publication date: 2023-05-30

Abstract

The embodiment of the invention provides a path management system and a path management method suitable for a charging chip, which are characterized in that in the process of changing load current Iload, a current control loop and a voltage control loop are utilized to sequentially control a fourth power tube switch Q4, charging current Ichg is maintained to charge reference current Ichg_reg through the current control loop, conversion output voltage Vsys is maintained to conversion output reference voltage Vsys_reg through the voltage control loop, and simultaneously, the regulation and control of a PWM control module are combined, so that the output current IL of an inductor L, the input end current Ibus of a first power tube switch Q1 and the input end voltage Vbus are respectively maintained in respective preset ranges. The load is effectively and dynamically tracked through collection of the charging current Ichg and the conversion output voltage Vsys, and efficient adjustment of the charging current Ichg is achieved in the load current Iload change process so as to meet load requirements.

Description

Path management system and method suitable for charging chip

Technical Field

The embodiment of the invention relates to the technical field of charging management, in particular to a path management system and method suitable for a charging chip.

Background

With the development of information technology, today, a charging scheme of a mobile phone generally includes a main charging chip (Charger) and a fast charging chip to cooperate to realize full-phase charging management of a Battery (Battery) from low to full. In the main charging chip, as shown in fig. 1, the system structure can transmit the input terminal voltage Vbus (generally 5V/9V/12V) to the chip port through the type-c interface, and then realize charging management through a buck circuit 03. The charging path in fig. 1 includes four large N-type power transistors, which are a first power transistor switch Q1, a second power transistor switch Q2, a third power transistor switch Q3, and a fourth power transistor switch Q4, respectively. The function of the first power tube switch Q1 is to prevent the charging voltage VBAT from flowing backward to the input terminal, and also to enable the voltage Vbus of the input terminal to be clamped to be higher than 2V when the voltage Vbus of the input terminal is negative, and to prevent the negative voltage from flowing into the voltage terminal (PMID) of the adapter. The second power tube switch Q2 and the third power tube switch Q3 are connected to form a main switch SW of the buck circuit, and the converted output voltage Vsys of the buck circuit can be used as a power supply of the mobile phone system and can charge the rechargeable battery 04 through the fourth power tube switch Q4. The fourth power transistor switch Q4 is integrated inside the main charging chip (Charger), and when the charging voltage VBAT is lower than the conversion output minimum voltage Vsysmin (typically 3.5V), the conversion output voltage Vsys is maintained to be 180mV higher than the conversion output minimum voltage (typically vsysmin+180 mv=3.68v) in order to supply power to the load (mobile phone system), and a register is configured to regulate the charging current on the fourth power transistor switch Q4. When the charging voltage VBAT is greater than the conversion output minimum voltage Vsysmin (typically 3.5V), the fourth power transistor switch Q4 is fully on, and the conversion output voltage Vsys is passed through to the rechargeable battery 04, so as to realize high-efficiency high-current charging (typically 2 to 3A).

When the charging voltage VBAT is smaller than the conversion output minimum voltage vsysin (typically 3.5V), the conversion output voltage Vsys needs to be maintained above the typical value 3.68V to supply the charging current Ichg to the rechargeable battery 04. Since the output current IL of the inductor L is equal to the sum of the charging current Ichg and the load current Iload (il=ichg+iload), wherein the magnitude of the load current Iload is variable, when the load current Iload is relatively small, the output current IL of the inductor L is not large enough to trigger the current limiting protection and the voltage limiting protection of the buck conversion circuit (in order to protect the input voltage Vbus from being pulled dead, the current limiting threshold value Iindpm and the voltage limiting threshold value Vindpm are generally set, the current limiting protection is triggered when the input current Ibus is greater than the current limiting threshold value Iindpm, and the voltage limiting protection is triggered when the input voltage Vbus is less than the voltage limiting threshold value Vindpm. When the load current Iload is relatively large, the current limiting protection or voltage limiting protection is easy to trigger, the conversion output voltage Vsys is reduced at the moment, an adjusting mechanism is needed at the moment to ensure that the conversion output voltage Vsys is not pulled too low by adjusting the charging current Ichg so as to ensure the power supply of the mobile phone system load, and otherwise, the mobile phone is restarted. This protection mechanism is referred to as the DPM (dynamic power management ) mechanism.

Disclosure of Invention

Therefore, the embodiment of the invention provides a path management system and a path management method suitable for a charging chip, so as to solve the technical problem of how to realize high-efficiency regulation and control of charging current Ichg in the change process of load current Iload so as to meet the load demand.

In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:

according to a first aspect of an embodiment of the present invention, an embodiment of the present application provides a path management system suitable for a charging chip, the system including:

the first power tube switch Q1 is used for externally connecting a power supply;

the second power tube switch Q2 and the third power tube switch Q3 are used for being combined and connected at the output end of the first power tube switch Q1 to form a main switch SW;

the buck conversion circuit is used for carrying out buck conversion on the input voltage through the combination of the first capacitor C1 and the inductor L under the control of the main switch SW so as to supply power for a load and a rechargeable battery; the control end of the main switch SW is connected with a PWM control module for carrying out current-limiting regulation and voltage-limiting regulation and control on the duty ratio D of the buck conversion circuit;

the fourth power tube switch Q4 is arranged on a branch of the rechargeable battery and used for controlling the charging current Ichg;

The current control loop is used for accessing the grid electrode of the fourth power tube switch Q4, generating a first debugging signal by using charging current Ichg, and maintaining the charging current Ichg to a preset charging reference current Ichg_reg;

and a voltage control loop, configured to be connected to the gate of the fourth power transistor switch Q4, generate a second charging current control signal by using a transformed output voltage Vsys, and maintain the transformed output voltage Vsys to a preset transformed output reference voltage vsys_reg.

Further, a second capacitor C2 is connected between the fourth power tube switch Q4 and the rechargeable battery, and an output terminal of the second capacitor C2 is grounded.

Further, the current control loop includes: a first differential voltage signal input circuit, a first current control amplifier ea11, a differential current signal transmission circuit, a second current control amplifier ea12, and a current control switch tube MN6; the first differential voltage signal input circuit and the first current control amplifier ea11 are arranged in a preset low voltage domain, and the second current control amplifier ea12 and the current control switch tube MN6 are arranged in a first preset high voltage domain;

the first differential voltage signal input circuit includes: the charging mirror current source, the charging mirror reference current source, the first resistor R1 and the second resistor R2; the charging mirror current source is connected in series with the first resistor R1 to form a first branch, the charging mirror reference current source is connected in series with the second resistor R2 to form a second branch, and the first current control amplifier ea11 is respectively connected into the first branch and the second branch through a first comparison signal input end and a second comparison signal input end;

The differential current signal transmission circuit includes: the first differential current switch tube MN1, the second differential current switch tube MP1, the third differential current switch tube MN2 and the fourth differential current switch tube MP2; the first comparison signal output end of the first current control amplifier ea11 is connected to the second comparison signal input end of the second current control amplifier ea12 through the first differential current switching tube MN1 and the second differential current switching tube MP1 in sequence, and the second comparison signal output end of the first current control amplifier ea11 is connected to the first comparison signal input end of the second current control amplifier ea12 through the third differential current switching tube MN2 and the fourth differential current switching tube MP2 in sequence;

the gate of the current control switch tube MN6 is connected to the single-ended voltage signal output end of the second current control amplifier ea12, the drain of the current control switch tube MN6 is connected to the gate of the fourth power tube switch Q4, and the drain of the current control switch tube MN6 is connected to the first current source Ibp1.

Further, the current control loop further includes: a first mueller compensation circuit, the first mueller compensation circuit comprising: the single-ended voltage signal output end of the second current control amplifier ea12 is connected to an access point between the drain electrode of the current control switch tube MN6 and the first current source Ibp1 through the third capacitor CC1 and the third resistor RC1 in sequence.

Further, generating a first debug signal by using a charging current Ichg, maintaining the charging current Ichg to a preset charging reference current ichg_reg, including:

collecting charging current Ichg in real time and obtaining charging mirror voltage Vsns_ichg through the first branch;

obtaining a charging mirror image reference voltage Vref_ichg through the second branch by utilizing the charging reference current Ichg_reg;

inputting the charging image voltage Vsns_ichg and the charging image reference voltage Vref_ichg as first differential voltage signals to a first current control amplifier ea11, and converting the first differential voltage signals into differential current signals i1 and i2;

inputting the differential current signals i1 and i2 to a second current control amplifier ea12, and converting the differential current signals into a first single-ended voltage vo1;

comparing the charging image voltage vsns_ichg with the charging image reference voltage vref_ichg at the first current control amplifier ea 11; the first single-ended voltage vo1 is low if the charging image voltage vsns_ichg is greater than the charging image reference voltage vref_ichg; the first single-ended voltage vo1 is high if the charging image voltage vsns_ichg is less than the charging image reference voltage vref_ichg;

controlling the current control switching tube MN6 by using the first single-ended voltage vo1; if the first single-ended voltage vo1 is low, the current control switch tube MN6 is not turned on, and the charging current Ichg is not pulled down; if the first single-ended voltage vo1 is high, the current control switch tube MN6 is turned on, and pulls down the charging current Ichg.

Further, the voltage control loop includes: the voltage control amplifier ea2, the first voltage control switch tube MN4, the second voltage control switch tube MP3, the third voltage control switch tube MN5, the fourth voltage control switch tube MN7 and the fifth voltage control switch tube MP4; the voltage control amplifier ea2 is arranged in a preset low-voltage domain, and the first voltage control switch tube MN4 is arranged in a second preset high-voltage domain; the single-ended voltage signal output end of the voltage control amplifier ea2 is connected to the grid electrode of the second voltage control switch tube MP3 through the first voltage control switch tube MN 4; the drain electrode of the second voltage control switch tube MP3 is connected to an access point between the current control switch tube MN6 and the fourth power tube switch Q4 through the grid electrode of the third voltage control switch tube MN 5; the fourth voltage control switch tube MN7 is connected to a connection point between the second voltage control switch tube MP3 and the third voltage control switch tube MN 5; the fifth voltage control switch tube MP4 is connected to the source of the third voltage control switch tube MN 5.

Further, the voltage control loop further includes: a second mueller compensation circuit, the second mueller compensation circuit comprising: the fourth capacitor CC2 and the sixth voltage control switch tube MN3, where the sixth voltage control switch tube MN3 is disposed in a preset low voltage domain, the single-ended voltage signal output end of the voltage control amplifier ea2 is connected to the source electrode of the sixth voltage control switch tube MN3 through the fourth capacitor CC2, and the gate electrode of the sixth voltage control switch tube MN3 is connected to an access point between the first voltage control switch tube MN4 and the second voltage control switch tube MP 3.

Further, generating the second charging current control signal using the transformed output voltage Vsys, maintaining the transformed output voltage Vsys to a preset transformed output reference voltage vsys_reg, includes:

the transformed output voltage Vsys is acquired in real time, using a second mirrored scaling factor k ₂ Processing the converted output voltage Vsys to obtain a converted output mirror voltage vsys_sns;

using a second mirrored scaling factor k ₂ Processing the conversion output reference voltage Vsys_reg to obtain a conversion output mirror image reference voltage Vref_sysreg;

inputting the converted output mirror voltage vsys_sns and the converted output mirror reference voltage vref_sysreg as second differential voltage signals to a voltage control amplifier ea2, and converting the second differential voltage signals into a second single-ended voltage vo2;

comparing the transformed output mirror voltage vsys_sns with the transformed output mirror reference voltage vref_sysreg at the voltage control amplifier ea 2; the second single-ended voltage vo2 is low if the transformed output mirror voltage vsys_sns is greater than the transformed output mirror reference voltage vref_sysreg; the second single-ended voltage vo2 is high if the transformed output mirror voltage vsys_sns is less than the transformed output mirror reference voltage vref_sysreg;

Controlling the first voltage-controlled switching tube MN4 with the second single-ended voltage vo 2; when the second single-ended voltage vo2 is low, the first voltage control switch tube MN4 is not turned on, and the voltage cycle control voltage Vgate1a is pulled up to a high voltage preset threshold vpp by using a second current source Ibp 2; when the second single-ended voltage vo2 is high, the first voltage-controlled switch tube MN4 is turned on, the voltage circulation control voltage Vgate1a is pulled down by the second single-ended voltage vo2, and the voltage circulation control voltage Vgate1a is lower than a high-voltage preset threshold vpp;

controlling the second voltage control switch tube MP3 by using the voltage circulation control voltage Vgate1 a;

when the voltage circulation control voltage Vgate1a is close to the high voltage preset threshold vpp, the second voltage control switch tube MP3 is not conducted, the current of the third current source Ibn2 flows to the fourth voltage control switch tube MN7, the third voltage control switch tube MN5 is not conducted, and the charging current Ichg is not pulled down;

when the voltage cycle control voltage Vgate1a is lower than the high voltage preset threshold vpp, the second voltage control switch tube MP3 is turned on, the third voltage control switch tube MN5 is turned on, the source voltage of the third voltage control switch tube MN5 is clamped to the second preset voltage by the fifth voltage cycle control switch tube MP4, and the charging current Ichg is pulled down.

Further, during the load current Iload changing process, the current control loop and the voltage control loop sequentially control the fourth power tube switch Q4, and the output current IL of the inductor L, the input end current Ibus and the input end voltage Vbus of the first power tube switch Q1 are respectively maintained in respective preset ranges in combination with the regulation and control of the PWM control module.

According to a second aspect of the embodiments of the present invention, an embodiment of the present application provides a path management method suitable for a charging chip, where the method includes:

the first power tube switch Q1 is externally connected with a power supply;

the second power tube switch Q2 and the third power tube switch Q3 are combined and connected at the output end of the first power tube switch Q1 to form a main switch SW;

under the control of the main switch SW, the buck conversion circuit performs buck conversion on the input voltage through the combination of the first capacitor C1 and the inductor L to supply power for a load and a rechargeable battery;

at the control end of the main switch SW, the PWM control module is used for carrying out current-limiting regulation and control and voltage-limiting regulation and control on the duty ratio D of the buck conversion circuit;

A current control loop is connected to the grid electrode of the fourth power tube switch Q4, a first debugging signal is generated by using charging current Ichg, and the charging current Ichg is maintained to a preset charging reference current Ichg_reg;

the voltage control loop is connected to the gate of the fourth power tube switch Q4, and generates a second charging current control signal by using the conversion output voltage Vsys, so as to maintain the conversion output voltage Vsys to a preset conversion output reference voltage vsys_reg.

Compared with the prior art, in the path management system and method suitable for the charging chip, in the load current Iload changing process, the current control loop and the voltage control loop are utilized to sequentially control the fourth power tube switch Q4, the charging current Ichg is maintained to the charging reference current ichg_reg through the current control loop, the conversion output voltage Vsys is maintained to the conversion output reference voltage vsys_reg through the voltage control loop, and meanwhile, the output current IL of the inductor L, the input end current Ibus of the first power tube switch Q1 and the input end voltage Vbus are respectively maintained in respective preset ranges by combining the regulation and control of the PWM control module. The load is effectively and dynamically tracked through collection of the charging current Ichg and the conversion output voltage Vsys, and efficient adjustment of the charging current Ichg is achieved in the load current Iload change process so as to meet load requirements.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It will be apparent to those of ordinary skill in the art that the drawings in the following description are exemplary only and that other implementations can be obtained from the extensions of the drawings provided without inventive effort.

The structures, proportions, sizes, etc. shown in the present specification are shown only for the purposes of illustration and description, and are not intended to limit the scope of the invention, which is defined by the claims, so that any structural modifications, changes in proportions, or adjustments of sizes, which do not affect the efficacy or the achievement of the present invention, should fall within the ambit of the technical disclosure.

Fig. 1 is a schematic diagram of a charging path of a path management system suitable for a charging chip according to an embodiment of the present invention;

fig. 2 is a schematic diagram of current and voltage variation trend of each node under charging adjustment combined by a DPM mechanism and a compensation mode of a charging chip according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a current control loop and a voltage control loop of a path management system for a charging chip according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a current control loop and a voltage control loop of a path management system for a charging chip according to another embodiment of the present invention;

fig. 5 is a schematic flow chart of a path management method suitable for a charging chip according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a current and voltage trend of each node in a load current slow change process according to a path management method suitable for a charging chip according to an embodiment of the present invention;

fig. 7 is a schematic diagram of current and voltage variation trend of each node in a fast load current change process according to a path management method suitable for a charging chip according to an embodiment of the present invention.

Detailed Description

Other advantages and advantages of the present invention will become apparent to those skilled in the art from the following detailed description, which, by way of illustration, is to be read in connection with certain specific embodiments, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

DPM (dynamic power management ) mechanisms primarily serve incoming requests by dynamically configuring the system with minimal moving parts to conserve power. In the embodiment of the present invention, the DPM mechanism is implemented by reducing the magnitude of the charging current Ichg to maintain the conversion output voltage Vsys at a preset value (vsysin+55mv). As shown in fig. 2, it is shown that as the load current Iload increases gradually, when the input current Ibus is smaller than the current limit threshold Iindpm and the current limit protection is not triggered, the charging current Ichg is equal to the charging reference current ichg_reg (register is configurable), and the transformed output voltage Vsys is equal to the transformed output voltage preset threshold Vsys0 (vsysin+180 mV, typically 3.68V). When the input current Ibus is greater than the current limit threshold Iindpm, the charging current Ichg gradually decreases from the charging reference current ichg_reg to 0 after the current limit protection is triggered, the input current Ibus is maintained at the current limit threshold Iindpm, and the transformed output voltage Vsys is equal to the transformed output reference voltage vsys_reg (vsysin+55 mV typically 3.55V).

If the load current Iload continues to increase, resulting in that the conversion output voltage Vsys cannot be maintained at the conversion output reference voltage vsys_reg after the charging current Ichg decreases to 0, the conversion output voltage Vsys falls below the charging voltage VBAT, and the fourth power transistor switch Q4 is fully opened to directly supply power to the load through the charging voltage VBAT, so as to ensure that the conversion output voltage Vsys does not fall, i.e., the compensation mode (supply) shown in fig. 2.

In order to achieve the above regulation of the charging current Ichg during the load current Iload change, referring to fig. 3, a current control loop is used to generate a first debug signal to control the current control loop switch tube MN01, and a voltage control loop is used to generate a second debug signal to control the voltageThe control loop switching tube MN02 generates a pull-down current to control the gate voltage Vgate of the fourth power tube switch Q4. Since the gate voltage Vgate of the fourth power transistor switch Q4 is equal to the sum of the charging voltage VBAT and the gate-source voltage vgs of the fourth power transistor switch Q4 (vgate=vbat+vgs), the fourth power transistor switch Q4 may be weak on or full on, so that the range of variation of the gate-source voltage vgs is between the soft on threshold voltage vthn and 5V, i.e. the gate access point gate of the fourth power transistor switch Q4 is a node of high voltage, both the current control loop and the voltage control loop are arranged in the high voltage domain (between the high voltage preset threshold vpp and the ground voltage vgnd) (as shown in fig. 3). The inputs to the current control loop are the charge image voltage vsns_ichg and the charge image reference voltage vref_ichg, vsns_ichg=ichg_sns·r1, vref_ichg=ichg_ref·r2, and ichg_sns·r1=ichg_ref·r2 after the current control loop is established, so ichg_sns=ichg_ref·r2/R1. And ichg_sns=ichg·k1 (k 1 is a first preset mirror scaling factor), ichg=ichg_sns/k1=ichg_ref· (R2/R1)/k 1, so that maintaining the charging current Ichg to a preset target value can be achieved by adjusting ichg_ref. The inputs to the voltage control loop are a transformed output mirror voltage vsys_sns and a transformed output mirror reference voltage vref_sysreg, vsys_sns=k2·vsys (k) ₂ For the second mirror scaling factor), when the voltage control loop is established, vsys_sns=vref_sysreg, i.e. vsys=vref_sysreg/k 2, such that maintaining the transformed output voltage Vsys to the design threshold (i.e. the transformed output reference voltage vsys_reg, vsys_reg=vsysmin+55 mV, typically 3.55V) can be achieved by adjusting vref_sysreg. When Vsys>When Vssysin+55mV, the voltage control loop cannot intervene, the voltage control loop switch tube MN02 is not conducted, and at the moment, the current control loop acts to realize preset current charging. When the load current Iload becomes large, if Vsys<Vsysmin+55mV, the voltage control loop will intervene, the voltage control loop switch tube MN02 turns on, and the voltage control loop will modulate the gate voltage Vgate of the fourth power tube switch Q4 to reduce the charging current Ichg, thereby ensuring that the transformed output voltage Vsys is maintained to the design threshold (i.e., vsys_reg=vsysmin+55 mV).

In the arrangement design of the current control loop and the voltage control loop shown in fig. 3, the current control loop amplifier ea1 and the voltage control loop amplifier ea2 are both disposed in a high voltage domain (between a high voltage preset threshold vpp, which is a voltage realized by a charge pump (charge pump), up to 10V (vpp=vbat+5v), and the power supply capability thereof is effective. Most devices in the layout design of the current control loop and the voltage control loop are made in a high-voltage domain, and a large number of high-voltage devices are needed, which is finally unacceptable in area.

In the above-described layout design of the current control loop and the voltage control loop shown in fig. 3, from the stability point of view, the current control loop is considered to be a control node gate1 formed by the current control loop switch tube MN01 and a control node gate formed by the fourth power tube switch Q4 alone, and the third capacitor CC1 and the third resistor RC1 may be introduced to make the miller compensation, but a capacitor (cap) capable of resisting high voltage is required to make the third capacitor CC1, which results in an excessive occupation of area. From the voltage control loop, it contains the following three poles: the output node gate2 of the voltage control loop amplifier ea2, the control node gate formed by the fourth power transistor switch Q4, and the node sys formed at the output of the buck converter circuit. The greatest difficulty here is the pole position of the node sys, which is related to the output impedance of the buck converter (buck circuit) and the load impedance rload, which is as low as 13Hz when the output current IL of the inductor L is small (about 60 mA) and the first capacitance C1 is equal to 200 uF. Since it is not possible to push all internal nodes far enough, only the main pole can be made inside, in order to compensate the low frequency pole of node sys, a large fourth capacitor CC2 (about 50 pf) and fourth resistor RC2 (4M ohm) are needed for the voltage control loop switch MN02 to introduce zero compensation. In addition, when the output current IL of the inductor L is large, the ac small signal resistance of the node sys is small, so the gain from the control node gate formed by the fourth power transistor switch Q4 to the node sys is small, and the miller compensation is not effective, and only the miller compensation can be performed between the node gate2 formed by the input terminal of the voltage control loop switch MN02 and the control node gate formed by the fourth power transistor switch Q4, which has the consequence that the fourth capacitor CC2 must be a high-voltage device, but such a large capacitor requirement is difficult to be achieved by a high-voltage device, and the node gate capacitor is about 250pf, so that the driving current Ibp of the node gate must be required to be large to push away the pole at the node gate, and as a result, the charge pump circuit for generating the high-voltage preset threshold vpp needs a large area to be achieved.

In summary, the above-described layout design of the current control loop and the voltage control loop as shown in fig. 3 is not cost-effective from the standpoint of area and power consumption.

The aim of the embodiment of the invention is that: how to realize the efficient regulation control of the charging current Ichg in the load current Iload changing process so as to meet the load requirement. More specifically, on the one hand, the dual-loop operation of the fourth power transistor switch Q4 is realized with a sufficiently small high-voltage device and relatively small power consumption as much as possible. On the other hand, a relatively simple compensation mode is used for realizing stable operation of the current control loop and the voltage control loop.

As shown in fig. 1 and fig. 4, an embodiment of the present application provides a path management system suitable for a charging chip, including: the power supply circuit comprises a first power tube switch Q1, a second power tube switch Q2, a third power tube switch Q3, a fourth power tube switch Q4, a buck conversion circuit 3, a current control loop 7 and a voltage control loop 8.

The first power tube switch Q1 is used for externally connecting a power supply 1; the second power tube switch Q2 and the third power tube switch Q3 are used for being combined and connected at the output end of the first power tube switch Q1 to form a main switch SW; the buck conversion circuit 3 is used for performing buck conversion on the input voltage through the combination of the first capacitor C1 and the inductor L under the control of the main switch SW to supply power to the load 5 and the rechargeable battery 4; the control end of the main switch SW3 is connected with a PWM control module 2 for carrying out current-limiting regulation and voltage-limiting regulation on the duty ratio D of the buck conversion circuit 3; the fourth power tube switch Q4 is arranged on a branch of the rechargeable battery and used for controlling the charging current Ichg; the current control loop 7 is used for accessing a grid electrode of the fourth power tube switch Q4, generating a first charging current control signal by using the charging current Ichg, and maintaining the charging current Ichg to a preset charging reference current Ichg_reg; the voltage control loop 8 is connected to the gate of the fourth power transistor Q4, and generates a second charging current control signal by using the transformed output voltage Vsys, so as to maintain the transformed output voltage Vsys to a preset transformed output reference voltage vsys_reg.

Further, a second capacitor C2 is connected between the fourth power tube switch Q4 and the rechargeable battery 4, and an output terminal of the second capacitor C2 is grounded.

Further, the current control loop 7 includes: a first differential voltage signal input circuit 71, a first current control amplifier ea11, a differential current signal transmission circuit 72, a second current control amplifier ea12, and a current control switching transistor MN6.

The first differential voltage signal input circuit 71 and the first current control amplifier ea11 are disposed in a preset low voltage domain, and in the embodiment of the present invention, the voltage in the preset low voltage domain may be 5V, and the second current control amplifier ea12 and the current control switching tube MN6 are disposed in a first preset high voltage domain.

In the embodiment of the present invention, the first preset high voltage domain means that the power supply and the ground terminal are between vpp and VBAT, so that the second current control amplifier ea12 can be made by using a high voltage isolated low voltage device. The current control switch MN6 is disposed in the first preset high voltage domain.

The first differential voltage signal input circuit 71 includes: a charge mirror current source 711, a charge mirror reference current source 712, a first resistor R1, and a second resistor R2. The charging image current source 711 is connected in series with the first resistor R1, and a connection point between the charging image current source 711 and the first resistor R1 is connected to a first comparison signal input terminal of the first current control amplifier ea 11. The charging mirror reference current source 712 is connected in series with the second resistor R2, and a connection point between the charging mirror reference current source 712 and the second resistor R2 is connected to the second comparison signal input terminal of the first current control amplifier ea 11.

The differential current signal transmission circuit 72 includes: the first differential current switching tube MN1, the second differential current switching tube MP1, the third differential current switching tube MN2, and the fourth differential current switching tube MP2. The first contrast signal output end of the first current control amplifier ea11 is connected to the second contrast signal input end of the second current control amplifier ea12 through the first differential current switching tube MN1 and the second differential current switching tube MP1 in sequence. The second comparison signal output end of the first current control amplifier ea11 is connected to the first comparison signal input end of the second current control amplifier ea12 through a third differential current switching tube MN2 and a fourth differential current switching tube MP2 in sequence. The gates of the first differential current switching tube MN1 and the third differential current switching tube MN2 are connected to the first preset bias voltage vbn, and the gates of the second differential current switching tube MP1 and the fourth differential current switching tube MP2 are connected to the second preset bias voltage vbp. The first differential current switching tube MN1 and the third differential current switching tube MN2 may protect the first current control amplifier ea11 from breakdown, and the second differential current switching tube MP1 and the fourth differential current switching tube MP2 may protect the second current control amplifier ea12 from breakdown.

The grid electrode of the current control switch tube MN6 is connected to the single-ended voltage signal output end of the second current control amplifier ea12, the drain electrode of the current control switch tube MN6 is connected to the grid electrode of the fourth power tube switch Q4, and the drain electrode of the current control switch tube MN6 is connected with a first current source Ibp1.

The current control loop 7 further includes: the first miller compensation circuit 73, the first miller compensation circuit 73 includes: the single-ended voltage signal output end of the second current control amplifier ea12 is connected to an access point between the drain electrode of the current control switch tube MN6 and the first current source Ibp1 through the third capacitor CC1 and the third resistor RC1 in sequence.

In the embodiment of the invention, the signal input end of the second current control amplifier ea12 is made by using an isolated low-voltage device (the first current control amplifier ea 11), so that the second current control amplifier ea12 works in a high-voltage domain, the area of a charge pump is saved, and the driving power consumption of a current control loop is reduced.

Further, the voltage control loop 8 includes: the voltage control amplifier ea2, the first voltage control switch tube MN4, the second voltage control switch tube MP3, the third voltage control switch tube MN5, the fourth voltage control switch tube MN7, and the fifth voltage control switch tube MP4. The voltage control amplifier ea2 is disposed in a preset low voltage domain, and the first voltage control switch tube MN4 is disposed in a second preset high voltage domain.

The grid electrode of the first voltage control switch tube MN4 is connected to the single-ended voltage signal output end of the voltage control amplifier ea2, the drain electrode of the first voltage control switch tube MN4 is connected to the grid electrode of the second voltage control switch tube MP3, and the drain electrode of the first voltage control switch tube MN4 is connected with a second current source Ibp2.

The drain electrode of the second voltage control switch tube MP3 is connected with a third current source Ibn2, the connection point between the drain electrode of the second voltage control switch tube MP3 and the third current source Ibn2 is connected to the gate electrode of the third voltage control switch tube MN5, the connection point between the drain electrode of the second voltage control switch tube MP3 and the gate electrode of the third voltage control switch tube MN5 is connected to the fourth voltage control switch tube MN7, and the source electrode of the second voltage control switch tube MP3 and the drain electrode of the third voltage control switch tube MN5 are both connected to the access point between the source electrode of the current control switch tube MN6 and the gate electrode of the fourth power tube switch Q4.

As described above, the second voltage control switch tube MP3 and the third voltage control switch tube MN5 form a super source follower (supper source follower), and in the embodiment of the present invention, the super source follower is used as an isolation stage of the amplifier formed by the voltage control amplifier ea2 of the voltage control loop and the first voltage control switch tube MN 4. Therefore, the Miller compensation of the current control loop and the compensation circuit of the voltage control loop can not interfere with each other, and the pole at the gate node gate of the fourth power tube switch Q4 can be effectively pushed away to high frequency, so that the stability of the voltage control loop is facilitated. The output of the voltage controlled amplifier ea2 of the low voltage domain can also be effectively transferred to the high voltage domain.

The source of the third voltage control switch tube MN5 is connected to the source of the fifth voltage control switch tube MP4, the drain of the fifth voltage control switch tube MP4 is grounded, and the gate of the fifth voltage control switch tube MP4 is connected to the first preset voltage (VBAT-2 vthn, vthn is the soft-on threshold voltage).

The voltage control loop 8 further comprises: the second miller compensation circuit 81, the second miller compensation circuit 81 comprising: fourth capacitor CC2, sixth voltage control switch MN3. The sixth voltage control switch tube MN3 is disposed in a preset low voltage domain, the single-ended voltage signal output end of the voltage control amplifier ea2 is connected to the source of the sixth voltage control switch tube MN3 through the fourth capacitor CC2, and the gate of the sixth voltage control switch tube MN3 is connected to an access point between the drain of the first voltage control switch tube MN4 and the gate of the second voltage control switch tube MP 3.

Compared with the prior art, in the path management system suitable for the charging chip, in the load current Iload changing process, the current control loop and the voltage control loop are utilized to sequentially control the fourth power tube switch Q4, the charging current Ichg is maintained to the charging reference current ichg_reg through the current control loop, the conversion output voltage Vsys is maintained to the conversion output reference voltage vsys_reg through the voltage control loop, and meanwhile, the output current IL of the inductor L, the input end current Ibus of the first power tube switch Q1 and the input end voltage Vbus are respectively maintained in respective preset ranges by combining the regulation and control of the PWM control module. The load is effectively and dynamically tracked through collection of the charging current Ichg and the conversion output voltage Vsys, and efficient adjustment of the charging current Ichg is achieved in the load current Iload change process so as to meet load requirements.

Corresponding to the above disclosed path management system suitable for the charging chip, the embodiment of the invention also discloses a path management method suitable for the charging chip. The following describes in detail a path management method suitable for a charging chip disclosed in the embodiment of the present invention in conjunction with a path management system suitable for a charging chip described above.

As shown in fig. 5, the following provides a detailed description of specific steps of a path management method suitable for a charging chip in an embodiment of the present application.

The first power tube switch Q1 is externally connected with a power supply; the second power tube switch Q2 and the third power tube switch Q3 are combined and connected at the output end of the first power tube switch Q1 to form a main switch SW; under the control of a main switch SW, the buck conversion circuit 3 performs buck conversion on the input voltage through the combination of the first capacitor C1 and the inductor L to supply power for the load 5 and the rechargeable battery 4; at the control end of the main switch SW, the PWM control module 2 is used for carrying out current-limiting regulation and voltage-limiting regulation on the duty ratio D of the buck conversion circuit 3; the fourth power tube switch Q4 is arranged on a branch of the rechargeable battery 4 and is used for controlling the charging current Ichg; the grid electrode of the fourth power tube switch Q4 is connected by the current control loop 7, a first charging current control signal is generated by using the charging current Ichg, and the charging current Ichg is maintained to a preset charging reference current Ichg_reg; the voltage control loop 8 is connected to the gate of the fourth power transistor Q4, and generates a second charging current control signal by using the converted output voltage Vsys, so as to maintain the converted output voltage Vsys to a preset converted output reference voltage vsys_reg.

Further, the PWM control module 2 performs current-limiting regulation and voltage-limiting regulation on the duty ratio D of the buck conversion circuit 3, which specifically includes: when the input current Ibus is greater than the current limiting threshold Iindpm or the input voltage Vbus is less than the voltage limiting threshold Vindpm, the duty cycle D of the buck conversion circuit is limited, and the input current Ibus is maintained to the current limiting threshold Iindpm or the input voltage Vbus is maintained to the voltage limiting threshold Vindpm.

Further, the first charging current control signal is generated by using the charging current Ichg, and the charging current Ichg is maintained to a preset charging reference current ichg_reg, which specifically includes the following steps: collecting charging current Ichg in real time by a charging mirror current source 711; using a first predetermined mirror scaling factor k ₁ Processing the charging current Ichg to obtain a charging mirror current Ichg_sns; the calculation formula of the charging mirror current ichg_sns is as follows: ichg_sns=k ₁ Ichg; charging mirror current Ichg_sns flows through a first resistor R1 to obtain charging mirror voltage Vsns_ichg; the calculation formula of the charging mirror voltage vsns_ichg is as follows: vsns_ichg=ichg_sns·r1. Using a first predetermined mirror scaling factor k by the charge mirror reference current source 712 ₁ Processing the charging reference current Ichg_reg to obtain a charging mirror image reference current Ichg_ref; the calculation formula of the charging mirror image reference current ichg_ref is as follows: ichg_ref=k ₁ Ichg_reg; the charging mirror image reference current Ichg_ref flows through a second resistor R2 to obtain a charging mirror image reference voltage Vref_ichg; by a means ofThe calculation formula of the charging mirror reference voltage Vref_ichg is as follows: vref_ichg=ichg_ref·r1. The charge image voltage vsns_ichg and the charge image reference voltage vref_ichg are input as first differential voltage signals to the first current control amplifier ea11, and converted into differential current signals i1 and i2. The differential current signals i1 and i2 are input to the second current control amplifier ea12, and converted into a first single-ended voltage vo1. Comparing the charging image voltage vsns_ichg with the charging image reference voltage vref_ichg at the first current control amplifier ea 11; if the charging image voltage Vsns_ichg is greater than the charging image reference voltage Vref_ichg, the first single-ended voltage vo1 is low; the first single-ended voltage vo1 is high if the charging image voltage vsns_ichg is less than the charging image reference voltage vref_ichg. The first single-ended voltage vo1 is utilized to control the current control switch tube MN 6; if the first single-ended voltage vo1 is low, the current control switch tube MN6 is not conducted, and the charging current IChg is not pulled down; if the first single-ended voltage vo1 is high, the current control switching transistor MN6 is turned on, and the charging current Ichg is pulled down.

Further, the second charging current control signal is generated by using the transformed output voltage Vsys, and the transformed output voltage Vsys is maintained to a preset transformed output reference voltage vsys_reg, which specifically includes the steps of: the transformed output voltage Vsys is acquired in real time, using a second mirrored scaling factor k ₂ Processing the transformed output voltage Vsys to obtain a transformed output mirror voltage vsys_sns; the calculation formula of the conversion output mirror voltage vsys_sns is as follows: vsys_sns=k ₂ Vsys. Using a second mirrored scaling factor k ₂ The transformed output reference voltage vsys_reg is processed to obtain a transformed output mirror reference voltage vref_sysreg. The converted output mirror voltage vsys_sns and the converted output mirror reference voltage vref_sysreg are input as a second differential voltage signal to the voltage control amplifier ea2, and converted into a second single-ended voltage vo2. Comparing the transformed output mirror voltage vsys_sns with the transformed output mirror reference voltage vref_sysreg at the voltage control amplifier ea 2; if the transformed output mirror voltage vsys_sns is greater than the transformed output mirror reference voltage vref_sysreg, the second single-ended voltage vo2 is low; if the output mirror is transformedThe voltage vsys_sns is smaller than the transformed output mirror reference voltage vref_sysreg, and the second single-ended voltage vo2 is high. The second single-ended voltage vo2 is utilized to control the first voltage control switch tube MN 4; when the second single-ended voltage vo2 is low, the first voltage-controlled switch tube MN4 is not turned on, and the voltage-cycling control voltage Vgate1a is pulled up to the high-voltage preset threshold vpp by using the second current source Ibp 2; when the second single-ended voltage vo2 is high, the first voltage-controlled switch tube MN4 is turned on, the voltage-cycling control voltage Vgate1a is pulled down by the second single-ended voltage vo2, and the voltage-cycling control voltage Vgate1a is lower than the high-voltage preset threshold vpp. The second voltage control switching tube MP3 is controlled by the voltage cycle control voltage Vgate1 a. When the voltage cycle control voltage Vgate1a is close to the high voltage preset threshold vpp, the second voltage control switch tube MP3 is not turned on, the current of the third current source Ibn2 flows to the fourth voltage control switch tube MN7, the third voltage control switch tube MN5 is not turned on, and the charging current Ichg is not pulled down. When the voltage cycle control voltage Vgate1a is lower than the high voltage preset threshold vpp, the second voltage control switch tube MP3 is turned on, the third voltage control switch tube MN5 is turned on, the source voltage of the fifth voltage cycle control switch tube MP4 is connected to the first preset voltage (VBAT-2 vthn, vthn is the soft-on threshold voltage), the source voltage of the third voltage control switch tube MN5 is clamped to the second preset voltage (VBAT-vthn, vthn is the soft-on threshold voltage) by the fifth voltage cycle control switch tube MP4, and the charging current Ichg is pulled down.

In the embodiment of the invention, the source voltage of the third voltage control switch tube MN5 is clamped to the second preset voltage, so that the structures of the second voltage control switch tube MP3 and the third voltage control switch tube MN5 can be realized by using low-voltage tubes, the area is reduced, and the wider working range (1V-3.8V) of VBAT can be satisfied by using the lower driving voltage of the second voltage control switch tube MP 3.

In the process of changing the load current Iload, the current control loop 7 and the voltage control loop 8 sequentially control the fourth power tube switch Q4, and the output current IL of the inductor L, the input end current Ibus and the input end voltage Vbus of the first power tube switch Q1 are respectively maintained in respective preset ranges by combining the regulation and control of the PWM control module 2.

Compared with the prior art, in the path management method suitable for the charging chip, in the load current Iload changing process, the current control loop and the voltage control loop are utilized to sequentially control the fourth power tube switch Q4, the charging current Ichg is maintained to the charging reference current ichg_reg through the current control loop, the conversion output voltage Vsys is maintained to the conversion output reference voltage vsys_reg through the voltage control loop, and meanwhile, the output current IL of the inductor L, the input end current Ibus of the first power tube switch Q1 and the input end voltage Vbus are respectively maintained in respective preset ranges by combining the regulation and control of the PWM control module. The load is effectively and dynamically tracked through collection of the charging current Ichg and the conversion output voltage Vsys, and efficient adjustment of the charging current Ichg is achieved in the load current Iload change process so as to meet load requirements.

Specifically, through the path management strategy according to the embodiment of the invention, in the process of slowly changing the load current, the operation of switching from the current control loop 7 to the voltage control loop 8 is realized, and then the operation of switching from the voltage control loop 8 to the current control loop 7 is realized.

Specifically, when the load current Iload is slowly increased from 0, the current control loop is triggered to pull down the charging current Ichg, the charging current Ichg is maintained to the charging reference current ichg_reg, the voltage control loop does not pull down the charging current Ichg, and the output current IL and the input end current Ibus of the inductor L are slowly increased; triggering the current limiting protection of the main switch SW until the input end current Ibus is increased to a current limiting threshold value Iindpm, and reducing the duty ratio D of the buck conversion circuit to maintain the input end current Ibus at the current limiting threshold value Iindpm; after the output current IL of the inductor L is slowly increased to the inductor output current upper limit value il_lim, the voltage control loop is triggered to pull down the charging current Ichg, the conversion output voltage Vsys is maintained to the conversion output reference voltage vsys_reg, the charging current Ichg is not pulled down by the current control loop, the load current Iload is slowly increased to the highest load current value iload_high, and the charging current Ichg is reduced to the first charging current threshold value Ichg1; the load current Iload is slowly reduced from the highest load current value iload_high, and the charging current Ichg is slowly increased; until the charging current Ichg increases to the charging reference current ichg_reg, triggering the current control loop to pull down the charging current Ichg, maintaining the charging current Ichg to the charging reference current ichg_reg, starting the rising of the conversion output voltage Vsys from the conversion output reference voltage vsys_reg, exiting the pulling down of the charging current Ichg by the voltage control loop until the rising of the conversion output voltage Vsys to the conversion output voltage preset threshold Vsys0, triggering the voltage limiting protection of the main switch SW, reducing the duty cycle D of the buck conversion circuit to maintain the conversion output voltage Vsys at the conversion output voltage preset threshold Vsys0, continuing the reduction of the load current Iload, gradually reducing the input end current Ibus from the current limiting threshold Iindpm, exiting the current limiting protection by the main switch SW, continuing the pulling down of the charging current Ichg, and maintaining the charging current Ichg to the charging reference current ichg_reg.

Referring to fig. 6, if vsns_ichg is less than vref_ichg, current control loop 7 is triggered to pull down Ichg to maintain Ichg to ichg_reg as Iload slowly increases from 0 before time t 0. At this time, il=ichg+iload, vsys=vsys0; as Iload increases gradually from 0, IL also increases gradually, and the output power (il·vsys0) of the buck converter circuit also increases. Therefore, ibus also increases slowly, vbus gradually decreases from the first input voltage threshold Vbus0 under the influence of the internal resistance of the power supply 1, and if the internal resistance of the power supply is small enough, it can be considered that the Vbus voltage change is small at this time, and the input power increase is mainly provided by the rise of Ibus current.

Until time t0, ibus increases to Iindpm, triggering current limiting protection of the main switch SW, decreasing the duty cycle D of the buck conversion circuit to maintain Ibus at Iindpm, IL continues to rise.

From time t0 to time t1, since Ibus is unchanged, the drive capability of the buck conversion circuit is limited, IL continues to rise as Iload increases, and Vsys voltage decreases. In this process, the voltage control loop 8 does not intervene since Vsys is always higher than vsys_reg. Until time t1, vsys decreases to vsys_reg, the voltage control loop is operated, vsys is maintained at vsys_reg by the voltage control loop, and IL rises to il_lim.

From time t1 to time t2, as Iload continues to increase, vsys remains unchanged, the voltage control loop gradually decreases the gate voltage Vgate of the fourth power transistor switch Q4 to decrease Ichg, and il=il_lim=ichg+iload is always true. Thus, the output power (il_lim·vsys_reg) and the input power (iindpm·vbus1, vbus1 being the second input voltage threshold) of the buck conversion circuit remain approximately equal.

From time t2 to time t3, as Iload gradually decreases from iload_high, vsys continues to remain unchanged, the voltage control loop gradually increases the gate voltage Vgate of Q4 to increase Ichg, and il=il_lim=ichg+iload is always true. Thus, the output power (il_lim·vsys_reg) and the input power (iindpm·vbus1, vbus1 being the second input voltage threshold) of the buck conversion circuit remain approximately equal. Until time t3, ichg increases to ichg_reg, and the current control loop starts the intervention operation.

Continuing from time t3 to time t4, if Iload is reduced, since the current control loop has been interposed, ichg remains unchanged, IL gradually decreases from il_lim, vsys begins to rise, and the voltage control loop is taken out of operation. Thus, the output power (il_lim·vsys_reg) and the input power (iindpm·vbus1, vbus1 being the second input voltage threshold) of the buck conversion circuit remain approximately equal. Until time t4, vsys rises to Vsys0, triggering voltage limiting protection of the main switch SW, vsys being maintained at Vsys0 by the buck converter circuit main loop.

Continuing from time t4 to time t5, if Iload, IL decreases, the output power of the buck converter circuit (il·vsys0) decreases gradually, the input power of the buck converter circuit decreases gradually, the corresponding Ibus decreases gradually from Iindpm, the current limiting protection of the main switch SW is out of operation, and the current control loop is always in operation, ichg=ichg_reg.

Specifically, referring to fig. 7, through the path management strategy according to the embodiment of the present invention, during the fast change of the load current, the switching from the operation of the current control loop 7 to the operation of the voltage control loop 8 is realized, and then the switching from the operation of the voltage control loop 8 to the operation of the current control loop 7 is realized.

Specifically, when the load current Iload does not reach the highest load current value iload_high, the voltage control loop does not pull down the charging current Ichg, and the current control loop pulls down the charging current Ichg to maintain the charging current Ichg to the charging reference current ichg_reg; when the load current Iload instantaneously increases from 0 to a highest load current value iload_high, triggering the current limiting protection of the main switch SW, reducing the duty ratio D of the buck conversion circuit to maintain the input end current Ibus at a current limiting threshold value Iindpm until the charging current Ichg is reduced to a first charging current threshold value Ichg1, starting to trigger the voltage control loop to pull down the charging current Ichg, reducing the charging current Ichg to a second charging current threshold value Ichg2, and simultaneously maintaining the conversion output voltage Vsys to a conversion output reference voltage vsys_reg, wherein the charging current Ichg is not pulled down by the current control loop; until the load current Iload is instantaneously reduced from the highest load current value iload_high to 0, the conversion output voltage Vsys rises back from the conversion output reference voltage vsys_reg to the conversion output voltage preset threshold Vsys0; the voltage control loop stops pulling down the charging current Ichg, the charging current Ichg increases rapidly until the charging current Ichg reaches the charging reference current ichg_reg, and the current control loop is triggered again to pull down the charging current Ichg, so that the charging current Ichg is maintained to the charging reference current ichg_reg.

Referring to fig. 7, before time t 0: the current control loop works normally, ichg=ichg_reg, iload=0, il=il0=ichg (IL 0 is the inductor output current lower limit value), vsys=vsys0, ibus=ibus 0 (Ibus 0 input current preset).

From time t0 to time t1, at time t0, iload is instantaneously increased from 0 to iload_high, IL (ichg+iload) is also instantaneously increased to il_lim0 (the first inductance output current preset value, il_lim0=ichg_reg+iload_high), thereby causing Ibus to quickly rise from Ibus0 to Iindpm, triggering current limiting protection of the buck conversion circuit, and reducing the duty ratio D of the buck conversion circuit to maintain Ibus unchanged at Iindpm. Then Vsys will drop from Vsys0, and as the compensation capacitance (fourth capacitance CC 2) is relatively large, the voltage control loop response is relatively slow, vsys will relatively fast decrease to a value tens of mV greater than vbat, thereby decreasing the gate voltage Vgate of the fourth power transistor switch Q4 to decrease Ichg to Ichg1 (first charging current threshold).

From time t1 to time t2, the voltage control loop is in the process of being established, approximately 1ms being required to establish an operating point for the miller capacitance (fourth capacitance CC 2).

After the voltage control loop is stably established from time t2 to time t3, the gate voltage Vgate of the fourth power transistor switch Q4 starts to be reduced to further reduce Ichg to Ichg2 (second charging current threshold), while Vsys gradually rises to vsys_reg, and a steady-state operating point is established.

After time t3, at time t3 Iload decreases rapidly from iload_high to 0, vsys increases rapidly, the voltage control loop is deactivated, and Vsys returns from vsys_reg to sys0. The voltage control loop no longer modulates the gate voltage Vgate of the fourth power transistor switch Q4, vgate rises rapidly, ichg increases until Ichg equals ichg_reg, and the current control loop re-intervenes, stabilizing Ichg at ichg_reg.

In the embodiment of the invention, the current control loop and the voltage control loop realize the path management of the charging chip by utilizing the fully-isolated low-voltage tube as much as possible, so as to realize the function of dynamic load tracking, and greatly save the area. The high-voltage domain and the low-voltage domain consume less than 50uA power consumption in total to drive the q4 current control loop and the q4 voltage control loop to work, and the high-voltage domain consumes less than 30uA power consumption to save the area of the charge pump as much as possible. The compensation mode utilizes simple Miller compensation, and a zero point is respectively introduced into the current control loop and the voltage control loop to compensate, so that the normal operation of the capacitance of a large area of 20 uF-200 uF and a wide charging area of 60 mA-5A can be satisfied.

While the invention has been described in detail in the foregoing general description and specific examples, it will be apparent to those skilled in the art that modifications and improvements can be made thereto. Accordingly, such modifications or improvements may be made without departing from the spirit of the invention and are intended to be within the scope of the invention as claimed.

Claims

1. A path management system for a charging chip, the system comprising:

2. A path management system for a charging chip according to claim 1, wherein a second capacitor C2 is connected between the fourth power transistor switch Q4 and the rechargeable battery, and an output terminal of the second capacitor C2 is grounded.

3. A path management system for a charging chip as claimed in claim 2, wherein the current control loop comprises: a first differential voltage signal input circuit, a first current control amplifier ea11, a differential current signal transmission circuit, a second current control amplifier ea12, and a current control switch tube MN6; the first differential voltage signal input circuit and the first current control amplifier ea11 are arranged in a preset low voltage domain, and the second current control amplifier ea12 and the current control switch tube MN6 are arranged in a first preset high voltage domain;

4. A path management system for a charging chip as claimed in claim 3, wherein said current control loop further comprises: a first mueller compensation circuit, the first mueller compensation circuit comprising: the single-ended voltage signal output end of the second current control amplifier ea12 is connected to an access point between the drain electrode of the current control switch tube MN6 and the first current source Ibp1 through the third capacitor CC1 and the third resistor RC1 in sequence.

5. The path management system for a charging chip of claim 4, wherein generating a first debug signal using a charging current Ichg to maintain the charging current Ichg to a preset charging reference current ichg_reg comprises:

Controlling the current control switching tube MN6 by using the first single-ended voltage vo 1; if the first single-ended voltage vo1 is low, the current control switch tube MN6 is not turned on, and the charging current Ichg is not pulled down; if the first single-ended voltage vo1 is high, the current control switch tube MN6 is turned on, and pulls down the charging current Ichg.

6. A path management system for a charging chip as claimed in claim 5, wherein said voltage control loop comprises: the voltage control amplifier ea2, the first voltage control switch tube MN4, the second voltage control switch tube MP3, the third voltage control switch tube MN5, the fourth voltage control switch tube MN7 and the fifth voltage control switch tube MP4; the voltage control amplifier ea2 is arranged in a preset low-voltage domain, and the first voltage control switch tube MN4 is arranged in a second preset high-voltage domain; the single-ended voltage signal output end of the voltage control amplifier ea2 is connected to the grid electrode of the second voltage control switch tube MP3 through the first voltage control switch tube MN 4; the drain electrode of the second voltage control switch tube MP3 is connected to an access point between the current control switch tube MN6 and the fourth power tube switch Q4 through the grid electrode of the third voltage control switch tube MN 5; the fourth voltage control switch tube MN7 is connected to a connection point between the second voltage control switch tube MP3 and the third voltage control switch tube MN 5; the fifth voltage control switch tube MP4 is connected to the source of the third voltage control switch tube MN 5.

7. A path management system for a charging chip as claimed in claim 6, wherein said voltage control loop further comprises: a second mueller compensation circuit, the second mueller compensation circuit comprising: the fourth capacitor CC2 and the sixth voltage control switch tube MN3, where the sixth voltage control switch tube MN3 is disposed in a preset low voltage domain, the single-ended voltage signal output end of the voltage control amplifier ea2 is connected to the source electrode of the sixth voltage control switch tube MN3 through the fourth capacitor CC2, and the gate electrode of the sixth voltage control switch tube MN3 is connected to an access point between the first voltage control switch tube MN4 and the second voltage control switch tube MP 3.

8. The path management method for a charging chip according to claim 7, wherein generating the second charging current control signal using the transformed output voltage Vsys maintains the transformed output voltage Vsys to a preset transformed output reference voltage vsys_reg, comprising:

controlling the first voltage-controlled switching tube MN4 with the second single-ended voltage vo2; when the second single-ended voltage vo2 is low, the first voltage control switch tube MN4 is not turned on, and the voltage cycle control voltage Vgate1a is pulled up to a high voltage preset threshold vpp by using a second current source Ibp 2; when the second single-ended voltage vo2 is high, the first voltage-controlled switch tube MN4 is turned on, the voltage circulation control voltage Vgate1a is pulled down by the second single-ended voltage vo2, and the voltage circulation control voltage Vgate1a is lower than a high-voltage preset threshold vpp;

9. The path management system for a charging chip according to claim 1, wherein during a load current Iload change process, the current control loop and the voltage control loop sequentially control the fourth power tube switch Q4, and in combination with regulation of the PWM control module, the output current IL of the inductor L, the input current Ibus and the input voltage Vbus of the first power tube switch Q1 are respectively maintained within respective preset ranges.

10. A path management method suitable for a charging chip, the method comprising:

the first power tube switch Q1 is externally connected with a power supply;